* [PATCH v2 2/3] arm64: dts: qcom: sc7180: align TLMM pin configuration with DT schema
2022-10-13 18:46 [PATCH v2 1/3] arm64: dts: qcom: sc7180-trogdor-homestar: fully configure secondary I2S pins Krzysztof Kozlowski
@ 2022-10-13 18:46 ` Krzysztof Kozlowski
2022-10-14 17:50 ` Doug Anderson
2022-10-13 18:47 ` [PATCH v2 3/3] dt-bindings: pinctrl: qcom,sc7180: convert to dtschema Krzysztof Kozlowski
2022-10-14 17:51 ` [PATCH v2 1/3] arm64: dts: qcom: sc7180-trogdor-homestar: fully configure secondary I2S pins Doug Anderson
2 siblings, 1 reply; 8+ messages in thread
From: Krzysztof Kozlowski @ 2022-10-13 18:46 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Linus Walleij,
Rob Herring, Krzysztof Kozlowski, linux-arm-msm, linux-gpio,
devicetree, linux-kernel
Cc: Krzysztof Kozlowski, Doug Anderson
DT schema expects TLMM pin configuration nodes to be named with
'-state' suffix and their optional children with '-pins' suffix.
Merge subnodes named 'pinconf' and 'pinmux' into one entry, add function
where missing (required by bindings for GPIOs) and reorganize overriding
pins by boards.
Split the SPI and UART configuration into separate nodes
1. SPI (MOSI, MISO, SCLK), SPI chip-select, SPI chip-select via GPIO,
2. UART per each pin: TX, RX and optional CTS/RTS.
This allows each board to customize them easily without adding any new
nodes.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
Changes since v1:
1. Split SPI and UART nodes, after discussion with Doug.
Not tested on hardware.
Cc: Doug Anderson <dianders@chromium.org>
---
arch/arm64/boot/dts/qcom/sc7180-idp.dts | 236 +++----
.../boot/dts/qcom/sc7180-trogdor-coachz.dtsi | 36 +-
.../dts/qcom/sc7180-trogdor-homestar.dtsi | 47 +-
.../dts/qcom/sc7180-trogdor-kingoftown-r0.dts | 16 +-
.../dts/qcom/sc7180-trogdor-kingoftown.dtsi | 8 +-
.../boot/dts/qcom/sc7180-trogdor-lazor.dtsi | 16 +-
.../dts/qcom/sc7180-trogdor-mrbland-rev0.dtsi | 25 +-
.../boot/dts/qcom/sc7180-trogdor-mrbland.dtsi | 72 +-
.../qcom/sc7180-trogdor-parade-ps8640.dtsi | 32 +-
.../boot/dts/qcom/sc7180-trogdor-pazquel.dtsi | 8 +-
.../boot/dts/qcom/sc7180-trogdor-pompom.dtsi | 14 +-
.../qcom/sc7180-trogdor-quackingstick.dtsi | 56 +-
.../arm64/boot/dts/qcom/sc7180-trogdor-r1.dts | 8 +-
.../dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi | 16 +-
.../qcom/sc7180-trogdor-wormdingler-rev0.dtsi | 25 +-
.../dts/qcom/sc7180-trogdor-wormdingler.dtsi | 72 +-
arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 652 +++++++-----------
arch/arm64/boot/dts/qcom/sc7180.dtsi | 597 ++++++++--------
18 files changed, 786 insertions(+), 1150 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
index 9dee131b1e24..70fd9ff8dfa2 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts
+++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
@@ -481,287 +481,261 @@ pinconf {
};
&qspi_clk {
- pinconf {
- pins = "gpio63";
- bias-disable;
- };
+ bias-disable;
};
&qspi_cs0 {
- pinconf {
- pins = "gpio68";
- bias-disable;
- };
+ bias-disable;
};
&qspi_data01 {
- pinconf {
- pins = "gpio64", "gpio65";
-
- /* High-Z when no transfers; nice to park the lines */
- bias-pull-up;
- };
+ /* High-Z when no transfers; nice to park the lines */
+ bias-pull-up;
};
&qup_i2c2_default {
- pinconf {
- pins = "gpio15", "gpio16";
- drive-strength = <2>;
+ drive-strength = <2>;
- /* Has external pullup */
- bias-disable;
- };
+ /* Has external pullup */
+ bias-disable;
};
&qup_i2c4_default {
- pinconf {
- pins = "gpio115", "gpio116";
- drive-strength = <2>;
+ drive-strength = <2>;
- /* Has external pullup */
- bias-disable;
- };
+ /* Has external pullup */
+ bias-disable;
};
&qup_i2c7_default {
- pinconf {
- pins = "gpio6", "gpio7";
- drive-strength = <2>;
+ drive-strength = <2>;
- /* Has external pullup */
- bias-disable;
- };
+ /* Has external pullup */
+ bias-disable;
};
&qup_i2c9_default {
- pinconf {
- pins = "gpio46", "gpio47";
- drive-strength = <2>;
+ drive-strength = <2>;
- /* Has external pullup */
- bias-disable;
- };
+ /* Has external pullup */
+ bias-disable;
};
-&qup_uart3_default {
- pinconf-cts {
- /*
- * Configure a pull-down on CTS to match the pull of
- * the Bluetooth module.
- */
- pins = "gpio38";
- bias-pull-down;
- };
+&qup_uart3_cts {
+ /*
+ * Configure a pull-down on CTS to match the pull of
+ * the Bluetooth module.
+ */
+ bias-pull-down;
+};
- pinconf-rts {
- /* We'll drive RTS, so no pull */
- pins = "gpio39";
- drive-strength = <2>;
- bias-disable;
- };
+&qup_uart3_rts {
+ /* We'll drive RTS, so no pull */
+ drive-strength = <2>;
+ bias-disable;
+};
- pinconf-tx {
- /* We'll drive TX, so no pull */
- pins = "gpio40";
- drive-strength = <2>;
- bias-disable;
- };
+&qup_uart3_tx {
+ /* We'll drive TX, so no pull */
+ drive-strength = <2>;
+ bias-disable;
+};
- pinconf-rx {
- /*
- * Configure a pull-up on RX. This is needed to avoid
- * garbage data when the TX pin of the Bluetooth module is
- * in tri-state (module powered off or not driving the
- * signal yet).
- */
- pins = "gpio41";
- bias-pull-up;
- };
+&qup_uart3_rx {
+ /*
+ * Configure a pull-up on RX. This is needed to avoid
+ * garbage data when the TX pin of the Bluetooth module is
+ * in tri-state (module powered off or not driving the
+ * signal yet).
+ */
+ bias-pull-up;
};
-&qup_uart8_default {
- pinconf-tx {
- pins = "gpio44";
- drive-strength = <2>;
- bias-disable;
- };
+&qup_uart8_tx {
+ drive-strength = <2>;
+ bias-disable;
+};
- pinconf-rx {
- pins = "gpio45";
- drive-strength = <2>;
- bias-pull-up;
- };
+&qup_uart8_rx {
+ drive-strength = <2>;
+ bias-pull-up;
};
-&qup_spi0_default {
- pinconf {
- pins = "gpio34", "gpio35", "gpio36", "gpio37";
- drive-strength = <2>;
- bias-disable;
- };
+&qup_spi0_spi {
+ drive-strength = <2>;
+ bias-disable;
};
-&qup_spi6_default {
- pinconf {
- pins = "gpio59", "gpio60", "gpio61", "gpio62";
- drive-strength = <2>;
- bias-disable;
- };
+&qup_spi0_cs {
+ drive-strength = <2>;
+ bias-disable;
};
-&qup_spi10_default {
- pinconf {
- pins = "gpio86", "gpio87", "gpio88", "gpio89";
- drive-strength = <2>;
- bias-disable;
- };
+&qup_spi6_spi {
+ drive-strength = <2>;
+ bias-disable;
};
-&tlmm {
- qup_uart3_sleep: qup-uart3-sleep {
- pinmux {
- pins = "gpio38", "gpio39",
- "gpio40", "gpio41";
- function = "gpio";
- };
+&qup_spi6_cs {
+ drive-strength = <2>;
+ bias-disable;
+};
+
+&qup_spi10_spi {
+ drive-strength = <2>;
+ bias-disable;
+};
+
+&qup_spi10_cs {
+ drive-strength = <2>;
+ bias-disable;
+};
- pinconf-cts {
+&tlmm {
+ qup_uart3_sleep: qup-uart3-sleep-state {
+ cts-pins {
/*
* Configure a pull-down on CTS to match the pull of
* the Bluetooth module.
*/
pins = "gpio38";
+ function = "gpio";
bias-pull-down;
};
- pinconf-rts {
+ rts-pins {
/*
* Configure pull-down on RTS. As RTS is active low
* signal, pull it low to indicate the BT SoC that it
* can wakeup the system anytime from suspend state by
* pulling RX low (by sending wakeup bytes).
*/
- pins = "gpio39";
- bias-pull-down;
+ pins = "gpio39";
+ function = "gpio";
+ bias-pull-down;
};
- pinconf-tx {
+ tx-pins {
/*
* Configure pull-up on TX when it isn't actively driven
* to prevent BT SoC from receiving garbage during sleep.
*/
pins = "gpio40";
+ function = "gpio";
bias-pull-up;
};
- pinconf-rx {
+ rx-pins {
/*
* Configure a pull-up on RX. This is needed to avoid
* garbage data when the TX pin of the Bluetooth module
* is floating which may cause spurious wakeups.
*/
pins = "gpio41";
+ function = "gpio";
bias-pull-up;
};
};
- sdc1_on: sdc1-on {
- pinconf-clk {
+ sdc1_on: sdc1-on-state {
+ clk-pins {
pins = "sdc1_clk";
bias-disable;
drive-strength = <16>;
};
- pinconf-cmd {
+ cmd-pins {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <10>;
};
- pinconf-data {
+ data-pins {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <10>;
};
- pinconf-rclk {
+ rclk-pins {
pins = "sdc1_rclk";
bias-pull-down;
};
};
- sdc1_off: sdc1-off {
- pinconf-clk {
+ sdc1_off: sdc1-off-state {
+ clk-pins {
pins = "sdc1_clk";
bias-disable;
drive-strength = <2>;
};
- pinconf-cmd {
+ cmd-pins {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <2>;
};
- pinconf-data {
+ data-pins {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <2>;
};
- pinconf-rclk {
+ rclk-pins {
pins = "sdc1_rclk";
bias-pull-down;
};
};
- sdc2_on: sdc2-on {
- pinconf-clk {
+ sdc2_on: sdc2-on-state {
+ clk-pins {
pins = "sdc2_clk";
bias-disable;
drive-strength = <16>;
};
- pinconf-cmd {
+ cmd-pins {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <10>;
};
- pinconf-data {
+ data-pins {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <10>;
};
- pinconf-sd-cd {
+ sd-cd-pins {
pins = "gpio69";
+ function = "gpio";
bias-pull-up;
drive-strength = <2>;
};
};
- sdc2_off: sdc2-off {
- pinconf-clk {
+ sdc2_off: sdc2-off-state {
+ clk-pins {
pins = "sdc2_clk";
bias-disable;
drive-strength = <2>;
};
- pinconf-cmd {
+ cmd-pins {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <2>;
};
- pinconf-data {
+ data-pins {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <2>;
};
- pinconf-sd-cd {
+ sd-cd-pins {
pins = "gpio69";
+ function = "gpio";
bias-pull-up;
drive-strength = <2>;
};
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi
index 7ee407f7b6bb..8b8ea8af165d 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi
@@ -181,23 +181,15 @@ &sound_multimedia0_codec {
/* PINCTRL - modifications to sc7180-trogdor.dtsi */
&en_pp3300_dx_edp {
- pinmux {
- pins = "gpio67";
- };
-
- pinconf {
- pins = "gpio67";
- };
+ pins = "gpio67";
};
&ts_reset_l {
- pinconf {
- /*
- * We want reset state by default and it will be up to the
- * driver to disable this when it's ready.
- */
- output-low;
- };
+ /*
+ * We want reset state by default and it will be up to the
+ * driver to disable this when it's ready.
+ */
+ output-low;
};
/* PINCTRL - board-specific pinctrl */
@@ -327,16 +319,10 @@ &tlmm {
"DP_HOT_PLUG_DET",
"EC_IN_RW_ODL";
- dmic_clk_en: dmic_clk_en {
- pinmux {
- pins = "gpio83";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio83";
- drive-strength = <8>;
- bias-pull-up;
- };
+ dmic_clk_en: dmic-clk-en-state {
+ pins = "gpio83";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi
index bfab67f4a7c9..c66568a882b3 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi
@@ -180,36 +180,19 @@ &wifi {
/* PINCTRL - modifications to sc7180-trogdor.dtsi */
&en_pp3300_dx_edp {
- pinmux {
- pins = "gpio67";
- };
-
- pinconf {
- pins = "gpio67";
- };
+ pins = "gpio67";
};
&sec_mi2s_active{
- pinmux {
- pins = "gpio49", "gpio50", "gpio51", "gpio52";
- function = "mi2s_1";
- };
-
- pinconf {
- pins = "gpio49", "gpio50", "gpio51", "gpio52";
- drive-strength = <2>;
- bias-pull-down;
- };
+ pins = "gpio49", "gpio50", "gpio51", "gpio52";
};
&ts_reset_l {
- pinconf {
- /*
- * We want reset state by default and it will be up to the
- * driver to disable this when it's ready.
- */
- output-low;
- };
+ /*
+ * We want reset state by default and it will be up to the
+ * driver to disable this when it's ready.
+ */
+ output-low;
};
/* PINCTRL - board-specific pinctrl */
@@ -339,16 +322,10 @@ &tlmm {
"DP_HOT_PLUG_DET",
"EC_IN_RW_ODL";
- en_pp3300_touch: en-pp3300-touch {
- pinmux {
- pins = "gpio87";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio87";
- drive-strength = <2>;
- bias-disable;
- };
+ en_pp3300_touch: en-pp3300-touch-state {
+ pins = "gpio87";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r0.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r0.dts
index 1a62e8d435ab..3abd6222fe46 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r0.dts
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r0.dts
@@ -29,16 +29,10 @@ &pp3300_fp_tp {
};
&tlmm {
- en_fp_rails: en-fp-rails {
- pinmux {
- pins = "gpio74";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio74";
- drive-strength = <2>;
- bias-disable;
- };
+ en_fp_rails: en-fp-rails-state {
+ pins = "gpio74";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dtsi
index 74f0e07ea5cf..4156ad6dbd96 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dtsi
@@ -87,13 +87,7 @@ &wifi {
/* PINCTRL - modifications to sc7180-trogdor.dtsi */
&en_pp3300_dx_edp {
- pinmux {
- pins = "gpio67";
- };
-
- pinconf {
- pins = "gpio67";
- };
+ pins = "gpio67";
};
/* PINCTRL - board-specific pinctrl */
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi
index 002663d752da..269007d73162 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi
@@ -75,21 +75,13 @@ &wifi {
/* PINCTRL - modifications to sc7180-trogdor.dtsi */
&trackpad_int_1v8_odl {
- pinmux {
- pins = "gpio58";
- };
-
- pinconf {
- pins = "gpio58";
- };
+ pins = "gpio58";
};
&ts_reset_l {
- pinconf {
- /* This pin is not connected on -rev0, pull up to park. */
- /delete-property/bias-disable;
- bias-pull-up;
- };
+ /* This pin is not connected on -rev0, pull up to park. */
+ /delete-property/bias-disable;
+ bias-pull-up;
};
/* PINCTRL - board-specific pinctrl */
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0.dtsi
index 7bc8402c018e..f4c1f3813664 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0.dtsi
@@ -24,30 +24,13 @@ &v1p8_mipi {
/* PINCTRL - modifications to sc7180-trogdor-mrbland.dtsi */
&avdd_lcd_en {
- pinmux {
- pins = "gpio80";
- };
-
- pinconf {
- pins = "gpio80";
- };
+ pins = "gpio80";
};
&mipi_1800_en {
- pinmux {
- pins = "gpio81";
- };
-
- pinconf {
- pins = "gpio81";
- };
+ pins = "gpio81";
};
-&vdd_reset_1800 {
- pinmux {
- pins = "gpio76";
- };
- pinconf {
- pins = "gpio76";
- };
+&vdd_reset_1800 {
+ pins = "gpio76";
};
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland.dtsi
index 97cba7f8064f..5e563655baec 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland.dtsi
@@ -160,13 +160,7 @@ pp3300_disp_on: &pp3300_dx_edp {
*/
tp_en: &en_pp3300_dx_edp {
- pinmux {
- pins = "gpio85";
- };
-
- pinconf {
- pins = "gpio85";
- };
+ pins = "gpio85";
};
/* PINCTRL - board-specific pinctrl */
@@ -296,55 +290,31 @@ &tlmm {
"DP_HOT_PLUG_DET",
"EC_IN_RW_ODL";
- avdd_lcd_en: avdd-lcd-en {
- pinmux {
- pins = "gpio88";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio88";
- drive-strength = <2>;
- bias-disable;
- };
+ avdd_lcd_en: avdd-lcd-en-state {
+ pins = "gpio88";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
};
- avee_lcd_en: avee-lcd-en {
- pinmux {
- pins = "gpio21";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio21";
- drive-strength = <2>;
- bias-disable;
- };
+ avee_lcd_en: avee-lcd-en-state {
+ pins = "gpio21";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
};
- mipi_1800_en: mipi-1800-en {
- pinmux {
- pins = "gpio86";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio86";
- drive-strength = <2>;
- bias-disable;
- };
+ mipi_1800_en: mipi-1800-en-state {
+ pins = "gpio86";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
};
- vdd_reset_1800: vdd-reset-1800 {
- pinmux {
- pins = "gpio87";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio87";
- drive-strength = <2>;
- bias-disable;
- };
+ vdd_reset_1800: vdd-reset-1800-state {
+ pins = "gpio87";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-parade-ps8640.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-parade-ps8640.dtsi
index 6a84fba178d6..070b3acb7baa 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-parade-ps8640.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-parade-ps8640.dtsi
@@ -83,29 +83,17 @@ panel_in_edp: endpoint {
};
&tlmm {
- edp_brij_ps8640_rst: edp-brij-ps8640-rst {
- pinmux {
- pins = "gpio11";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio11";
- drive-strength = <2>;
- bias-disable;
- };
+ edp_brij_ps8640_rst: edp-brij-ps8640-rst-state {
+ pins = "gpio11";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
};
- en_pp3300_edp_brij_ps8640: en-pp3300-edp-brij-ps8640 {
- pinmux {
- pins = "gpio32";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio32";
- drive-strength = <2>;
- bias-disable;
- };
+ en_pp3300_edp_brij_ps8640: en-pp3300-edp-brij-ps8640-state {
+ pins = "gpio32";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi
index 56d787785fd5..d06cc4ea3375 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi
@@ -84,13 +84,7 @@ &pp3300_dx_edp {
};
&en_pp3300_dx_edp {
- pinmux {
- pins = "gpio67";
- };
-
- pinconf {
- pins = "gpio67";
- };
+ pins = "gpio67";
};
/* PINCTRL - board-specific pinctrl */
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi
index a7582fb547ee..6c5287bd27d6 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi
@@ -312,15 +312,9 @@ &tlmm {
"DP_HOT_PLUG_DET",
"EC_IN_RW_ODL";
- dmic_sel: dmic-sel {
- pinmux {
- pins = "gpio86";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio86";
- bias-pull-down;
- };
+ dmic_sel: dmic-sel-state {
+ pins = "gpio86";
+ function = "gpio";
+ bias-pull-down;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi
index 695b04fe7221..c1367999eafb 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi
@@ -147,13 +147,7 @@ pp3300_disp_on: &pp3300_dx_edp {
*/
tp_en: &en_pp3300_dx_edp {
- pinmux {
- pins = "gpio67";
- };
-
- pinconf {
- pins = "gpio67";
- };
+ pins = "gpio67";
};
/* PINCTRL - board-specific pinctrl */
@@ -283,42 +277,24 @@ &tlmm {
"DP_HOT_PLUG_DET",
"EC_IN_RW_ODL";
- lcd_rst: lcd-rst {
- pinmux {
- pins = "gpio87";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio87";
- drive-strength = <2>;
- bias-disable;
- };
+ lcd_rst: lcd-rst-state {
+ pins = "gpio87";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
};
- ppvar_lcd_en: ppvar-lcd-en {
- pinmux {
- pins = "gpio88";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio88";
- drive-strength = <2>;
- bias-disable;
- };
+ ppvar_lcd_en: ppvar-lcd-en-state {
+ pins = "gpio88";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
};
- pp1800_disp_on: pp1800-disp-on {
- pinmux {
- pins = "gpio86";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio86";
- drive-strength = <2>;
- bias-disable;
- };
+ pp1800_disp_on: pp1800-disp-on-state {
+ pins = "gpio86";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts
index bc097d1b1b23..671b3691f1bb 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts
@@ -63,13 +63,7 @@ &usb_hub_3_x {
/* PINCTRL - modifications to sc7180-trogdor.dtsi */
&trackpad_int_1v8_odl {
- pinmux {
- pins = "gpio58";
- };
-
- pinconf {
- pins = "gpio58";
- };
+ pins = "gpio58";
};
/* PINCTRL - board-specific pinctrl */
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi
index f869e6a343c1..65333709e529 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-ti-sn65dsi86.dtsi
@@ -76,16 +76,10 @@ panel_in_edp: endpoint {
};
&tlmm {
- edp_brij_irq: edp-brij-irq {
- pinmux {
- pins = "gpio11";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio11";
- drive-strength = <2>;
- bias-pull-down;
- };
+ edp_brij_irq: edp-brij-irq-state {
+ pins = "gpio11";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0.dtsi
index db29e0cba29d..7f272c6e95f6 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0.dtsi
@@ -24,30 +24,13 @@ &v1p8_mipi {
/* PINCTRL - modifications to sc7180-trogdor-wormdingler.dtsi */
&avdd_lcd_en {
- pinmux {
- pins = "gpio80";
- };
-
- pinconf {
- pins = "gpio80";
- };
+ pins = "gpio80";
};
&mipi_1800_en {
- pinmux {
- pins = "gpio81";
- };
-
- pinconf {
- pins = "gpio81";
- };
+ pins = "gpio81";
};
-&vdd_reset_1800 {
- pinmux {
- pins = "gpio76";
- };
- pinconf {
- pins = "gpio76";
- };
+&vdd_reset_1800 {
+ pins = "gpio76";
};
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi
index 6312108e8b3e..123989ba97e1 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi
@@ -222,13 +222,7 @@ pp3300_disp_on: &pp3300_dx_edp {
*/
tp_en: &en_pp3300_dx_edp {
- pinmux {
- pins = "gpio85";
- };
-
- pinconf {
- pins = "gpio85";
- };
+ pins = "gpio85";
};
/* PINCTRL - board-specific pinctrl */
@@ -358,55 +352,31 @@ &tlmm {
"DP_HOT_PLUG_DET",
"EC_IN_RW_ODL";
- avdd_lcd_en: avdd-lcd-en {
- pinmux {
- pins = "gpio88";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio88";
- drive-strength = <2>;
- bias-disable;
- };
+ avdd_lcd_en: avdd-lcd-en-state {
+ pins = "gpio88";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
};
- avee_lcd_en: avee-lcd-en {
- pinmux {
- pins = "gpio21";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio21";
- drive-strength = <2>;
- bias-disable;
- };
+ avee_lcd_en: avee-lcd-en-state {
+ pins = "gpio21";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
};
- mipi_1800_en: mipi-1800-en {
- pinmux {
- pins = "gpio86";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio86";
- drive-strength = <2>;
- bias-disable;
- };
+ mipi_1800_en: mipi-1800-en-state {
+ pins = "gpio86";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
};
- vdd_reset_1800: vdd-reset-1800 {
- pinmux {
- pins = "gpio87";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio87";
- drive-strength = <2>;
- bias-disable;
- };
+ vdd_reset_1800: vdd-reset-1800-state {
+ pins = "gpio87";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
index eae22e6e97c1..37abe131951c 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
@@ -880,7 +880,7 @@ &sdhc_2 {
};
&spi0 {
- pinctrl-0 = <&qup_spi0_cs_gpio_init_high>, <&qup_spi0_cs_gpio>;
+ pinctrl-0 = <&qup_spi0_cs_gpio_init_high>, <&qup_spi0_spi>;
cs-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
};
@@ -997,175 +997,141 @@ wifi-firmware {
/* PINCTRL - additions to nodes defined in sc7180.dtsi */
&dp_hot_plug_det {
- pinconf {
- pins = "gpio117";
- bias-disable;
- };
+ bias-disable;
};
&pri_mi2s_active {
- pinconf {
- pins = "gpio53", "gpio54", "gpio55", "gpio56";
- drive-strength = <2>;
- bias-pull-down;
- };
+ drive-strength = <2>;
+ bias-pull-down;
};
&pri_mi2s_mclk_active {
- pinconf {
- pins = "gpio57";
- drive-strength = <2>;
- bias-pull-down;
- };
+ drive-strength = <2>;
+ bias-pull-down;
};
&qspi_cs0 {
- pinconf {
- pins = "gpio68";
- bias-disable;
- };
+ bias-disable;
};
&qspi_clk {
- pinconf {
- pins = "gpio63";
- drive-strength = <8>;
- bias-disable;
- };
+ drive-strength = <8>;
+ bias-disable;
};
&qspi_data01 {
- pinconf {
- pins = "gpio64", "gpio65";
-
- /* High-Z when no transfers; nice to park the lines */
- bias-pull-up;
- };
+ /* High-Z when no transfers; nice to park the lines */
+ bias-pull-up;
};
&qup_i2c2_default {
- pinconf {
- pins = "gpio15", "gpio16";
- drive-strength = <2>;
+ drive-strength = <2>;
- /* Has external pullup */
- bias-disable;
- };
+ /* Has external pullup */
+ bias-disable;
};
&qup_i2c4_default {
- pinconf {
- pins = "gpio115", "gpio116";
- drive-strength = <2>;
+ drive-strength = <2>;
- /* Has external pullup */
- bias-disable;
- };
+ /* Has external pullup */
+ bias-disable;
};
&qup_i2c5_default {
- pinconf {
- pins = "gpio25", "gpio26";
- drive-strength = <2>;
+ drive-strength = <2>;
- /* Has external pullup */
- bias-disable;
- };
+ /* Has external pullup */
+ bias-disable;
};
&qup_i2c7_default {
- pinconf {
- pins = "gpio6", "gpio7";
- drive-strength = <2>;
+ drive-strength = <2>;
- /* Has external pullup */
- bias-disable;
- };
+ /* Has external pullup */
+ bias-disable;
};
&qup_i2c9_default {
- pinconf {
- pins = "gpio46", "gpio47";
- drive-strength = <2>;
+ drive-strength = <2>;
- /* Has external pullup */
- bias-disable;
- };
+ /* Has external pullup */
+ bias-disable;
+};
+
+&qup_spi0_spi {
+ drive-strength = <2>;
+ bias-disable;
};
&qup_spi0_cs_gpio {
- pinconf {
- pins = "gpio34", "gpio35", "gpio36", "gpio37";
- drive-strength = <2>;
- bias-disable;
- };
+ drive-strength = <2>;
+ bias-disable;
+};
+
+&qup_spi6_spi {
+ drive-strength = <2>;
+ bias-disable;
};
&qup_spi6_cs_gpio {
- pinconf {
- pins = "gpio59", "gpio60", "gpio61", "gpio62";
- drive-strength = <2>;
- bias-disable;
- };
+ drive-strength = <2>;
+ bias-disable;
+};
+
+&qup_spi10_spi {
+ drive-strength = <2>;
+ bias-disable;
};
&qup_spi10_cs_gpio {
- pinconf {
- pins = "gpio86", "gpio87", "gpio88", "gpio89";
- drive-strength = <2>;
- bias-disable;
- };
+ drive-strength = <2>;
+ bias-disable;
};
-&qup_uart3_default {
- pinconf-cts {
- /*
- * Configure a pull-down on CTS to match the pull of
- * the Bluetooth module.
- */
- pins = "gpio38";
- bias-pull-down;
- };
+&qup_uart3_cts {
+ /*
+ * Configure a pull-down on CTS to match the pull of
+ * the Bluetooth module.
+ */
+ bias-pull-down;
+};
- pinconf-rts-tx {
- /* We'll drive RTS and TX, so no pull */
- pins = "gpio39", "gpio40";
- drive-strength = <2>;
- bias-disable;
- };
+&qup_uart3_rts {
+ /* We'll drive RTS, so no pull */
+ drive-strength = <2>;
+ bias-disable;
+};
- pinconf-rx {
- /*
- * Configure a pull-up on RX. This is needed to avoid
- * garbage data when the TX pin of the Bluetooth module is
- * in tri-state (module powered off or not driving the
- * signal yet).
- */
- pins = "gpio41";
- bias-pull-up;
- };
+&qup_uart3_tx {
+ /* We'll drive TX, so no pull */
+ drive-strength = <2>;
+ bias-disable;
};
-&qup_uart8_default {
- pinconf-tx {
- pins = "gpio44";
- drive-strength = <2>;
- bias-disable;
- };
+&qup_uart3_rx {
+ /*
+ * Configure a pull-up on RX. This is needed to avoid
+ * garbage data when the TX pin of the Bluetooth module is
+ * in tri-state (module powered off or not driving the
+ * signal yet).
+ */
+ bias-pull-up;
+};
- pinconf-rx {
- pins = "gpio45";
- drive-strength = <2>;
- bias-pull-up;
- };
+&qup_uart8_tx {
+ drive-strength = <2>;
+ bias-disable;
+};
+
+&qup_uart8_rx {
+ drive-strength = <2>;
+ bias-pull-up;
};
&sec_mi2s_active {
- pinconf {
- pins = "gpio49", "gpio50", "gpio51";
- drive-strength = <2>;
- bias-pull-down;
- };
+ drive-strength = <2>;
+ bias-pull-down;
};
/* PINCTRL - board-specific pinctrl */
@@ -1196,468 +1162,342 @@ &tlmm {
pinctrl-names = "default";
pinctrl-0 = <&bios_flash_wp_l>, <&ap_suspend_l_neuter>;
- amp_en: amp-en {
- pinmux {
- pins = "gpio23";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio23";
- bias-pull-down;
- };
+ amp_en: amp-en-state {
+ pins = "gpio23";
+ function = "gpio";
+ bias-pull-down;
};
- ap_ec_int_l: ap-ec-int-l {
- pinmux {
- pins = "gpio94";
- function = "gpio";
- input-enable;
- };
-
- pinconf {
- pins = "gpio94";
- bias-pull-up;
- };
+ ap_ec_int_l: ap-ec-int-l-state {
+ pins = "gpio94";
+ function = "gpio";
+ input-enable;
+ bias-pull-up;
};
- ap_edp_bklten: ap-edp-bklten {
- pinmux {
- pins = "gpio12";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio12";
- drive-strength = <2>;
- bias-disable;
+ ap_edp_bklten: ap-edp-bklten-state {
+ pins = "gpio12";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
- /* Force backlight to be disabled to match state at boot. */
- output-low;
- };
+ /* Force backlight to be disabled to match state at boot. */
+ output-low;
};
- ap_suspend_l_neuter: ap-suspend-l-neuter {
- pinmux {
- pins = "gpio27";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio27";
- bias-disable;
- };
+ ap_suspend_l_neuter: ap-suspend-l-neuter-state {
+ pins = "gpio27";
+ function = "gpio";
+ bias-disable;
};
- bios_flash_wp_l: bios-flash-wp-l {
- pinmux {
- pins = "gpio66";
- function = "gpio";
- input-enable;
- };
-
- pinconf {
- pins = "gpio66";
- bias-disable;
- };
+ bios_flash_wp_l: bios-flash-wp-l-state {
+ pins = "gpio66";
+ function = "gpio";
+ input-enable;
+ bias-disable;
};
- edp_brij_en: edp-brij-en {
- pinmux {
- pins = "gpio104";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio104";
- drive-strength = <2>;
- bias-disable;
- };
+ edp_brij_en: edp-brij-en-state {
+ pins = "gpio104";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
};
- en_pp3300_codec: en-pp3300-codec {
- pinmux {
- pins = "gpio83";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio83";
- drive-strength = <2>;
- bias-disable;
- };
+ en_pp3300_codec: en-pp3300-codec-state {
+ pins = "gpio83";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
};
- en_pp3300_dx_edp: en-pp3300-dx-edp {
- pinmux {
- pins = "gpio30";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio30";
- drive-strength = <2>;
- bias-disable;
- };
+ en_pp3300_dx_edp: en-pp3300-dx-edp-state {
+ pins = "gpio30";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
};
- en_pp3300_hub: en-pp3300-hub {
- pinmux {
- pins = "gpio84";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio84";
- drive-strength = <2>;
- bias-disable;
- };
+ en_pp3300_hub: en-pp3300-hub-state {
+ pins = "gpio84";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
};
- fp_to_ap_irq_l: fp-to-ap-irq-l {
- pinmux {
- pins = "gpio4";
- function = "gpio";
- input-enable;
- };
+ fp_to_ap_irq_l: fp-to-ap-irq-l-state {
+ pins = "gpio4";
+ function = "gpio";
+ input-enable;
- pinconf {
- pins = "gpio4";
-
- /* Has external pullup */
- bias-disable;
- };
+ /* Has external pullup */
+ bias-disable;
};
- h1_ap_int_odl: h1-ap-int-odl {
- pinmux {
- pins = "gpio42";
- function = "gpio";
- input-enable;
- };
-
- pinconf {
- pins = "gpio42";
- bias-pull-up;
- };
+ h1_ap_int_odl: h1-ap-int-odl-state {
+ pins = "gpio42";
+ function = "gpio";
+ input-enable;
+ bias-pull-up;
};
- hp_irq: hp-irq {
- pinmux {
- pins = "gpio28";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio28";
- bias-pull-up;
- };
+ hp_irq: hp-irq-state {
+ pins = "gpio28";
+ function = "gpio";
+ bias-pull-up;
};
- pen_irq_l: pen-irq-l {
- pinmux {
- pins = "gpio21";
- function = "gpio";
- };
+ pen_irq_l: pen-irq-l-state {
+ pins = "gpio21";
+ function = "gpio";
- pinconf {
- pins = "gpio21";
-
- /* Has external pullup */
- bias-disable;
- };
+ /* Has external pullup */
+ bias-disable;
};
- pen_pdct_l: pen-pdct-l {
- pinmux {
- pins = "gpio52";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio52";
+ pen_pdct_l: pen-pdct-l-state-state {
+ pins = "gpio52";
+ function = "gpio";
- /* Has external pullup */
- bias-disable;
- };
+ /* Has external pullup */
+ bias-disable;
};
- pen_rst_odl: pen-rst-odl {
- pinmux {
- pins = "gpio18";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio18";
- bias-disable;
- drive-strength = <2>;
+ pen_rst_odl: pen-rst-odl-state {
+ pins = "gpio18";
+ function = "gpio";
+ bias-disable;
+ drive-strength = <2>;
- /*
- * The pen driver doesn't currently support
- * driving this reset line. By specifying
- * output-high here we're relying on the fact
- * that this pin has a default pulldown at boot
- * (which makes sure the pen was in reset if it
- * was powered) and then we set it high here to
- * take it out of reset. Better would be if the
- * pen driver could control this and we could
- * remove "output-high" here.
- */
- output-high; /* TODO: Remove this? */
- };
+ /*
+ * The pen driver doesn't currently support
+ * driving this reset line. By specifying
+ * output-high here we're relying on the fact
+ * that this pin has a default pulldown at boot
+ * (which makes sure the pen was in reset if it
+ * was powered) and then we set it high here to
+ * take it out of reset. Better would be if the
+ * pen driver could control this and we could
+ * remove "output-high" here.
+ */
+ output-high; /* TODO: Remove this? */
};
- p_sensor_int_l: p-sensor-int-l {
- pinmux {
- pins = "gpio24";
- function = "gpio";
- input-enable;
- };
+ p_sensor_int_l: p-sensor-int-l-state {
+ pins = "gpio24";
+ function = "gpio";
+ input-enable;
- pinconf {
- pins = "gpio24";
- /* Has external pullup */
- bias-disable;
- };
+ /* Has external pullup */
+ bias-disable;
};
- qup_spi0_cs_gpio_init_high: qup-spi0-cs-gpio-init-high {
- pinconf {
- pins = "gpio37";
- output-high;
- };
+ qup_spi0_cs_gpio_init_high: qup-spi0-cs-gpio-init-high-state {
+ pins = "gpio37";
+ function = "gpio";
+ output-high;
};
- qup_spi6_cs_gpio_init_high: qup-spi6-cs-gpio-init-high {
- pinconf {
- pins = "gpio62";
- output-high;
- };
+ qup_spi6_cs_gpio_init_high: qup-spi6-cs-gpio-init-high-state {
+ pins = "gpio62";
+ function = "gpio";
+ output-high;
};
- qup_spi10_cs_gpio_init_high: qup-spi10-cs-gpio-init-high {
- pinconf {
- pins = "gpio89";
- output-high;
- };
+ qup_spi10_cs_gpio_init_high: qup-spi10-cs-gpio-init-high-state {
+ pins = "gpio89";
+ function = "gpio";
+ output-high;
};
- qup_uart3_sleep: qup-uart3-sleep {
- pinmux {
- pins = "gpio38", "gpio39",
- "gpio40", "gpio41";
- function = "gpio";
- };
-
- pinconf-cts {
+ qup_uart3_sleep: qup-uart3-sleep-state {
+ cts-pins {
/*
* Configure a pull-down on CTS to match the pull of
* the Bluetooth module.
*/
pins = "gpio38";
+ function = "gpio";
bias-pull-down;
};
- pinconf-rts {
+ rts-pins {
/*
* Configure pull-down on RTS. As RTS is active low
* signal, pull it low to indicate the BT SoC that it
* can wakeup the system anytime from suspend state by
* pulling RX low (by sending wakeup bytes).
*/
- pins = "gpio39";
- bias-pull-down;
+ pins = "gpio39";
+ function = "gpio";
+ bias-pull-down;
};
- pinconf-tx {
+ tx-pins {
/*
* Configure pull-up on TX when it isn't actively driven
* to prevent BT SoC from receiving garbage during sleep.
*/
pins = "gpio40";
+ function = "gpio";
bias-pull-up;
};
- pinconf-rx {
+ rx-pins {
/*
* Configure a pull-up on RX. This is needed to avoid
* garbage data when the TX pin of the Bluetooth module
* is floating which may cause spurious wakeups.
*/
pins = "gpio41";
+ function = "gpio";
bias-pull-up;
};
};
/* Named trackpad_int_1v8_odl on earlier revision schematics */
trackpad_int_1v8_odl:
- tp_int_odl: tp-int-odl {
- pinmux {
- pins = "gpio0";
- function = "gpio";
- };
+ tp_int_odl: tp-int-odl-state {
+ pins = "gpio0";
+ function = "gpio";
- pinconf {
- pins = "gpio0";
-
- /* Has external pullup */
- bias-disable;
- };
+ /* Has external pullup */
+ bias-disable;
};
- ts_int_l: ts-int-l {
- pinmux {
- pins = "gpio9";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio9";
- bias-pull-up;
- };
+ ts_int_l: ts-int-l-state {
+ pins = "gpio9";
+ function = "gpio";
+ bias-pull-up;
};
- ts_reset_l: ts-reset-l {
- pinmux {
- pins = "gpio8";
- function = "gpio";
- };
-
- pinconf {
- pins = "gpio8";
- bias-disable;
- drive-strength = <2>;
- };
+ ts_reset_l: ts-reset-l-state {
+ pins = "gpio8";
+ function = "gpio";
+ bias-disable;
+ drive-strength = <2>;
};
- sdc1_on: sdc1-on {
- pinconf-clk {
+ sdc1_on: sdc1-on-state {
+ clk-pins {
pins = "sdc1_clk";
bias-disable;
drive-strength = <16>;
};
- pinconf-cmd {
+ cmd-pins {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <16>;
};
- pinconf-data {
+ data-pins {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <16>;
};
- pinconf-rclk {
+ rclk-pins {
pins = "sdc1_rclk";
bias-pull-down;
};
};
- sdc1_off: sdc1-off {
- pinconf-clk {
+ sdc1_off: sdc1-off-state {
+ clk-pins {
pins = "sdc1_clk";
bias-disable;
drive-strength = <2>;
};
- pinconf-cmd {
+ cmd-pins {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <2>;
};
- pinconf-data {
+ data-pins {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <2>;
};
- pinconf-rclk {
+ rclk-pins {
pins = "sdc1_rclk";
bias-pull-down;
};
};
- sdc2_on: sdc2-on {
- pinconf-clk {
+ sdc2_on: sdc2-on-state {
+ clk-pins {
pins = "sdc2_clk";
bias-disable;
drive-strength = <16>;
};
- pinconf-cmd {
+ cmd-pins {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <10>;
};
- pinconf-data {
+ data-pins {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <10>;
};
- pinconf-sd-cd {
+ sd-cd-pins {
pins = "gpio69";
+ function = "gpio";
bias-pull-up;
drive-strength = <2>;
};
};
- sdc2_off: sdc2-off {
- pinconf-clk {
+ sdc2_off: sdc2-off-state {
+ clk-pins {
pins = "sdc2_clk";
bias-disable;
drive-strength = <2>;
};
- pinconf-cmd {
+ cmd-pins {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <2>;
};
- pinconf-data {
+ data-pins {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <2>;
};
- pinconf-sd-cd {
+ sd-cd-pins {
pins = "gpio69";
+ function = "gpio";
bias-pull-up;
drive-strength = <2>;
};
};
- uf_cam_en: uf-cam-en {
- pinmux {
- pins = "gpio6";
- function = "gpio";
- };
+ uf_cam_en: uf-cam-en-state {
+ pins = "gpio6";
+ function = "gpio";
+ drive-strength = <2>;
- pinconf {
- pins = "gpio6";
- drive-strength = <2>;
- /* External pull down */
- bias-disable;
- };
+ /* External pull down */
+ bias-disable;
};
- wf_cam_en: wf-cam-en {
- pinmux {
- pins = "gpio7";
- function = "gpio";
- };
+ wf_cam_en: wf-cam-en-state {
+ pins = "gpio7";
+ function = "gpio";
+ drive-strength = <2>;
- pinconf {
- pins = "gpio7";
- drive-strength = <2>;
- /* External pull down */
- bias-disable;
- };
+ /* External pull down */
+ bias-disable;
};
};
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 58976a1ba06b..9f465662bd49 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -795,7 +795,7 @@ spi0: spi@880000 {
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
pinctrl-names = "default";
- pinctrl-0 = <&qup_spi0_default>;
+ pinctrl-0 = <&qup_spi0_spi>, <&qup_spi0_cs>;
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -849,7 +849,7 @@ spi1: spi@884000 {
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
pinctrl-names = "default";
- pinctrl-0 = <&qup_spi1_default>;
+ pinctrl-0 = <&qup_spi1_spi>, <&qup_spi1_cs>;
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -939,7 +939,7 @@ spi3: spi@88c000 {
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
pinctrl-names = "default";
- pinctrl-0 = <&qup_spi3_default>;
+ pinctrl-0 = <&qup_spi3_spi>, <&qup_spi3_cs>;
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1029,7 +1029,7 @@ spi5: spi@894000 {
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
pinctrl-names = "default";
- pinctrl-0 = <&qup_spi5_default>;
+ pinctrl-0 = <&qup_spi5_spi>, <&qup_spi5_cs>;
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1096,7 +1096,7 @@ spi6: spi@a80000 {
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
pinctrl-names = "default";
- pinctrl-0 = <&qup_spi6_default>;
+ pinctrl-0 = <&qup_spi6_spi>, <&qup_spi6_cs>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1186,7 +1186,7 @@ spi8: spi@a88000 {
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
pinctrl-names = "default";
- pinctrl-0 = <&qup_spi8_default>;
+ pinctrl-0 = <&qup_spi8_spi>, <&qup_spi8_cs>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1276,7 +1276,7 @@ spi10: spi@a90000 {
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
pinctrl-names = "default";
- pinctrl-0 = <&qup_spi10_default>;
+ pinctrl-0 = <&qup_spi10_spi>, <&qup_spi10_cs>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1330,7 +1330,7 @@ spi11: spi@a94000 {
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
pinctrl-names = "default";
- pinctrl-0 = <&qup_spi11_default>;
+ pinctrl-0 = <&qup_spi11_spi>, <&qup_spi11_cs>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1486,410 +1486,443 @@ tlmm: pinctrl@3500000 {
gpio-ranges = <&tlmm 0 0 120>;
wakeup-parent = <&pdc>;
- dp_hot_plug_det: dp-hot-plug-det {
- pinmux {
- pins = "gpio117";
- function = "dp_hot";
- };
+ dp_hot_plug_det: dp-hot-plug-det-state {
+ pins = "gpio117";
+ function = "dp_hot";
};
- qspi_clk: qspi-clk {
- pinmux {
- pins = "gpio63";
- function = "qspi_clk";
- };
+ qspi_clk: qspi-clk-state {
+ pins = "gpio63";
+ function = "qspi_clk";
};
- qspi_cs0: qspi-cs0 {
- pinmux {
- pins = "gpio68";
- function = "qspi_cs";
- };
+ qspi_cs0: qspi-cs0-state {
+ pins = "gpio68";
+ function = "qspi_cs";
};
- qspi_cs1: qspi-cs1 {
- pinmux {
- pins = "gpio72";
- function = "qspi_cs";
- };
+ qspi_cs1: qspi-cs1-state {
+ pins = "gpio72";
+ function = "qspi_cs";
};
- qspi_data01: qspi-data01 {
- pinmux-data {
- pins = "gpio64", "gpio65";
- function = "qspi_data";
- };
+ qspi_data01: qspi-data01-state {
+ pins = "gpio64", "gpio65";
+ function = "qspi_data";
};
- qspi_data12: qspi-data12 {
- pinmux-data {
- pins = "gpio66", "gpio67";
- function = "qspi_data";
- };
+ qspi_data12: qspi-data12-state {
+ pins = "gpio66", "gpio67";
+ function = "qspi_data";
};
- qup_i2c0_default: qup-i2c0-default {
- pinmux {
- pins = "gpio34", "gpio35";
- function = "qup00";
- };
+ qup_i2c0_default: qup-i2c0-default-state {
+ pins = "gpio34", "gpio35";
+ function = "qup00";
};
- qup_i2c1_default: qup-i2c1-default {
- pinmux {
- pins = "gpio0", "gpio1";
- function = "qup01";
- };
+ qup_i2c1_default: qup-i2c1-default-state {
+ pins = "gpio0", "gpio1";
+ function = "qup01";
};
- qup_i2c2_default: qup-i2c2-default {
- pinmux {
- pins = "gpio15", "gpio16";
- function = "qup02_i2c";
- };
+ qup_i2c2_default: qup-i2c2-default-state {
+ pins = "gpio15", "gpio16";
+ function = "qup02_i2c";
};
- qup_i2c3_default: qup-i2c3-default {
- pinmux {
- pins = "gpio38", "gpio39";
- function = "qup03";
- };
+ qup_i2c3_default: qup-i2c3-default-state {
+ pins = "gpio38", "gpio39";
+ function = "qup03";
};
- qup_i2c4_default: qup-i2c4-default {
- pinmux {
- pins = "gpio115", "gpio116";
- function = "qup04_i2c";
- };
+ qup_i2c4_default: qup-i2c4-default-state {
+ pins = "gpio115", "gpio116";
+ function = "qup04_i2c";
};
- qup_i2c5_default: qup-i2c5-default {
- pinmux {
- pins = "gpio25", "gpio26";
- function = "qup05";
- };
+ qup_i2c5_default: qup-i2c5-default-state {
+ pins = "gpio25", "gpio26";
+ function = "qup05";
};
- qup_i2c6_default: qup-i2c6-default {
- pinmux {
- pins = "gpio59", "gpio60";
- function = "qup10";
- };
+ qup_i2c6_default: qup-i2c6-default-state {
+ pins = "gpio59", "gpio60";
+ function = "qup10";
};
- qup_i2c7_default: qup-i2c7-default {
- pinmux {
- pins = "gpio6", "gpio7";
- function = "qup11_i2c";
- };
+ qup_i2c7_default: qup-i2c7-default-state {
+ pins = "gpio6", "gpio7";
+ function = "qup11_i2c";
};
- qup_i2c8_default: qup-i2c8-default {
- pinmux {
- pins = "gpio42", "gpio43";
- function = "qup12";
- };
+ qup_i2c8_default: qup-i2c8-default-state {
+ pins = "gpio42", "gpio43";
+ function = "qup12";
};
- qup_i2c9_default: qup-i2c9-default {
- pinmux {
- pins = "gpio46", "gpio47";
- function = "qup13_i2c";
- };
+ qup_i2c9_default: qup-i2c9-default-state {
+ pins = "gpio46", "gpio47";
+ function = "qup13_i2c";
};
- qup_i2c10_default: qup-i2c10-default {
- pinmux {
- pins = "gpio86", "gpio87";
- function = "qup14";
- };
+ qup_i2c10_default: qup-i2c10-default-state {
+ pins = "gpio86", "gpio87";
+ function = "qup14";
};
- qup_i2c11_default: qup-i2c11-default {
- pinmux {
- pins = "gpio53", "gpio54";
- function = "qup15";
- };
+ qup_i2c11_default: qup-i2c11-default-state {
+ pins = "gpio53", "gpio54";
+ function = "qup15";
+ };
+
+ qup_spi0_spi: qup-spi0-spi-state {
+ pins = "gpio34", "gpio35", "gpio36";
+ function = "qup00";
+ };
+
+ qup_spi0_cs: qup-spi0-cs-state {
+ pins = "gpio37";
+ function = "qup00";
+ };
+
+ qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
+ pins = "gpio37";
+ function = "gpio";
+ };
+
+ qup_spi1_spi: qup-spi1-spi-state {
+ pins = "gpio0", "gpio1", "gpio2";
+ function = "qup01";
+ };
+
+ qup_spi1_cs: qup-spi1-cs-state {
+ pins = "gpio3";
+ function = "qup01";
+ };
+
+ qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
+ pins = "gpio3";
+ function = "gpio";
+ };
+
+ qup_spi3_spi: qup-spi3-spi-state {
+ pins = "gpio38", "gpio39", "gpio40";
+ function = "qup03";
+ };
+
+ qup_spi3_cs: qup-spi3-cs-state {
+ pins = "gpio41";
+ function = "qup03";
};
- qup_spi0_default: qup-spi0-default {
- pinmux {
- pins = "gpio34", "gpio35",
- "gpio36", "gpio37";
+ qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
+ pins = "gpio41";
+ function = "gpio";
+ };
+
+ qup_spi5_spi: qup-spi5-spi-state {
+ pins = "gpio25", "gpio26", "gpio27";
+ function = "qup05";
+ };
+
+ qup_spi5_cs: qup-spi5-cs-state {
+ pins = "gpio28";
+ function = "qup05";
+ };
+
+ qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
+ pins = "gpio28";
+ function = "gpio";
+ };
+
+ qup_spi6_spi: qup-spi6-spi-state {
+ pins = "gpio59", "gpio60", "gpio61";
+ function = "qup10";
+ };
+
+ qup_spi6_cs: qup-spi6-cs-state {
+ pins = "gpio62";
+ function = "qup10";
+ };
+
+ qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
+ pins = "gpio62";
+ function = "gpio";
+ };
+
+ qup_spi8_spi: qup-spi8-spi-state {
+ pins = "gpio42", "gpio43", "gpio44";
+ function = "qup12";
+ };
+
+ qup_spi8_cs: qup-spi8-cs-state {
+ pins = "gpio45";
+ function = "qup12";
+ };
+
+ qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
+ pins = "gpio45";
+ function = "gpio";
+ };
+
+ qup_spi10_spi: qup-spi10-spi-state {
+ pins = "gpio86", "gpio87", "gpio88";
+ function = "qup14";
+ };
+
+ qup_spi10_cs: qup-spi10-cs-state {
+ pins = "gpio89";
+ function = "qup14";
+ };
+
+ qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
+ pins = "gpio89";
+ function = "gpio";
+ };
+
+ qup_spi11_spi: qup-spi11-spi-state {
+ pins = "gpio53", "gpio54", "gpio55";
+ function = "qup15";
+ };
+
+ qup_spi11_cs: qup-spi11-cs-state {
+ pins = "gpio56";
+ function = "qup15";
+ };
+
+ qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
+ pins = "gpio56";
+ function = "gpio";
+ };
+
+ qup_uart0_default: qup-uart0-default-state {
+ qup_uart0_cts: cts-pins {
+ pins = "gpio34";
function = "qup00";
};
- };
- qup_spi0_cs_gpio: qup-spi0-cs-gpio {
- pinmux {
- pins = "gpio34", "gpio35",
- "gpio36";
+ qup_uart0_rts: rts-pins {
+ pins = "gpio35";
function = "qup00";
};
- pinmux-cs {
+ qup_uart0_tx: tx-pins {
+ pins = "gpio36";
+ function = "qup00";
+ };
+
+ qup_uart0_rx: rx-pins {
pins = "gpio37";
- function = "gpio";
+ function = "qup00";
};
};
- qup_spi1_default: qup-spi1-default {
- pinmux {
- pins = "gpio0", "gpio1",
- "gpio2", "gpio3";
+ qup_uart1_default: qup-uart1-default-state {
+ qup_uart1_cts: cts-pins {
+ pins = "gpio0";
function = "qup01";
};
- };
- qup_spi1_cs_gpio: qup-spi1-cs-gpio {
- pinmux {
- pins = "gpio0", "gpio1",
- "gpio2";
+ qup_uart1_rts: rts-pins {
+ pins = "gpio1";
function = "qup01";
};
- pinmux-cs {
- pins = "gpio3";
- function = "gpio";
+ qup_uart1_tx: tx-pins {
+ pins = "gpio2";
+ function = "qup01";
};
- };
- qup_spi3_default: qup-spi3-default {
- pinmux {
- pins = "gpio38", "gpio39",
- "gpio40", "gpio41";
- function = "qup03";
+ qup_uart1_rx: rx-pins {
+ pins = "gpio3";
+ function = "qup01";
};
};
- qup_spi3_cs_gpio: qup-spi3-cs-gpio {
- pinmux {
- pins = "gpio38", "gpio39",
- "gpio40";
- function = "qup03";
+ qup_uart2_default: qup-uart2-default-state {
+ qup_uart2_tx: tx-pins {
+ pins = "gpio15";
+ function = "qup02_uart";
};
- pinmux-cs {
- pins = "gpio41";
- function = "gpio";
+ qup_uart2_rx: rx-pins {
+ pins = "gpio16";
+ function = "qup02_uart";
};
};
- qup_spi5_default: qup-spi5-default {
- pinmux {
- pins = "gpio25", "gpio26",
- "gpio27", "gpio28";
- function = "qup05";
+ qup_uart3_default: qup-uart3-default-state {
+ qup_uart3_cts: cts-pins {
+ pins = "gpio38";
+ function = "qup03";
};
- };
- qup_spi5_cs_gpio: qup-spi5-cs-gpio {
- pinmux {
- pins = "gpio25", "gpio26",
- "gpio27";
- function = "qup05";
+ qup_uart3_rts: rts-pins {
+ pins = "gpio39";
+ function = "qup03";
};
- pinmux-cs {
- pins = "gpio28";
- function = "gpio";
+ qup_uart3_tx: tx-pins {
+ pins = "gpio40";
+ function = "qup03";
};
- };
- qup_spi6_default: qup-spi6-default {
- pinmux {
- pins = "gpio59", "gpio60",
- "gpio61", "gpio62";
- function = "qup10";
+ qup_uart3_rx: rx-pins {
+ pins = "gpio41";
+ function = "qup03";
};
};
- qup_spi6_cs_gpio: qup-spi6-cs-gpio {
- pinmux {
- pins = "gpio59", "gpio60",
- "gpio61";
- function = "qup10";
+ qup_uart4_default: qup-uart4-default-state {
+ qup_uart4_tx: tx-pins {
+ pins = "gpio115";
+ function = "qup04_uart";
};
- pinmux-cs {
- pins = "gpio62";
- function = "gpio";
+ qup_uart4_rx: rx-pins {
+ pins = "gpio116";
+ function = "qup04_uart";
};
};
- qup_spi8_default: qup-spi8-default {
- pinmux {
- pins = "gpio42", "gpio43",
- "gpio44", "gpio45";
- function = "qup12";
+ qup_uart5_default: qup-uart5-default-state {
+ qup_uart5_cts: cts-pins {
+ pins = "gpio25";
+ function = "qup05";
};
- };
- qup_spi8_cs_gpio: qup-spi8-cs-gpio {
- pinmux {
- pins = "gpio42", "gpio43",
- "gpio44";
- function = "qup12";
+ qup_uart5_rts: rts-pins {
+ pins = "gpio26";
+ function = "qup05";
};
- pinmux-cs {
- pins = "gpio45";
- function = "gpio";
+ qup_uart5_tx: tx-pins {
+ pins = "gpio27";
+ function = "qup05";
};
- };
- qup_spi10_default: qup-spi10-default {
- pinmux {
- pins = "gpio86", "gpio87",
- "gpio88", "gpio89";
- function = "qup14";
+ qup_uart5_rx: rx-pins {
+ pins = "gpio28";
+ function = "qup05";
};
};
- qup_spi10_cs_gpio: qup-spi10-cs-gpio {
- pinmux {
- pins = "gpio86", "gpio87",
- "gpio88";
- function = "qup14";
+ qup_uart6_default: qup-uart6-default-state {
+ qup_uart6_cts: cts-pins {
+ pins = "gpio59";
+ function = "qup10";
};
- pinmux-cs {
- pins = "gpio89";
- function = "gpio";
+ qup_uart6_rts: rts-pins {
+ pins = "gpio60";
+ function = "qup10";
};
- };
- qup_spi11_default: qup-spi11-default {
- pinmux {
- pins = "gpio53", "gpio54",
- "gpio55", "gpio56";
- function = "qup15";
+ qup_uart6_tx: tx-pins {
+ pins = "gpio61";
+ function = "qup10";
+ };
+
+ qup_uart6_rx: rx-pins {
+ pins = "gpio62";
+ function = "qup10";
};
};
- qup_spi11_cs_gpio: qup-spi11-cs-gpio {
- pinmux {
- pins = "gpio53", "gpio54",
- "gpio55";
- function = "qup15";
+ qup_uart7_default: qup-uart7-default-state {
+ qup_uart7_tx: tx-pins {
+ pins = "gpio6";
+ function = "qup11_uart";
};
- pinmux-cs {
- pins = "gpio56";
- function = "gpio";
+ qup_uart7_rx: rx-pins {
+ pins = "gpio7";
+ function = "qup11_uart";
};
};
- qup_uart0_default: qup-uart0-default {
- pinmux {
- pins = "gpio34", "gpio35",
- "gpio36", "gpio37";
- function = "qup00";
+ qup_uart8_default: qup-uart8-default-state {
+ qup_uart8_tx: tx-pins {
+ pins = "gpio44";
+ function = "qup12";
};
- };
- qup_uart1_default: qup-uart1-default {
- pinmux {
- pins = "gpio0", "gpio1",
- "gpio2", "gpio3";
- function = "qup01";
+ qup_uart8_rx: rx-pins {
+ pins = "gpio45";
+ function = "qup12";
};
};
- qup_uart2_default: qup-uart2-default {
- pinmux {
- pins = "gpio15", "gpio16";
- function = "qup02_uart";
+ qup_uart9_default: qup-uart9-default-state {
+ qup_uart9_tx: tx-pins {
+ pins = "gpio46";
+ function = "qup13_uart";
};
- };
- qup_uart3_default: qup-uart3-default {
- pinmux {
- pins = "gpio38", "gpio39",
- "gpio40", "gpio41";
- function = "qup03";
+ qup_uart9_rx: rx-pins {
+ pins = "gpio47";
+ function = "qup13_uart";
};
};
- qup_uart4_default: qup-uart4-default {
- pinmux {
- pins = "gpio115", "gpio116";
- function = "qup04_uart";
+ qup_uart10_default: qup-uart10-default-state {
+ qup_uart10_cts: cts-pins {
+ pins = "gpio86";
+ function = "qup14";
};
- };
- qup_uart5_default: qup-uart5-default {
- pinmux {
- pins = "gpio25", "gpio26",
- "gpio27", "gpio28";
- function = "qup05";
+ qup_uart10_rts: rts-pins {
+ pins = "gpio87";
+ function = "qup14";
};
- };
- qup_uart6_default: qup-uart6-default {
- pinmux {
- pins = "gpio59", "gpio60",
- "gpio61", "gpio62";
- function = "qup10";
+ qup_uart10_tx: tx-pins {
+ pins = "gpio88";
+ function = "qup14";
};
- };
- qup_uart7_default: qup-uart7-default {
- pinmux {
- pins = "gpio6", "gpio7";
- function = "qup11_uart";
+ qup_uart10_rx: rx-pins {
+ pins = "gpio89";
+ function = "qup14";
};
};
- qup_uart8_default: qup-uart8-default {
- pinmux {
- pins = "gpio44", "gpio45";
- function = "qup12";
+ qup_uart11_default: qup-uart11-default-state {
+ qup_uart11_cts: cts-pins {
+ pins = "gpio53";
+ function = "qup15";
};
- };
- qup_uart9_default: qup-uart9-default {
- pinmux {
- pins = "gpio46", "gpio47";
- function = "qup13_uart";
+ qup_uart11_rts: rts-pins {
+ pins = "gpio54";
+ function = "qup15";
};
- };
- qup_uart10_default: qup-uart10-default {
- pinmux {
- pins = "gpio86", "gpio87",
- "gpio88", "gpio89";
- function = "qup14";
+ qup_uart11_tx: tx-pins {
+ pins = "gpio55";
+ function = "qup15";
};
- };
- qup_uart11_default: qup-uart11-default {
- pinmux {
- pins = "gpio53", "gpio54",
- "gpio55", "gpio56";
+ qup_uart11_rx: rx-pins {
+ pins = "gpio56";
function = "qup15";
};
};
- sec_mi2s_active: sec-mi2s-active {
- pinmux {
- pins = "gpio49", "gpio50", "gpio51";
- function = "mi2s_1";
- };
+ sec_mi2s_active: sec-mi2s-active-state {
+ pins = "gpio49", "gpio50", "gpio51";
+ function = "mi2s_1";
};
- pri_mi2s_active: pri-mi2s-active {
- pinmux {
- pins = "gpio53", "gpio54", "gpio55", "gpio56";
- function = "mi2s_0";
- };
+ pri_mi2s_active: pri-mi2s-active-state {
+ pins = "gpio53", "gpio54", "gpio55", "gpio56";
+ function = "mi2s_0";
};
- pri_mi2s_mclk_active: pri-mi2s-mclk-active {
- pinmux {
- pins = "gpio57";
- function = "lpass_ext";
- };
+ pri_mi2s_mclk_active: pri-mi2s-mclk-active-state {
+ pins = "gpio57";
+ function = "lpass_ext";
};
};
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v2 2/3] arm64: dts: qcom: sc7180: align TLMM pin configuration with DT schema
2022-10-13 18:46 ` [PATCH v2 2/3] arm64: dts: qcom: sc7180: align TLMM pin configuration with DT schema Krzysztof Kozlowski
@ 2022-10-14 17:50 ` Doug Anderson
2022-10-16 16:23 ` Krzysztof Kozlowski
0 siblings, 1 reply; 8+ messages in thread
From: Doug Anderson @ 2022-10-14 17:50 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Andy Gross, Bjorn Andersson, Konrad Dybcio, Linus Walleij,
Rob Herring, Krzysztof Kozlowski, linux-arm-msm, linux-gpio,
devicetree, linux-kernel
Hi,
On Thu, Oct 13, 2022 at 11:49 AM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
> index eae22e6e97c1..37abe131951c 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
[ ... cut ... ]
> &spi0 {
> - pinctrl-0 = <&qup_spi0_cs_gpio_init_high>, <&qup_spi0_cs_gpio>;
> + pinctrl-0 = <&qup_spi0_cs_gpio_init_high>, <&qup_spi0_spi>;
> cs-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
> };
Something still looks wrong with the above. I would have expected:
<&qup_spi0_cs_gpio_init_high>, <&qup_spi0_spi>, <&qup_spi0_cs_gpio>;
Specifically the old commit e440e30e26dd ("arm64: dts: qcom: sc7180:
Avoid glitching SPI CS at bootup on trogdor") only worked correctly
because "qup_spi0_cs_gpio_init_high" didn't specify a "function".
That meant it was guaranteed to _just_ set the GPIO output to be
high without changing the mux. Then later we'd change the mux and
the output would already be high and we'd have no glitch.
As I mentioned earlier, I didn't love that solution but I didn't
see a better way. Specifically, I don't think that the properties
within a device tree node are ordered. Thus with your new definition:
qup_spi0_cs_gpio_init_high: qup-spi0-cs-gpio-init-high-state {
pins = "gpio37";
function = "gpio";
output-high;
};
Nothing tells the pinctrl subsystem whether it should apply the
'output-high' before the 'function = "gpio"' or vice versa. From
my previous investigation it seemed to set the function first
and then the output to be high. Maybe that's because I happened
to list the function first, but I wouldn't have thought it was
legal to rely on the ordering of properties.
On the other hand, values within a property _are_ ordered. That
means that when we specify:
<&qup_spi0_cs_gpio_init_high>, <&qup_spi0_spi>, <&qup_spi0_cs_gpio>;
The pinctrl subsystem can see that we want "init_high" done first,
then the SPI pins setup, and then the GPIO setup.
I confirmed that with your patches applied that the EC was reporting
a glitch, though I haven't (yet) managed to reproduce the cros-ec
probe failure that we were seeing in the past.
Unfortunately, I then reverted your patches and the EC was _still_
glitching. :( It looks like things broke in commit b991f8c3622c ("pinctrl:
core: Handling pinmux and pinconf separately"). :( Sure enough,
reverting that patch fixes the glitching.
OK, several hours later and I've come up with a proposed solution [1].
Assuming that solution lands, then I think the answer is:
a) Totally get rid of the '_init_high' entries.
b) trogdor should just specify:
<&qup_spi0_spi>, <&qup_spi0_cs_gpio>;
[ ... cut ... ]
> +&qup_spi0_spi {
> + drive-strength = <2>;
> + bias-disable;
> };
>
> &qup_spi0_cs_gpio {
> - pinconf {
> - pins = "gpio34", "gpio35", "gpio36", "gpio37";
> - drive-strength = <2>;
> - bias-disable;
> - };
> + drive-strength = <2>;
> + bias-disable;
> +};
> +
> +&qup_spi6_spi {
> + drive-strength = <2>;
> + bias-disable;
> };
>
> &qup_spi6_cs_gpio {
> - pinconf {
> - pins = "gpio59", "gpio60", "gpio61", "gpio62";
> - drive-strength = <2>;
> - bias-disable;
> - };
> + drive-strength = <2>;
> + bias-disable;
> +};
> +
> +&qup_spi10_spi {
> + drive-strength = <2>;
> + bias-disable;
> };
>
> &qup_spi10_cs_gpio {
> - pinconf {
> - pins = "gpio86", "gpio87", "gpio88", "gpio89";
> - drive-strength = <2>;
> - bias-disable;
> - };
> + drive-strength = <2>;
> + bias-disable;
> };
Mostly addressed by the above, but it should be noted that in your
patch you were specifying settings in the trogdor.dtsi file for
"qup_spi#_cs_gpio" but then never using it (it used the _init_high
versions).
[1] https://lore.kernel.org/r/20221014103217.1.I656bb2c976ed626e5d37294eb252c1cf3be769dc@changeid
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH v2 2/3] arm64: dts: qcom: sc7180: align TLMM pin configuration with DT schema
2022-10-14 17:50 ` Doug Anderson
@ 2022-10-16 16:23 ` Krzysztof Kozlowski
0 siblings, 0 replies; 8+ messages in thread
From: Krzysztof Kozlowski @ 2022-10-16 16:23 UTC (permalink / raw)
To: Doug Anderson
Cc: Andy Gross, Bjorn Andersson, Konrad Dybcio, Linus Walleij,
Rob Herring, Krzysztof Kozlowski, linux-arm-msm, linux-gpio,
devicetree, linux-kernel
On 14/10/2022 13:50, Doug Anderson wrote:
> Hi,
>
> On Thu, Oct 13, 2022 at 11:49 AM Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
>> index eae22e6e97c1..37abe131951c 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
>
> [ ... cut ... ]
>
>> &spi0 {
>> - pinctrl-0 = <&qup_spi0_cs_gpio_init_high>, <&qup_spi0_cs_gpio>;
>> + pinctrl-0 = <&qup_spi0_cs_gpio_init_high>, <&qup_spi0_spi>;
>> cs-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
>> };
>
> Something still looks wrong with the above. I would have expected:
>
> <&qup_spi0_cs_gpio_init_high>, <&qup_spi0_spi>, <&qup_spi0_cs_gpio>;
Yes, you're right.
>
> Specifically the old commit e440e30e26dd ("arm64: dts: qcom: sc7180:
> Avoid glitching SPI CS at bootup on trogdor") only worked correctly
> because "qup_spi0_cs_gpio_init_high" didn't specify a "function".
> That meant it was guaranteed to _just_ set the GPIO output to be
> high without changing the mux. Then later we'd change the mux and
> the output would already be high and we'd have no glitch.
>
> As I mentioned earlier, I didn't love that solution but I didn't
> see a better way. Specifically, I don't think that the properties
> within a device tree node are ordered. Thus with your new definition:
>
> qup_spi0_cs_gpio_init_high: qup-spi0-cs-gpio-init-high-state {
> pins = "gpio37";
> function = "gpio";
> output-high;
> };
>
> Nothing tells the pinctrl subsystem whether it should apply the
> 'output-high' before the 'function = "gpio"' or vice versa. From
> my previous investigation it seemed to set the function first
> and then the output to be high. Maybe that's because I happened
> to list the function first, but I wouldn't have thought it was
> legal to rely on the ordering of properties.
>
> On the other hand, values within a property _are_ ordered. That
> means that when we specify:
>
> <&qup_spi0_cs_gpio_init_high>, <&qup_spi0_spi>, <&qup_spi0_cs_gpio>;
>
> The pinctrl subsystem can see that we want "init_high" done first,
> then the SPI pins setup, and then the GPIO setup.
>
> I confirmed that with your patches applied that the EC was reporting
> a glitch, though I haven't (yet) managed to reproduce the cros-ec
> probe failure that we were seeing in the past.
>
> Unfortunately, I then reverted your patches and the EC was _still_
> glitching. :( It looks like things broke in commit b991f8c3622c ("pinctrl:
> core: Handling pinmux and pinconf separately"). :( Sure enough,
> reverting that patch fixes the glitching.
Regardless of this issue, binding requiring a function does not allow to
keep the pin in previous state. Your glitch-workaround was actually an
use-case for such keep-old-function feature.
Yet, I am not sure if we should keep such ability. The firmware could
configure the pin to whatever. Firmware behavior could also change it
making the OS behavior non-predictable.
>
> OK, several hours later and I've come up with a proposed solution [1].
> Assuming that solution lands, then I think the answer is:
>
> a) Totally get rid of the '_init_high' entries.
> b) trogdor should just specify:
> <&qup_spi0_spi>, <&qup_spi0_cs_gpio>;
Yes.
>
> [ ... cut ... ]
>
>> +&qup_spi0_spi {
>> + drive-strength = <2>;
>> + bias-disable;
>> };
>>
>> &qup_spi0_cs_gpio {
>> - pinconf {
>> - pins = "gpio34", "gpio35", "gpio36", "gpio37";
>> - drive-strength = <2>;
>> - bias-disable;
>> - };
>> + drive-strength = <2>;
>> + bias-disable;
>> +};
>> +
>> +&qup_spi6_spi {
>> + drive-strength = <2>;
>> + bias-disable;
>> };
>>
>> &qup_spi6_cs_gpio {
>> - pinconf {
>> - pins = "gpio59", "gpio60", "gpio61", "gpio62";
>> - drive-strength = <2>;
>> - bias-disable;
>> - };
>> + drive-strength = <2>;
>> + bias-disable;
>> +};
>> +
>> +&qup_spi10_spi {
>> + drive-strength = <2>;
>> + bias-disable;
>> };
>>
>> &qup_spi10_cs_gpio {
>> - pinconf {
>> - pins = "gpio86", "gpio87", "gpio88", "gpio89";
>> - drive-strength = <2>;
>> - bias-disable;
>> - };
>> + drive-strength = <2>;
>> + bias-disable;
>> };
>
> Mostly addressed by the above, but it should be noted that in your
> patch you were specifying settings in the trogdor.dtsi file for
> "qup_spi#_cs_gpio" but then never using it (it used the _init_high
> versions).
>
> [1] https://lore.kernel.org/r/20221014103217.1.I656bb2c976ed626e5d37294eb252c1cf3be769dc@changeid
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 3/3] dt-bindings: pinctrl: qcom,sc7180: convert to dtschema
2022-10-13 18:46 [PATCH v2 1/3] arm64: dts: qcom: sc7180-trogdor-homestar: fully configure secondary I2S pins Krzysztof Kozlowski
2022-10-13 18:46 ` [PATCH v2 2/3] arm64: dts: qcom: sc7180: align TLMM pin configuration with DT schema Krzysztof Kozlowski
@ 2022-10-13 18:47 ` Krzysztof Kozlowski
2022-10-14 18:02 ` Doug Anderson
2022-10-14 17:51 ` [PATCH v2 1/3] arm64: dts: qcom: sc7180-trogdor-homestar: fully configure secondary I2S pins Doug Anderson
2 siblings, 1 reply; 8+ messages in thread
From: Krzysztof Kozlowski @ 2022-10-13 18:47 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Linus Walleij,
Rob Herring, Krzysztof Kozlowski, linux-arm-msm, linux-gpio,
devicetree, linux-kernel
Cc: Krzysztof Kozlowski, Rob Herring, Doug Anderson
Convert Qualcomm SC7180 pin controller bindings to DT schema. Keep the
parsing of pin configuration subnodes consistent with other Qualcomm
schemas (children named with '-state' suffix, their children with
'-pins').
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Changes since v1:
1. Drop default:2 for drive strength
2. Add Rb tag.
Cc: Doug Anderson <dianders@chromium.org>
---
.../bindings/pinctrl/qcom,sc7180-pinctrl.txt | 187 ------------------
.../bindings/pinctrl/qcom,sc7180-pinctrl.yaml | 162 +++++++++++++++
2 files changed, 162 insertions(+), 187 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sc7180-pinctrl.txt
create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sc7180-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc7180-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,sc7180-pinctrl.txt
deleted file mode 100644
index 6ffeac9801df..000000000000
--- a/Documentation/devicetree/bindings/pinctrl/qcom,sc7180-pinctrl.txt
+++ /dev/null
@@ -1,187 +0,0 @@
-Qualcomm Technologies, Inc. SC7180 TLMM block
-
-This binding describes the Top Level Mode Multiplexer block found in the
-SC7180 platform.
-
-- compatible:
- Usage: required
- Value type: <string>
- Definition: must be "qcom,sc7180-pinctrl"
-
-- reg:
- Usage: required
- Value type: <prop-encoded-array>
- Definition: the base address and size of the north, south and west
- TLMM tiles
-
-- reg-names:
- Usage: required
- Value type: <prop-encoded-array>
- Definition: names for the cells of reg, must contain "north", "south"
- and "west".
-
-- interrupts:
- Usage: required
- Value type: <prop-encoded-array>
- Definition: should specify the TLMM summary IRQ.
-
-- interrupt-controller:
- Usage: required
- Value type: <none>
- Definition: identifies this node as an interrupt controller
-
-- #interrupt-cells:
- Usage: required
- Value type: <u32>
- Definition: must be 2. Specifying the pin number and flags, as defined
- in <dt-bindings/interrupt-controller/irq.h>
-
-- gpio-controller:
- Usage: required
- Value type: <none>
- Definition: identifies this node as a gpio controller
-
-- #gpio-cells:
- Usage: required
- Value type: <u32>
- Definition: must be 2. Specifying the pin number and flags, as defined
- in <dt-bindings/gpio/gpio.h>
-
-- gpio-ranges:
- Usage: required
- Value type: <prop-encoded-array>
- Definition: see ../gpio/gpio.txt
-
-- gpio-reserved-ranges:
- Usage: optional
- Value type: <prop-encoded-array>
- Definition: see ../gpio/gpio.txt
-
-Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
-a general description of GPIO and interrupt bindings.
-
-Please refer to pinctrl-bindings.txt in this directory for details of the
-common pinctrl bindings used by client devices, including the meaning of the
-phrase "pin configuration node".
-
-The pin configuration nodes act as a container for an arbitrary number of
-subnodes. Each of these subnodes represents some desired configuration for a
-pin, a group, or a list of pins or groups. This configuration can include the
-mux function to select on those pin(s)/group(s), and various pin configuration
-parameters, such as pull-up, drive strength, etc.
-
-
-PIN CONFIGURATION NODES:
-
-The name of each subnode is not important; all subnodes should be enumerated
-and processed purely based on their content.
-
-Each subnode only affects those parameters that are explicitly listed. In
-other words, a subnode that lists a mux function but no pin configuration
-parameters implies no information about any pin configuration parameters.
-Similarly, a pin subnode that describes a pullup parameter implies no
-information about e.g. the mux function.
-
-
-The following generic properties as defined in pinctrl-bindings.txt are valid
-to specify in a pin configuration subnode:
-
-- pins:
- Usage: required
- Value type: <string-array>
- Definition: List of gpio pins affected by the properties specified in
- this subnode.
-
- Valid pins are:
- gpio0-gpio118
- Supports mux, bias and drive-strength
-
- sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd,
- sdc2_data sdc1_rclk
- Supports bias and drive-strength
-
- ufs_reset
- Supports bias and drive-strength
-
-- function:
- Usage: required
- Value type: <string>
- Definition: Specify the alternative function to be configured for the
- specified pins. Functions are only valid for gpio pins.
- Valid values are:
-
- adsp_ext, agera_pll, aoss_cti, atest_char, atest_char0,
- atest_char1, atest_char2, atest_char3, atest_tsens,
- atest_tsens2, atest_usb1, atest_usb10, atest_usb11,
- atest_usb12, atest_usb13, atest_usb2, atest_usb20,
- atest_usb21, atest_usb22, atest_usb23, audio_ref,
- btfm_slimbus, cam_mclk, cci_async, cci_i2c, cci_timer0,
- cci_timer1, cci_timer2, cci_timer3, cci_timer4,
- cri_trng, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
- ddr_pxi2, ddr_pxi3, dp_hot, edp_lcd, gcc_gp1, gcc_gp2,
- gcc_gp3, gpio, gp_pdm0, gp_pdm1, gp_pdm2, gps_tx,
- jitter_bist, ldo_en, ldo_update, lpass_ext, mdp_vsync,
- mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s_0,
- mi2s_1, mi2s_2, mss_lte, m_voc, pa_indicator, phase_flag,
- PLL_BIST, pll_bypassnl, pll_reset, prng_rosc, qdss,
- qdss_cti, qlink_enable, qlink_request, qspi_clk, qspi_cs,
- qspi_data, qup00, qup01, qup02_i2c, qup02_uart, qup03,
- qup04_i2c, qup04_uart, qup05, qup10, qup11_i2c, qup11_uart,
- qup12, qup13_i2c, qup13_uart, qup14, qup15, sdc1_tb,
- sdc2_tb, sd_write, sp_cmu, tgu_ch0, tgu_ch1, tgu_ch2,
- tgu_ch3, tsense_pwm1, tsense_pwm2, uim1, uim2, uim_batt,
- usb_phy, vfr_1, _V_GPIO, _V_PPS_IN, _V_PPS_OUT,
- vsense_trigger, wlan1_adc0, wlan1_adc1, wlan2_adc0,
- wlan2_adc1,
-
-- bias-disable:
- Usage: optional
- Value type: <none>
- Definition: The specified pins should be configured as no pull.
-
-- bias-pull-down:
- Usage: optional
- Value type: <none>
- Definition: The specified pins should be configured as pull down.
-
-- bias-pull-up:
- Usage: optional
- Value type: <none>
- Definition: The specified pins should be configured as pull up.
-
-- output-high:
- Usage: optional
- Value type: <none>
- Definition: The specified pins are configured in output mode, driven
- high.
- Not valid for sdc pins.
-
-- output-low:
- Usage: optional
- Value type: <none>
- Definition: The specified pins are configured in output mode, driven
- low.
- Not valid for sdc pins.
-
-- drive-strength:
- Usage: optional
- Value type: <u32>
- Definition: Selects the drive strength for the specified pins, in mA.
- Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
-
-Example:
-
- tlmm: pinctrl@3500000 {
- compatible = "qcom,sc7180-pinctrl";
- reg = <0x3500000 0x300000>,
- <0x3900000 0x300000>,
- <0x3D00000 0x300000>;
- reg-names = "west", "north", "south";
- interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&tlmm 0 0 119>;
- gpio-reserved-ranges = <0 4>, <106 4>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc7180-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc7180-pinctrl.yaml
new file mode 100644
index 000000000000..464f1031d15d
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc7180-pinctrl.yaml
@@ -0,0 +1,162 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,sc7180-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SC7180 TLMM pin controller
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+ - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+
+description:
+ Top Level Mode Multiplexer pin controller in Qualcomm SC7180 SoC.
+
+properties:
+ compatible:
+ const: qcom,sc7180-pinctrl
+
+ reg:
+ maxItems: 3
+
+ reg-names:
+ items:
+ - const: west
+ - const: north
+ - const: south
+
+ interrupts: true
+ interrupt-controller: true
+ "#interrupt-cells": true
+ gpio-controller: true
+ "#gpio-cells": true
+ gpio-ranges: true
+ wakeup-parent: true
+
+ gpio-reserved-ranges:
+ minItems: 1
+ maxItems: 60
+
+ gpio-line-names:
+ maxItems: 119
+
+patternProperties:
+ "-state$":
+ oneOf:
+ - $ref: "#/$defs/qcom-sc7180-tlmm-state"
+ - patternProperties:
+ "-pins$":
+ $ref: "#/$defs/qcom-sc7180-tlmm-state"
+ additionalProperties: false
+
+$defs:
+ qcom-sc7180-tlmm-state:
+ type: object
+ description:
+ Pinctrl node's client devices use subnodes for desired pin configuration.
+ Client device subnodes use below standard properties.
+ $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
+
+ properties:
+ pins:
+ description:
+ List of gpio pins affected by the properties specified in this
+ subnode.
+ items:
+ oneOf:
+ - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-8])$"
+ - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk,
+ sdc2_cmd, sdc2_data, ufs_reset ]
+ minItems: 1
+ maxItems: 36
+
+ function:
+ description:
+ Specify the alternative function to be configured for the specified
+ pins.
+
+ enum: [ adsp_ext, agera_pll, aoss_cti, atest_char, atest_char0,
+ atest_char1, atest_char2, atest_char3, atest_tsens,
+ atest_tsens2, atest_usb1, atest_usb10, atest_usb11,
+ atest_usb12, atest_usb13, atest_usb2, atest_usb20, atest_usb21,
+ atest_usb22, atest_usb23, audio_ref, btfm_slimbus, cam_mclk,
+ cci_async, cci_i2c, cci_timer0, cci_timer1, cci_timer2,
+ cci_timer3, cci_timer4, cri_trng, dbg_out, ddr_bist, ddr_pxi0,
+ ddr_pxi1, ddr_pxi2, ddr_pxi3, dp_hot, edp_lcd, gcc_gp1,
+ gcc_gp2, gcc_gp3, gpio, gp_pdm0, gp_pdm1, gp_pdm2, gps_tx,
+ jitter_bist, ldo_en, ldo_update, lpass_ext, mdp_vsync,
+ mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s_0, mi2s_1,
+ mi2s_2, mss_lte, m_voc, pa_indicator, phase_flag, PLL_BIST,
+ pll_bypassnl, pll_reset, prng_rosc, qdss, qdss_cti,
+ qlink_enable, qlink_request, qspi_clk, qspi_cs, qspi_data,
+ qup00, qup01, qup02_i2c, qup02_uart, qup03, qup04_i2c,
+ qup04_uart, qup05, qup10, qup11_i2c, qup11_uart, qup12,
+ qup13_i2c, qup13_uart, qup14, qup15, sdc1_tb, sdc2_tb,
+ sd_write, sp_cmu, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3,
+ tsense_pwm1, tsense_pwm2, uim1, uim2, uim_batt, usb_phy, vfr_1,
+ _V_GPIO, _V_PPS_IN, _V_PPS_OUT, vsense_trigger, wlan1_adc0,
+ wlan1_adc1, wlan2_adc0, wlan2_adc1 ]
+
+ drive-strength:
+ enum: [2, 4, 6, 8, 10, 12, 14, 16]
+ description:
+ Selects the drive strength for the specified pins, in mA.
+
+ bias-pull-down: true
+ bias-pull-up: true
+ bias-disable: true
+ input-enable: true
+ output-high: true
+ output-low: true
+
+ required:
+ - pins
+
+ additionalProperties: false
+
+allOf:
+ - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
+
+required:
+ - compatible
+ - reg
+ - reg-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ tlmm: pinctrl@3500000 {
+ compatible = "qcom,sc7180-pinctrl";
+ reg = <0x03500000 0x300000>,
+ <0x03900000 0x300000>,
+ <0x03d00000 0x300000>;
+ reg-names = "west", "north", "south";
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 120>;
+ wakeup-parent = <&pdc>;
+
+ dp_hot_plug_det: dp-hot-plug-det-state {
+ pins = "gpio117";
+ function = "dp_hot";
+ };
+
+ qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
+ spi-pins {
+ pins = "gpio53", "gpio54", "gpio55";
+ function = "qup15";
+ };
+
+ cs-pins {
+ pins = "gpio56";
+ function = "gpio";
+ };
+ };
+ };
--
2.34.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH v2 3/3] dt-bindings: pinctrl: qcom,sc7180: convert to dtschema
2022-10-13 18:47 ` [PATCH v2 3/3] dt-bindings: pinctrl: qcom,sc7180: convert to dtschema Krzysztof Kozlowski
@ 2022-10-14 18:02 ` Doug Anderson
2022-10-16 16:30 ` Krzysztof Kozlowski
0 siblings, 1 reply; 8+ messages in thread
From: Doug Anderson @ 2022-10-14 18:02 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Andy Gross, Bjorn Andersson, Konrad Dybcio, Linus Walleij,
Rob Herring, Krzysztof Kozlowski, linux-arm-msm, linux-gpio,
devicetree, linux-kernel, Rob Herring
Hi,
On Thu, Oct 13, 2022 at 11:49 AM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc7180-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc7180-pinctrl.yaml
> new file mode 100644
> index 000000000000..464f1031d15d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc7180-pinctrl.yaml
[ ... cut ... ]
> @@ -0,0 +1,162 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/qcom,sc7180-pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm SC7180 TLMM pin controller
> +
> +maintainers:
> + - Bjorn Andersson <andersson@kernel.org>
> + - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> +
> +description:
> + Top Level Mode Multiplexer pin controller in Qualcomm SC7180 SoC.
> +
> +properties:
> + compatible:
> + const: qcom,sc7180-pinctrl
> +
> + reg:
> + maxItems: 3
> +
> + reg-names:
> + items:
> + - const: west
> + - const: north
> + - const: south
> +
> + interrupts: true
> + interrupt-controller: true
> + "#interrupt-cells": true
> + gpio-controller: true
> + "#gpio-cells": true
> + gpio-ranges: true
> + wakeup-parent: true
Do you need interrupts/interrupt-controller/.../... ? Below you
include allOf "/schemas/pinctrl/qcom,tlmm-common.yaml". Won't you
magically get those from there? Why do you need to duplicate this?
> + gpio-reserved-ranges:
> + minItems: 1
> + maxItems: 60
> +
> + gpio-line-names:
> + maxItems: 119
> +
> +patternProperties:
> + "-state$":
> + oneOf:
> + - $ref: "#/$defs/qcom-sc7180-tlmm-state"
> + - patternProperties:
> + "-pins$":
> + $ref: "#/$defs/qcom-sc7180-tlmm-state"
> + additionalProperties: false
> +
> +$defs:
> + qcom-sc7180-tlmm-state:
> + type: object
> + description:
> + Pinctrl node's client devices use subnodes for desired pin configuration.
> + Client device subnodes use below standard properties.
> + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
> +
> + properties:
> + pins:
> + description:
> + List of gpio pins affected by the properties specified in this
> + subnode.
> + items:
> + oneOf:
> + - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-8])$"
> + - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk,
> + sdc2_cmd, sdc2_data, ufs_reset ]
> + minItems: 1
> + maxItems: 36
> +
> + function:
> + description:
> + Specify the alternative function to be configured for the specified
> + pins.
> +
> + enum: [ adsp_ext, agera_pll, aoss_cti, atest_char, atest_char0,
> + atest_char1, atest_char2, atest_char3, atest_tsens,
> + atest_tsens2, atest_usb1, atest_usb10, atest_usb11,
> + atest_usb12, atest_usb13, atest_usb2, atest_usb20, atest_usb21,
> + atest_usb22, atest_usb23, audio_ref, btfm_slimbus, cam_mclk,
> + cci_async, cci_i2c, cci_timer0, cci_timer1, cci_timer2,
> + cci_timer3, cci_timer4, cri_trng, dbg_out, ddr_bist, ddr_pxi0,
> + ddr_pxi1, ddr_pxi2, ddr_pxi3, dp_hot, edp_lcd, gcc_gp1,
> + gcc_gp2, gcc_gp3, gpio, gp_pdm0, gp_pdm1, gp_pdm2, gps_tx,
> + jitter_bist, ldo_en, ldo_update, lpass_ext, mdp_vsync,
> + mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s_0, mi2s_1,
> + mi2s_2, mss_lte, m_voc, pa_indicator, phase_flag, PLL_BIST,
> + pll_bypassnl, pll_reset, prng_rosc, qdss, qdss_cti,
> + qlink_enable, qlink_request, qspi_clk, qspi_cs, qspi_data,
> + qup00, qup01, qup02_i2c, qup02_uart, qup03, qup04_i2c,
> + qup04_uart, qup05, qup10, qup11_i2c, qup11_uart, qup12,
> + qup13_i2c, qup13_uart, qup14, qup15, sdc1_tb, sdc2_tb,
> + sd_write, sp_cmu, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3,
> + tsense_pwm1, tsense_pwm2, uim1, uim2, uim_batt, usb_phy, vfr_1,
> + _V_GPIO, _V_PPS_IN, _V_PPS_OUT, vsense_trigger, wlan1_adc0,
> + wlan1_adc1, wlan2_adc0, wlan2_adc1 ]
> +
> + drive-strength:
> + enum: [2, 4, 6, 8, 10, 12, 14, 16]
> + description:
> + Selects the drive strength for the specified pins, in mA.
Again, why do you need to duplicate. The yaml is weak in me, but I
think you're effectively subclassing
"qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state", right? It has the
exact same definition of drive-strength. Why duplicate it?
> + bias-pull-down: true
> + bias-pull-up: true
> + bias-disable: true
> + input-enable: true
> + output-high: true
> + output-low: true
Again, maybe the above properties aren't needed? Don't you inherit
them from tlmm-common?
-Doug
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 3/3] dt-bindings: pinctrl: qcom,sc7180: convert to dtschema
2022-10-14 18:02 ` Doug Anderson
@ 2022-10-16 16:30 ` Krzysztof Kozlowski
0 siblings, 0 replies; 8+ messages in thread
From: Krzysztof Kozlowski @ 2022-10-16 16:30 UTC (permalink / raw)
To: Doug Anderson
Cc: Andy Gross, Bjorn Andersson, Konrad Dybcio, Linus Walleij,
Rob Herring, Krzysztof Kozlowski, linux-arm-msm, linux-gpio,
devicetree, linux-kernel, Rob Herring
On 14/10/2022 14:02, Doug Anderson wrote:
> Hi,
>
> On Thu, Oct 13, 2022 at 11:49 AM Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
>>
>> diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc7180-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc7180-pinctrl.yaml
>> new file mode 100644
>> index 000000000000..464f1031d15d
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc7180-pinctrl.yaml
>
> [ ... cut ... ]
>
>> @@ -0,0 +1,162 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/pinctrl/qcom,sc7180-pinctrl.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm SC7180 TLMM pin controller
>> +
>> +maintainers:
>> + - Bjorn Andersson <andersson@kernel.org>
>> + - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>> +
>> +description:
>> + Top Level Mode Multiplexer pin controller in Qualcomm SC7180 SoC.
>> +
>> +properties:
>> + compatible:
>> + const: qcom,sc7180-pinctrl
>> +
>> + reg:
>> + maxItems: 3
>> +
>> + reg-names:
>> + items:
>> + - const: west
>> + - const: north
>> + - const: south
>> +
>> + interrupts: true
>> + interrupt-controller: true
>> + "#interrupt-cells": true
>> + gpio-controller: true
>> + "#gpio-cells": true
>> + gpio-ranges: true
>> + wakeup-parent: true
>
> Do you need interrupts/interrupt-controller/.../... ? Below you
> include allOf "/schemas/pinctrl/qcom,tlmm-common.yaml". Won't you
> magically get those from there? Why do you need to duplicate this?
There is additionalProperties:false, so every property from referenced
schema has to be included.
The true solution would be to switch to unevaluatedProperties:false but
then we accept all properties from:
1. qcom,tlmm-common.yaml - not a problem, we already mention all of them
here with :true
2. pinctrl.yaml - we would now allow to use pinctrl-use-default.
3. any other future common properties.
>
>
>> + gpio-reserved-ranges:
>> + minItems: 1
>> + maxItems: 60
>> +
>> + gpio-line-names:
>> + maxItems: 119
>> +
>> +patternProperties:
>> + "-state$":
>> + oneOf:
>> + - $ref: "#/$defs/qcom-sc7180-tlmm-state"
>> + - patternProperties:
>> + "-pins$":
>> + $ref: "#/$defs/qcom-sc7180-tlmm-state"
>> + additionalProperties: false
>> +
>> +$defs:
>> + qcom-sc7180-tlmm-state:
>> + type: object
>> + description:
>> + Pinctrl node's client devices use subnodes for desired pin configuration.
>> + Client device subnodes use below standard properties.
>> + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
>> +
>> + properties:
>> + pins:
>> + description:
>> + List of gpio pins affected by the properties specified in this
>> + subnode.
>> + items:
>> + oneOf:
>> + - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-8])$"
>> + - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk,
>> + sdc2_cmd, sdc2_data, ufs_reset ]
>> + minItems: 1
>> + maxItems: 36
>> +
>> + function:
>> + description:
>> + Specify the alternative function to be configured for the specified
>> + pins.
>> +
>> + enum: [ adsp_ext, agera_pll, aoss_cti, atest_char, atest_char0,
>> + atest_char1, atest_char2, atest_char3, atest_tsens,
>> + atest_tsens2, atest_usb1, atest_usb10, atest_usb11,
>> + atest_usb12, atest_usb13, atest_usb2, atest_usb20, atest_usb21,
>> + atest_usb22, atest_usb23, audio_ref, btfm_slimbus, cam_mclk,
>> + cci_async, cci_i2c, cci_timer0, cci_timer1, cci_timer2,
>> + cci_timer3, cci_timer4, cri_trng, dbg_out, ddr_bist, ddr_pxi0,
>> + ddr_pxi1, ddr_pxi2, ddr_pxi3, dp_hot, edp_lcd, gcc_gp1,
>> + gcc_gp2, gcc_gp3, gpio, gp_pdm0, gp_pdm1, gp_pdm2, gps_tx,
>> + jitter_bist, ldo_en, ldo_update, lpass_ext, mdp_vsync,
>> + mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s_0, mi2s_1,
>> + mi2s_2, mss_lte, m_voc, pa_indicator, phase_flag, PLL_BIST,
>> + pll_bypassnl, pll_reset, prng_rosc, qdss, qdss_cti,
>> + qlink_enable, qlink_request, qspi_clk, qspi_cs, qspi_data,
>> + qup00, qup01, qup02_i2c, qup02_uart, qup03, qup04_i2c,
>> + qup04_uart, qup05, qup10, qup11_i2c, qup11_uart, qup12,
>> + qup13_i2c, qup13_uart, qup14, qup15, sdc1_tb, sdc2_tb,
>> + sd_write, sp_cmu, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3,
>> + tsense_pwm1, tsense_pwm2, uim1, uim2, uim_batt, usb_phy, vfr_1,
>> + _V_GPIO, _V_PPS_IN, _V_PPS_OUT, vsense_trigger, wlan1_adc0,
>> + wlan1_adc1, wlan2_adc0, wlan2_adc1 ]
>> +
>> + drive-strength:
>> + enum: [2, 4, 6, 8, 10, 12, 14, 16]
>> + description:
>> + Selects the drive strength for the specified pins, in mA.
>
> Again, why do you need to duplicate. The yaml is weak in me, but I
> think you're effectively subclassing
> "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state", right? It has the
> exact same definition of drive-strength. Why duplicate it?
Yes, this can be dropped.
>
>
>> + bias-pull-down: true
>> + bias-pull-up: true
>> + bias-disable: true
>> + input-enable: true
>> + output-high: true
>> + output-low: true
>
> Again, maybe the above properties aren't needed? Don't you inherit
> them from tlmm-common?
From tlmm-common yes, however without this and
additionalProperties:false we would accept everything from pincfg-node
which too much. The binding/hardware does not support all of them, I think.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v2 1/3] arm64: dts: qcom: sc7180-trogdor-homestar: fully configure secondary I2S pins
2022-10-13 18:46 [PATCH v2 1/3] arm64: dts: qcom: sc7180-trogdor-homestar: fully configure secondary I2S pins Krzysztof Kozlowski
2022-10-13 18:46 ` [PATCH v2 2/3] arm64: dts: qcom: sc7180: align TLMM pin configuration with DT schema Krzysztof Kozlowski
2022-10-13 18:47 ` [PATCH v2 3/3] dt-bindings: pinctrl: qcom,sc7180: convert to dtschema Krzysztof Kozlowski
@ 2022-10-14 17:51 ` Doug Anderson
2 siblings, 0 replies; 8+ messages in thread
From: Doug Anderson @ 2022-10-14 17:51 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Andy Gross, Bjorn Andersson, Konrad Dybcio, Linus Walleij,
Rob Herring, Krzysztof Kozlowski, linux-arm-msm, linux-gpio,
devicetree, linux-kernel
Hi,
On Thu, Oct 13, 2022 at 11:49 AM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> The Trogdor Homestar DTSI adds additional GPIO52 pin to secondary I2S pins
> ("sec_mi2s_active") and configures it to "mi2s_1" function.
>
> The Trogdor DTSI (which is included by Homestar) configures drive
> strength and bias for all "sec_mi2s_active" pins, thus the intention was
> to apply this configuration also to GPIO52 on Homestar.
>
> Reported-by: Doug Anderson <dianders@chromium.org>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Fixes: be0416a3f917 ("arm64: dts: qcom: Add sc7180-trogdor-homestar")
> ---
>
> Changes since v1:
> 1. New patch
>
> Not tested on hardware.
>
> Cc: Doug Anderson <dianders@chromium.org>
> ---
> arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi
> index 1bd6c7dcd9e9..bfab67f4a7c9 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi
> @@ -194,6 +194,12 @@ pinmux {
> pins = "gpio49", "gpio50", "gpio51", "gpio52";
> function = "mi2s_1";
> };
> +
> + pinconf {
> + pins = "gpio49", "gpio50", "gpio51", "gpio52";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
Personally I wouldn't have replicated the "drive-strength" and
"bias-pull-down" here (nor would I have replicated the "function =
"mi2s_1"" in the node above but I didn't notice it before). ...but it
doesn't really hurt, the resulting dtb (after combining all includes)
isn't changed, and you've about to clean this up in your next patch.
Thus:
Reviewed-by: Douglas Anderson <dianders@chromium.org>
^ permalink raw reply [flat|nested] 8+ messages in thread