From: "Jiawen Wu" <jiawenwu@trustnetic.com>
To: "'Andrew Lunn'" <andrew@lunn.ch>
Cc: "'Andy Shevchenko'" <andy.shevchenko@gmail.com>,
<netdev@vger.kernel.org>, <jarkko.nikula@linux.intel.com>,
<andriy.shevchenko@linux.intel.com>,
<mika.westerberg@linux.intel.com>, <jsd@semihalf.com>,
<Jose.Abreu@synopsys.com>, <hkallweit1@gmail.com>,
<linux@armlinux.org.uk>, <linux-i2c@vger.kernel.org>,
<linux-gpio@vger.kernel.org>, <mengyuanlou@net-swift.com>
Subject: RE: [PATCH net-next v8 6/9] net: txgbe: Support GPIO to SFP socket
Date: Fri, 19 May 2023 16:24:15 +0800 [thread overview]
Message-ID: <02ad01d98a2b$4cd080e0$e67182a0$@trustnetic.com> (raw)
In-Reply-To: <1e1615b3-566c-490c-8b1a-78f5521ca0b0@lunn.ch>
On Thursday, May 18, 2023 8:49 PM, Andrew Lunn wrote:
> > > I _think_ you are mixing upstream IRQs and downstream IRQs.
> > >
> > > Interrupts are arranged in trees. The CPU itself only has one or two
> > > interrupts. e.g. for ARM you have FIQ and IRQ. When the CPU gets an
> > > interrupt, you look in the interrupt controller to see what external
> > > or internal interrupt triggered the CPU interrupt. And that interrupt
> > > controller might indicate the interrupt came from another interrupt
> > > controller. Hence the tree structure. And each node in the tree is
> > > considered an interrupt domain.
> > >
> > > A GPIO controller can also be an interrupt controller. It has an
> > > upstream interrupt, going to the controller above it. And it has
> > > downstream interrupts, the GPIO lines coming into it which can cause
> > > an interrupt. And the GPIO interrupt controller is a domain.
> > >
> > > So what exactly does gpio_regmap_config.irq_domain mean? Is it the
> > > domain of the upstream interrupt controller? Is it an empty domain
> > > structure to be used by the GPIO interrupt controller? It is very
> > > unlikely to have anything to do with the SFP devices below it.
> >
> > Sorry, since I don't know much about interrupt, it is difficult to understand
> > regmap-irq in a short time. There are many questions about regmap-irq.
> >
> > When I want to add an IRQ chip for regmap, for the further irq_domain,
> > I need to pass a parameter of IRQ, and this IRQ will be requested with handler:
> > regmap_irq_thread(). Which IRQ does it mean?
>
> That is your upstream IRQ, the interrupt indicating one of your GPIO
> lines has changed state.
>
> > In the previous code of using
> > devm_gpiochip_add_data(), I set the MSI-X interrupt as gpio-irq's parent, but
> > it was used to set chained handler only. Should the parent be this IRQ? I found
> > the error with irq_free_descs and irq_domain_remove when I remove txgbe.ko.
>
> Do you have one MSI-X dedicated for GPIOs. Or is it your general MAC
> interrupt, and you need to read an interrupt controller register to
> determine it was GPIOs which triggered the interrupt?
>
> If you are getting errors when removing the driver it means you are
> missing some level of undoing what us done in probe. Are you sure
> regmap_del_irq_chip() is being called on unload?
>
> > As you said, the interrupt of each tree node has its domain. Can I understand
> > that there are two layer in the interrupt tree for MSI-X and GPIOs, and requesting
> > them separately is not conflicting? Although I thought so, but after I implement
> > gpio-regmap, SFP driver even could not find gpio_desc. Maybe I missed something
> > on registering gpio-regmap...
>
> That is probably some sort of naming issue. You might want to add some
> prints in swnode_find_gpio() and gpiochip_find() to see what it is
> looking for vs what the name actually is.
It's true for the problem of name, but there is another problem. SFP driver has
successfully got gpio_desc, then it failed to get gpio_irq from gpio_desc (with error
return -517). I traced the function gpiod_to_irq():
gc = desc->gdev->chip;
offset = gpio_chip_hwgpio(desc);
if (gc->to_irq) {
int retirq = gc->to_irq(gc, offset);
/* Zero means NO_IRQ */
if (!retirq)
return -ENXIO;
return retirq;
}
'gc->to_irq = gpiochip_to_irq' was set in [4]gpiochip_irqchip_add_domain().
So:
static int gpiochip_to_irq(struct gpio_chip *gc, unsigned int offset)
{
struct irq_domain *domain = gc->irq.domain;
#ifdef CONFIG_GPIOLIB_IRQCHIP
/*
* Avoid race condition with other code, which tries to lookup
* an IRQ before the irqchip has been properly registered,
* i.e. while gpiochip is still being brought up.
*/
if (!gc->irq.initialized)
return -EPROBE_DEFER;
#endif
gc->irq.initialized is set to true at the end of [3]gpiochip_add_irqchip() only.
Firstly, it checks if irqchip is NULL:
static int gpiochip_add_irqchip(struct gpio_chip *gc,
struct lock_class_key *lock_key,
struct lock_class_key *request_key)
{
struct fwnode_handle *fwnode = dev_fwnode(&gc->gpiodev->dev);
struct irq_chip *irqchip = gc->irq.chip;
unsigned int type;
unsigned int i;
if (!irqchip)
return 0;
The result shows that it was NULL, so gc->irq.initialized = false.
Above all, return irq = -EPROBE_DEFER.
So let's sort the function calls. In chronological order, [1] calls [2], [2] calls
[3], then [1] calls [4]. The irq_chip was added to irq_domain->host_data->irq_chip
before [1]. But I don't find where to convert gpio_chip->irq.domain->host_data->irq_chip
to gpio_chip->irq.chip, it seems like it should happen after [4] ? But if it wants to use
'gc->to_irq' successfully, it should happen before [3]?
[1] gpio_regmap_register()
[2] gpiochip_add_data()
[3] gpiochip_add_irqchip()
[4] gpiochip_irqchip_add_domain()
I'm sorry that I described the problem in a confusing way, apologize if I missed
some code that caused this confusion.
next prev parent reply other threads:[~2023-05-19 8:25 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-15 6:31 [PATCH net-next v8 0/9] TXGBE PHYLINK support Jiawen Wu
2023-05-15 6:31 ` [PATCH net-next v8 1/9] net: txgbe: Add software nodes to support phylink Jiawen Wu
2023-05-15 6:31 ` [PATCH net-next v8 2/9] i2c: designware: Add driver support for Wangxun 10Gb NIC Jiawen Wu
2023-05-15 9:24 ` andy.shevchenko
2023-05-17 8:49 ` Jarkko Nikula
2023-05-17 9:25 ` Jiawen Wu
2023-05-17 9:44 ` Andy Shevchenko
2023-05-19 13:26 ` Jarkko Nikula
2023-05-17 9:40 ` Andy Shevchenko
2023-05-15 6:31 ` [PATCH net-next v8 3/9] net: txgbe: Register fixed rate clock Jiawen Wu
2023-05-15 6:31 ` [PATCH net-next v8 4/9] net: txgbe: Register I2C platform device Jiawen Wu
2023-05-15 9:29 ` andy.shevchenko
2023-05-15 6:31 ` [PATCH net-next v8 5/9] net: txgbe: Add SFP module identify Jiawen Wu
2023-05-15 6:31 ` [PATCH net-next v8 6/9] net: txgbe: Support GPIO to SFP socket Jiawen Wu
2023-05-15 9:42 ` andy.shevchenko
2023-05-16 2:38 ` Jiawen Wu
2023-05-16 7:12 ` Andy Shevchenko
2023-05-16 9:39 ` Paolo Abeni
2023-05-16 10:31 ` Russell King (Oracle)
2023-05-17 2:55 ` Jiawen Wu
2023-05-17 10:26 ` Andy Shevchenko
2023-05-17 15:00 ` Andrew Lunn
2023-05-18 11:49 ` Jiawen Wu
2023-05-18 12:27 ` Andy Shevchenko
2023-05-18 16:02 ` Michael Walle
2023-05-18 16:07 ` Andy Shevchenko
2023-05-23 9:55 ` Jiawen Wu
2023-05-23 11:07 ` Andy Shevchenko
2023-05-23 11:10 ` Andy Shevchenko
2023-05-18 12:48 ` Andrew Lunn
2023-05-19 2:25 ` Jiawen Wu
2023-05-19 13:13 ` Andrew Lunn
2023-05-22 9:00 ` Jiawen Wu
2023-05-22 9:06 ` Jiawen Wu
2023-05-22 10:58 ` Jiawen Wu
2023-05-22 21:36 ` 'Andy Shevchenko'
2023-05-23 2:08 ` Jiawen Wu
2023-05-23 6:12 ` Jiawen Wu
2023-05-19 8:24 ` Jiawen Wu [this message]
2023-05-19 13:24 ` Andrew Lunn
2023-05-15 21:36 ` Andy Shevchenko
2023-05-16 2:05 ` Jiawen Wu
2023-05-17 10:29 ` 'Andy Shevchenko'
2023-05-15 6:31 ` [PATCH net-next v8 7/9] net: pcs: Add 10GBASE-R mode for Synopsys Designware XPCS Jiawen Wu
2023-05-15 6:31 ` [PATCH net-next v8 8/9] net: txgbe: Implement phylink pcs Jiawen Wu
2023-05-16 2:45 ` Lars-Peter Clausen
2023-05-15 6:32 ` [PATCH net-next v8 9/9] net: txgbe: Support phylink MAC layer Jiawen Wu
2023-05-16 9:43 ` Paolo Abeni
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