* [PATCH] pinctrl: meson-gxl: add tsin_a pins
@ 2017-06-08 13:09 Jerome Brunet
2017-06-08 13:49 ` Andreas Färber
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Jerome Brunet @ 2017-06-08 13:09 UTC (permalink / raw)
To: Linus Walleij, Kevin Hilman
Cc: Jerome Brunet, Carlo Caione, linux-gpio, linux-amlogic,
linux-kernel
Add Tsin A pins to bank DV and X.
We don't have a driver for the tsin yet but since the tsin A pinmux is
enabled by default at boot time, declaring this pinmux is required to
properly operate on GPIOX.
Without this change, GPIOX 8, 9, 10 and 11 can't be driven as GPIO output
as the tsin A seems to have priority.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
drivers/pinctrl/meson/pinctrl-meson-gxl.c | 36 +++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxl.c b/drivers/pinctrl/meson/pinctrl-meson-gxl.c
index 190f50c6a9ba..2624b0d4d3c4 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-gxl.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-gxl.c
@@ -243,6 +243,25 @@ static const unsigned int spdif_out_h_pins[] = { PIN(GPIOH_4, EE_OFF) };
static const unsigned int eth_link_led_pins[] = { PIN(GPIOZ_14, EE_OFF) };
static const unsigned int eth_act_led_pins[] = { PIN(GPIOZ_15, EE_OFF) };
+static const unsigned int tsin_a_d0_pins[] = { PIN(GPIODV_0, EE_OFF) };
+static const unsigned int tsin_a_d0_x_pins[] = { PIN(GPIOX_10, EE_OFF) };
+static const unsigned int tsin_a_clk_pins[] = { PIN(GPIODV_8, EE_OFF) };
+static const unsigned int tsin_a_clk_x_pins[] = { PIN(GPIOX_11, EE_OFF) };
+static const unsigned int tsin_a_sop_pins[] = { PIN(GPIODV_9, EE_OFF) };
+static const unsigned int tsin_a_sop_x_pins[] = { PIN(GPIOX_8, EE_OFF) };
+static const unsigned int tsin_a_d_valid_pins[] = { PIN(GPIODV_10, EE_OFF) };
+static const unsigned int tsin_a_d_valid_x_pins[] = { PIN(GPIOX_9, EE_OFF) };
+static const unsigned int tsin_a_fail_pins[] = { PIN(GPIODV_11, EE_OFF) };
+static const unsigned int tsin_a_dp_pins[] = {
+ PIN(GPIODV_1, EE_OFF),
+ PIN(GPIODV_2, EE_OFF),
+ PIN(GPIODV_3, EE_OFF),
+ PIN(GPIODV_4, EE_OFF),
+ PIN(GPIODV_5, EE_OFF),
+ PIN(GPIODV_6, EE_OFF),
+ PIN(GPIODV_7, EE_OFF),
+};
+
static const struct pinctrl_pin_desc meson_gxl_aobus_pins[] = {
MESON_PIN(GPIOAO_0, 0),
MESON_PIN(GPIOAO_1, 0),
@@ -421,6 +440,10 @@ static struct meson_pmx_group meson_gxl_periphs_groups[] = {
GROUP(spi_miso, 5, 2),
GROUP(spi_ss0, 5, 1),
GROUP(spi_sclk, 5, 0),
+ GROUP(tsin_a_sop_x, 6, 3),
+ GROUP(tsin_a_d_valid_x, 6, 2),
+ GROUP(tsin_a_d0_x, 6, 1),
+ GROUP(tsin_a_clk_x, 6, 0),
/* Bank Z */
GROUP(eth_mdio, 4, 23),
@@ -469,6 +492,12 @@ static struct meson_pmx_group meson_gxl_periphs_groups[] = {
GROUP(i2c_sck_c, 1, 10),
GROUP(pwm_b, 2, 11),
GROUP(pwm_d, 2, 12),
+ GROUP(tsin_a_d0, 2, 4),
+ GROUP(tsin_a_dp, 2, 3),
+ GROUP(tsin_a_clk, 2, 2),
+ GROUP(tsin_a_sop, 2, 1),
+ GROUP(tsin_a_d_valid, 2, 0),
+ GROUP(tsin_a_fail, 1, 31),
/* Bank BOOT */
GROUP(emmc_nand_d07, 7, 31),
@@ -675,6 +704,12 @@ static const char * const eth_led_groups[] = {
"eth_link_led", "eth_act_led",
};
+static const char * const tsin_a_groups[] = {
+ "tsin_a_clk", "tsin_a_clk_x", "tsin_a_sop", "tsin_a_sop_x",
+ "tsin_a_d_valid", "tsin_a_d_valid_x", "tsin_a_d0", "tsin_a_d0_x",
+ "tsin_a_dp", "tsin_a_fail",
+};
+
static const char * const gpio_aobus_groups[] = {
"GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4",
"GPIOAO_5", "GPIOAO_6", "GPIOAO_7", "GPIOAO_8", "GPIOAO_9",
@@ -747,6 +782,7 @@ static struct meson_pmx_func meson_gxl_periphs_functions[] = {
FUNCTION(i2s_out),
FUNCTION(spdif_out),
FUNCTION(eth_led),
+ FUNCTION(tsin_a),
};
static struct meson_pmx_func meson_gxl_aobus_functions[] = {
--
2.9.4
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH] pinctrl: meson-gxl: add tsin_a pins
2017-06-08 13:09 [PATCH] pinctrl: meson-gxl: add tsin_a pins Jerome Brunet
@ 2017-06-08 13:49 ` Andreas Färber
2017-06-08 13:53 ` Jerome Brunet
2017-06-09 9:54 ` Neil Armstrong
2017-06-16 9:10 ` Linus Walleij
2 siblings, 1 reply; 7+ messages in thread
From: Andreas Färber @ 2017-06-08 13:49 UTC (permalink / raw)
To: Jerome Brunet
Cc: Linus Walleij, Kevin Hilman, Carlo Caione, linux-gpio,
linux-amlogic, linux-kernel
Am 08.06.2017 um 15:09 schrieb Jerome Brunet:
> Add Tsin A pins to bank DV and X.
> We don't have a driver for the tsin yet but since the tsin A pinmux is
> enabled by default at boot time, declaring this pinmux is required to
> properly operate on GPIOX.
>
> Without this change, GPIOX 8, 9, 10 and 11 can't be driven as GPIO output
> as the tsin A seems to have priority.
Should this get a Fixes header then for stable backports?
>
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
> ---
> drivers/pinctrl/meson/pinctrl-meson-gxl.c | 36 +++++++++++++++++++++++++++++++
> 1 file changed, 36 insertions(+)
Looks OK AFAICT.
Cheers,
Andreas
--
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG Nürnberg)
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] pinctrl: meson-gxl: add tsin_a pins
2017-06-08 13:49 ` Andreas Färber
@ 2017-06-08 13:53 ` Jerome Brunet
2017-06-08 13:58 ` Andreas Färber
0 siblings, 1 reply; 7+ messages in thread
From: Jerome Brunet @ 2017-06-08 13:53 UTC (permalink / raw)
To: Andreas Färber
Cc: Linus Walleij, Kevin Hilman, Carlo Caione, linux-gpio,
linux-amlogic, linux-kernel
On Thu, 2017-06-08 at 15:49 +0200, Andreas Färber wrote:
> Am 08.06.2017 um 15:09 schrieb Jerome Brunet:
> > Add Tsin A pins to bank DV and X.
> > We don't have a driver for the tsin yet but since the tsin A pinmux is
> > enabled by default at boot time, declaring this pinmux is required to
> > properly operate on GPIOX.
> >
> > Without this change, GPIOX 8, 9, 10 and 11 can't be driven as GPIO output
> > as the tsin A seems to have priority.
>
> Should this get a Fixes header then for stable backports?
Nothing is wrong with what is already in. This is merely an addition.
If we go that way, all commit to this file should have a Fixes to the
initial commit. This seems a bit extreme to me ...
>
> >
> > Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
> > ---
> > drivers/pinctrl/meson/pinctrl-meson-gxl.c | 36
> > +++++++++++++++++++++++++++++++
> > 1 file changed, 36 insertions(+)
>
> Looks OK AFAICT.
>
> Cheers,
> Andreas
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] pinctrl: meson-gxl: add tsin_a pins
2017-06-08 13:53 ` Jerome Brunet
@ 2017-06-08 13:58 ` Andreas Färber
2017-06-08 14:05 ` Jerome Brunet
0 siblings, 1 reply; 7+ messages in thread
From: Andreas Färber @ 2017-06-08 13:58 UTC (permalink / raw)
To: Jerome Brunet
Cc: Linus Walleij, Kevin Hilman, Carlo Caione, linux-gpio,
linux-amlogic, linux-kernel
Am 08.06.2017 um 15:53 schrieb Jerome Brunet:
> On Thu, 2017-06-08 at 15:49 +0200, Andreas Färber wrote:
>> Am 08.06.2017 um 15:09 schrieb Jerome Brunet:
>>> Add Tsin A pins to bank DV and X.
>>> We don't have a driver for the tsin yet but since the tsin A pinmux is
>>> enabled by default at boot time, declaring this pinmux is required to
>>> properly operate on GPIOX.
>>>
>>> Without this change, GPIOX 8, 9, 10 and 11 can't be driven as GPIO output
>>> as the tsin A seems to have priority.
>>
>> Should this get a Fixes header then for stable backports?
>
> Nothing is wrong with what is already in. This is merely an addition.
Your above description of not being able to use GPIOs on e.g. the GXL
based Khadas Vim devboard sounded like a bug to me.
> If we go that way, all commit to this file should have a Fixes to the
> initial commit. This seems a bit extreme to me ...
Thought it might have been just an oversight.
Cheers,
Andreas
--
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG Nürnberg)
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] pinctrl: meson-gxl: add tsin_a pins
2017-06-08 13:58 ` Andreas Färber
@ 2017-06-08 14:05 ` Jerome Brunet
0 siblings, 0 replies; 7+ messages in thread
From: Jerome Brunet @ 2017-06-08 14:05 UTC (permalink / raw)
To: Andreas Färber
Cc: Linus Walleij, Kevin Hilman, Carlo Caione, linux-gpio,
linux-amlogic, linux-kernel
On Thu, 2017-06-08 at 15:58 +0200, Andreas Färber wrote:
> Am 08.06.2017 um 15:53 schrieb Jerome Brunet:
> > On Thu, 2017-06-08 at 15:49 +0200, Andreas Färber wrote:
> > > Am 08.06.2017 um 15:09 schrieb Jerome Brunet:
> > > > Add Tsin A pins to bank DV and X.
> > > > We don't have a driver for the tsin yet but since the tsin A pinmux is
> > > > enabled by default at boot time, declaring this pinmux is required to
> > > > properly operate on GPIOX.
> > > >
> > > > Without this change, GPIOX 8, 9, 10 and 11 can't be driven as GPIO
> > > > output
> > > > as the tsin A seems to have priority.
> > >
> > > Should this get a Fixes header then for stable backports?
> >
> > Nothing is wrong with what is already in. This is merely an addition.
>
> Your above description of not being able to use GPIOs on e.g. the GXL
> based Khadas Vim devboard sounded like a bug to me.
As far as I know, the affected pins (GPIOX 8 to 11) are used for BTPCM, not
GPIOs, on all supported designs, including the Vim.
>
> > If we go that way, all commit to this file should have a Fixes to the
> > initial commit. This seems a bit extreme to me ...
>
> Thought it might have been just an oversight.
>
> Cheers,
> Andreas
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] pinctrl: meson-gxl: add tsin_a pins
2017-06-08 13:09 [PATCH] pinctrl: meson-gxl: add tsin_a pins Jerome Brunet
2017-06-08 13:49 ` Andreas Färber
@ 2017-06-09 9:54 ` Neil Armstrong
2017-06-16 9:10 ` Linus Walleij
2 siblings, 0 replies; 7+ messages in thread
From: Neil Armstrong @ 2017-06-09 9:54 UTC (permalink / raw)
To: Jerome Brunet, Linus Walleij, Kevin Hilman
Cc: Carlo Caione, linux-gpio, linux-amlogic, linux-kernel
On 06/08/2017 03:09 PM, Jerome Brunet wrote:
> Add Tsin A pins to bank DV and X.
> We don't have a driver for the tsin yet but since the tsin A pinmux is
> enabled by default at boot time, declaring this pinmux is required to
> properly operate on GPIOX.
>
> Without this change, GPIOX 8, 9, 10 and 11 can't be driven as GPIO output
> as the tsin A seems to have priority.
>
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
> ---
> drivers/pinctrl/meson/pinctrl-meson-gxl.c | 36 +++++++++++++++++++++++++++++++
> 1 file changed, 36 insertions(+)
>
> diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxl.c b/drivers/pinctrl/meson/pinctrl-meson-gxl.c
> index 190f50c6a9ba..2624b0d4d3c4 100644
> --- a/drivers/pinctrl/meson/pinctrl-meson-gxl.c
> +++ b/drivers/pinctrl/meson/pinctrl-meson-gxl.c
> @@ -243,6 +243,25 @@ static const unsigned int spdif_out_h_pins[] = { PIN(GPIOH_4, EE_OFF) };
> static const unsigned int eth_link_led_pins[] = { PIN(GPIOZ_14, EE_OFF) };
> static const unsigned int eth_act_led_pins[] = { PIN(GPIOZ_15, EE_OFF) };
>
> +static const unsigned int tsin_a_d0_pins[] = { PIN(GPIODV_0, EE_OFF) };
> +static const unsigned int tsin_a_d0_x_pins[] = { PIN(GPIOX_10, EE_OFF) };
> +static const unsigned int tsin_a_clk_pins[] = { PIN(GPIODV_8, EE_OFF) };
> +static const unsigned int tsin_a_clk_x_pins[] = { PIN(GPIOX_11, EE_OFF) };
> +static const unsigned int tsin_a_sop_pins[] = { PIN(GPIODV_9, EE_OFF) };
> +static const unsigned int tsin_a_sop_x_pins[] = { PIN(GPIOX_8, EE_OFF) };
> +static const unsigned int tsin_a_d_valid_pins[] = { PIN(GPIODV_10, EE_OFF) };
> +static const unsigned int tsin_a_d_valid_x_pins[] = { PIN(GPIOX_9, EE_OFF) };
> +static const unsigned int tsin_a_fail_pins[] = { PIN(GPIODV_11, EE_OFF) };
> +static const unsigned int tsin_a_dp_pins[] = {
> + PIN(GPIODV_1, EE_OFF),
> + PIN(GPIODV_2, EE_OFF),
> + PIN(GPIODV_3, EE_OFF),
> + PIN(GPIODV_4, EE_OFF),
> + PIN(GPIODV_5, EE_OFF),
> + PIN(GPIODV_6, EE_OFF),
> + PIN(GPIODV_7, EE_OFF),
> +};
> +
> static const struct pinctrl_pin_desc meson_gxl_aobus_pins[] = {
> MESON_PIN(GPIOAO_0, 0),
> MESON_PIN(GPIOAO_1, 0),
> @@ -421,6 +440,10 @@ static struct meson_pmx_group meson_gxl_periphs_groups[] = {
> GROUP(spi_miso, 5, 2),
> GROUP(spi_ss0, 5, 1),
> GROUP(spi_sclk, 5, 0),
> + GROUP(tsin_a_sop_x, 6, 3),
> + GROUP(tsin_a_d_valid_x, 6, 2),
> + GROUP(tsin_a_d0_x, 6, 1),
> + GROUP(tsin_a_clk_x, 6, 0),
>
> /* Bank Z */
> GROUP(eth_mdio, 4, 23),
> @@ -469,6 +492,12 @@ static struct meson_pmx_group meson_gxl_periphs_groups[] = {
> GROUP(i2c_sck_c, 1, 10),
> GROUP(pwm_b, 2, 11),
> GROUP(pwm_d, 2, 12),
> + GROUP(tsin_a_d0, 2, 4),
> + GROUP(tsin_a_dp, 2, 3),
> + GROUP(tsin_a_clk, 2, 2),
> + GROUP(tsin_a_sop, 2, 1),
> + GROUP(tsin_a_d_valid, 2, 0),
> + GROUP(tsin_a_fail, 1, 31),
>
> /* Bank BOOT */
> GROUP(emmc_nand_d07, 7, 31),
> @@ -675,6 +704,12 @@ static const char * const eth_led_groups[] = {
> "eth_link_led", "eth_act_led",
> };
>
> +static const char * const tsin_a_groups[] = {
> + "tsin_a_clk", "tsin_a_clk_x", "tsin_a_sop", "tsin_a_sop_x",
> + "tsin_a_d_valid", "tsin_a_d_valid_x", "tsin_a_d0", "tsin_a_d0_x",
> + "tsin_a_dp", "tsin_a_fail",
> +};
> +
> static const char * const gpio_aobus_groups[] = {
> "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4",
> "GPIOAO_5", "GPIOAO_6", "GPIOAO_7", "GPIOAO_8", "GPIOAO_9",
> @@ -747,6 +782,7 @@ static struct meson_pmx_func meson_gxl_periphs_functions[] = {
> FUNCTION(i2s_out),
> FUNCTION(spdif_out),
> FUNCTION(eth_led),
> + FUNCTION(tsin_a),
> };
>
> static struct meson_pmx_func meson_gxl_aobus_functions[] = {
>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH] pinctrl: meson-gxl: add tsin_a pins
2017-06-08 13:09 [PATCH] pinctrl: meson-gxl: add tsin_a pins Jerome Brunet
2017-06-08 13:49 ` Andreas Färber
2017-06-09 9:54 ` Neil Armstrong
@ 2017-06-16 9:10 ` Linus Walleij
2 siblings, 0 replies; 7+ messages in thread
From: Linus Walleij @ 2017-06-16 9:10 UTC (permalink / raw)
To: Jerome Brunet
Cc: Kevin Hilman, Carlo Caione, linux-gpio@vger.kernel.org,
open list:ARM/Amlogic Meson..., linux-kernel@vger.kernel.org
On Thu, Jun 8, 2017 at 3:09 PM, Jerome Brunet <jbrunet@baylibre.com> wrote:
> Add Tsin A pins to bank DV and X.
> We don't have a driver for the tsin yet but since the tsin A pinmux is
> enabled by default at boot time, declaring this pinmux is required to
> properly operate on GPIOX.
>
> Without this change, GPIOX 8, 9, 10 and 11 can't be driven as GPIO output
> as the tsin A seems to have priority.
>
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Patch applied with Neil's ACK.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 7+ messages in thread
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2017-06-08 13:09 [PATCH] pinctrl: meson-gxl: add tsin_a pins Jerome Brunet
2017-06-08 13:49 ` Andreas Färber
2017-06-08 13:53 ` Jerome Brunet
2017-06-08 13:58 ` Andreas Färber
2017-06-08 14:05 ` Jerome Brunet
2017-06-09 9:54 ` Neil Armstrong
2017-06-16 9:10 ` Linus Walleij
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