From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Linus Walleij <linus.walleij@linaro.org>
Cc: Andy Gross <agross@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konrad.dybcio@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Srinivas Kandagatla <srinivas.kandagatla@linaro.org>,
linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] dt-bindings: pinctrl: qcom: lpass-lpi: correct description of second reg
Date: Tue, 7 Mar 2023 14:39:59 +0100 [thread overview]
Message-ID: <08aa9325-ed36-250c-d4d6-de6af1e82de5@linaro.org> (raw)
In-Reply-To: <CACRpkdbe=sHG9KVaGrbEaFoVbMY-2=r2X4WkcbNhCfZ9KOw1sQ@mail.gmail.com>
On 07/03/2023 14:32, Linus Walleij wrote:
> On Thu, Mar 2, 2023 at 4:52 PM Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
>
>> The description of second IO address is a bit confusing. It is supposed
>> to be the MCC range which contains the slew rate registers, not the slew
>> rate register base. The Linux driver then accesses slew rate register
>> with hard-coded offset (0xa000).
>>
>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>
> LGTM, is this something I should just apply or will you collect a larger
> series of Qcom DT patches this time around as well?
Please grab it. I think I cleaned up Qualcomm pinctrl bindings from
technical debt, thus no more work for me!
Best regards,
Krzysztof
next prev parent reply other threads:[~2023-03-07 13:40 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-02 15:52 [PATCH] dt-bindings: pinctrl: qcom: lpass-lpi: correct description of second reg Krzysztof Kozlowski
2023-03-07 13:32 ` Linus Walleij
2023-03-07 13:39 ` Krzysztof Kozlowski [this message]
2023-03-09 13:46 ` Linus Walleij
2023-03-09 16:11 ` Krzysztof Kozlowski
2023-03-08 20:33 ` Rob Herring
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