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Mon, 25 Nov 2024 19:46:12 +0100 Message-ID: <0c6fa2cc-3a7e-4db2-bbad-7c19a876937e@gmx.net> Date: Mon, 25 Nov 2024 19:46:10 +0100 Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 06/10] pinctrl: rp1: Implement RaspberryPi RP1 gpio support To: Andrea della Porta , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Broadcom internal kernel review list , Lorenzo Pieralisi , Krzysztof Wilczynski , Manivannan Sadhasivam , Bjorn Helgaas , Linus Walleij , Catalin Marinas , Will Deacon , Bartosz Golaszewski , Derek Kiernan , Dragan Cvetic , Arnd Bergmann , Greg Kroah-Hartman , Saravana Kannan , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-gpio@vger.kernel.org, Masahiro Yamada , Herve Codina , Luca Ceresoli , Thomas Petazzoni , Andrew Lunn References: <1257f76168ae03dba027bd33e6fca31b8df29c35.1732444746.git.andrea.porta@suse.com> Content-Language: en-US From: Stefan Wahren In-Reply-To: <1257f76168ae03dba027bd33e6fca31b8df29c35.1732444746.git.andrea.porta@suse.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Provags-ID: V03:K1:BPxstd5PG9ii50gxD3QFzCia8ZtZfz1FrMC9GEaSmohukVFc8pM 4pPyBwPOV1gpyguV4e7aOdGci0vuMRPoCFFJC2WjtJ5SAOdZLn3B1ru/Y0lJ9+yTQylu76E cNd94z5KkcKxxBU8JWjbgVMQDNVmNZ/pvxmKODJa+97tmp8HqcWWqqg2Vbr4gJcqwonmHx3 Wus5KRt3hTWH9+DKCYRgA== X-Spam-Flag: NO UI-OutboundReport: notjunk:1;M01:P0:TfkttF/NobQ=;RJQ4AN65XloMCZXRYId0Lyvr73F STq7YLJ96O9szCp1wZFJ6wAEVftm4lorvf5J29jJywz0XoJlQd3vu+DpEXsdfv5L8U3Jcau5m y7+81SXU61H3xi+IKKSzVx3VR5CZpAwv4vm6Dawqnb5l+XutNhhkCLj3DMIRISaSJmsfaM0hs OkX7zCbA3ftjGQ1yExO/PCnfKNNHdaWj1X7W/nV6P4kSGKyxM6ISrifJ5CNFo+veLzHbX3WMy iq3ggFg/+IDdXJhPC79ycPS06lAuznETUlU8hCUGGkxnTzQWAIaA91vr94Cp7N68oUA07isWf lWnJY0+feGQsID6+dItAG2Z/05faSirflzo/mVclsdThy//3g7iHqCS1mSiDYVNwZEOMn9w0G raiXOkVBT6V1wFa2KqydLYrn6v3Cv35EIlRp/pfLRISJd18rTWyNbmUabckxAygEXN9SDm7Qh 9iE05MqyBT0v6IBZXKKIwvGVRVPLJXjGDF5OJmhy7xq9aZ5LrbMkHimJB0WraFbUwYpClZBdx KPT3bMzcwFFRXIBDnNMjJHbnjcrDx/s1Kzs7F89BIV/29MnTL908vmRnFtXMMaGGHK4nL2UcL Bs0HihL+qt3qPQREKCVVz2BFn9+U3Ti2zBYePgOhFHBlYJ5XqNLLB0x5SiR/L46PoYYT55W4B 8SFVAJAzPvaUUWscxr6fFGrSVe49kuoeEtSUM2NOTrQZZ/ZwUiWKBL0tyuifHv5dp8TYfNNUp SrdVq5yiLr7/C7KDqGYyTgHeHXRqFzidU7szXanNfFNnsPeFDMpFHstFzxZbR/9go/tXgNB4m yU4iu1GFK0sYJifORjsDW992/kjvcNR27Hd3rxi+zsJm/CawqVzn0/0cJQ7L4dYtz8YrD08tK 3QPwR8eTcEaMfbCVTuGXAaEWtjzyBbRLLGhD/ecm0jYZx6wAy55022I/J Hi Andrea, Am 24.11.24 um 11:51 schrieb Andrea della Porta: > The RP1 is an MFD supporting a gpio controller and /pinmux/pinctrl. > Add minimum support for the gpio only portion. The driver is in > pinctrl folder since upcoming patches will add the pinmux/pinctrl > support where the gpio part can be seen as an addition. > > Signed-off-by: Andrea della Porta > Reviewed-by: Linus Walleij > --- > MAINTAINERS | 1 + > drivers/pinctrl/Kconfig | 11 + > drivers/pinctrl/Makefile | 1 + > drivers/pinctrl/pinctrl-rp1.c | 789 ++++++++++++++++++++++++++++++++++ > 4 files changed, 802 insertions(+) > create mode 100644 drivers/pinctrl/pinctrl-rp1.c ... > + > +static int rp1_pinctrl_probe(struct platform_device *pdev) > +{ > + struct regmap *gpio_regmap, *rio_regmap, *pads_regmap; > + struct rp1_pinctrl *pc = &rp1_pinctrl_data; > + struct device *dev = &pdev->dev; > + struct device_node *np = dev->of_node; > + struct gpio_irq_chip *girq; > + int err, i; > + > + pc->dev = dev; > + pc->gpio_chip = rp1_gpio_chip; > + pc->gpio_chip.parent = dev; > + > + pc->gpio_base = devm_platform_ioremap_resource(pdev, 0); > + if (IS_ERR(pc->gpio_base)) > + return dev_err_probe(dev, PTR_ERR(pc->gpio_base), "could not get GPIO IO memory\n"); > + > + pc->rio_base = devm_platform_ioremap_resource(pdev, 1); > + if (IS_ERR(pc->rio_base)) > + return dev_err_probe(dev, PTR_ERR(pc->rio_base), "could not get RIO IO memory\n"); > + > + pc->pads_base = devm_platform_ioremap_resource(pdev, 2); > + if (IS_ERR(pc->pads_base)) > + return dev_err_probe(dev, PTR_ERR(pc->pads_base), "could not get PADS IO memory\n"); > + > + gpio_regmap = devm_regmap_init_mmio(dev, pc->gpio_base, > + &rp1_pinctrl_regmap_cfg); > + if (IS_ERR(gpio_regmap)) > + return dev_err_probe(dev, PTR_ERR(gpio_regmap), "could not init GPIO regmap\n"); > + > + rio_regmap = devm_regmap_init_mmio(dev, pc->rio_base, > + &rp1_pinctrl_regmap_cfg); > + if (IS_ERR(rio_regmap)) > + return dev_err_probe(dev, PTR_ERR(rio_regmap), "could not init RIO regmap\n"); > + > + pads_regmap = devm_regmap_init_mmio(dev, pc->pads_base, > + &rp1_pinctrl_regmap_cfg); > + if (IS_ERR(pads_regmap)) > + return dev_err_probe(dev, PTR_ERR(pads_regmap), "could not init PADS regmap\n"); > + > + for (i = 0; i < RP1_NUM_BANKS; i++) { > + const struct rp1_iobank_desc *bank = &rp1_iobanks[i]; > + int j; > + > + for (j = 0; j < bank->num_gpios; j++) { > + struct rp1_pin_info *pin = > + &pc->pins[bank->min_gpio + j]; > + int reg_off; > + > + pin->num = bank->min_gpio + j; > + pin->bank = i; > + pin->offset = j; > + > + reg_off = bank->gpio_offset + pin->offset > + * sizeof(u32) * 2; Just a nit: the first * belongs in the line above Except of this: Reviewed-by: Stefan Wahren