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From: Andrew Jeffery <andrew@codeconstruct.com.au>
To: Nikita Shubin <nikita.shubin@maquefel.me>, Joel Stanley <joel@jms.id.au>
Cc: linux-gpio@vger.kernel.org
Subject: Re: Question about ASPEED GPIO value/direction set order
Date: Tue, 18 Mar 2025 11:18:12 +1030	[thread overview]
Message-ID: <0d0c60dcd2eae1d8bc6113a4678f5e362c3244fd.camel@codeconstruct.com.au> (raw)
In-Reply-To: <5372f57d61f31ac681e295964cacf2e23df3b3ed.camel@maquefel.me>

Hi Nikita,

On Thu, 2025-03-13 at 10:39 +0300, Nikita Shubin wrote:
> Hi Andrew, thank you for quick answer.
> 
> The reason i am asking this is that in QEMU the first time we set
> pin,
> all below if (diff) in aspeed_gpio_update() won't be triggered due to
> direction is set after the value itself (so no qemu_set_irq()
> triggers):
> 
> https://elixir.bootlin.com/qemu/v9.2.2/source/hw/gpio/aspeed_gpio.c#L314
> 
> aspeed # gpioset 0 8=1
> aspeed_gpio_write offset: 0x1c value 0x100
> aspeed_gpio_write offset: 0x0 value 0x100       <-- VALUE
> aspeed_gpio_write offset: 0x4 value 0x100       <-- DIRECTION
> 
> And i doubted if it's a QEMU or Linux driver flaw.

That sounds like a bug in the qemu model. Please send a patch to the
qemu lists for discussion.

Thanks,

Andrew

      reply	other threads:[~2025-03-18  0:48 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-11 12:40 Question about ASPEED GPIO value/direction set order Nikita Shubin
2025-03-13  6:21 ` Andrew Jeffery
2025-03-13  7:39   ` Nikita Shubin
2025-03-18  0:48     ` Andrew Jeffery [this message]

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