[PATCH v2 0/8] pinctrl: ocelot: convert to YAML format

[PATCH v2 0/8] pinctrl: ocelot: convert to YAML format

[Michael Walle]

Convert the pinctrl ocelot binding to the new YAML format. Pin
configuration nodes should have a "-pins" postfix. But unfortunately,
there are many device trees which don't follow this. First rename
all these nodes and then convert the binding to the YAML format so
that the validation will pass.

Because there were no maintainers before and there is none in
MAINTAINERS I added Alexandre Belloni and Lars Povlsen, juding by
the commits - to the binding as maintainers. Please tell me if you
disagree.

changes since v1:
 - drop "Device Tree Binding" from the title of the binding
 - describe reg properties and provide minItems and set it differently
   depending on the compatible string
 - skip interrupt description
 - move required section after patternProperties

Michael Walle (8):
  MIPS: mscc: jaguar2: fix pinctrl nodes
  MIPS: mscc: ocelot: fix MIIM1 pinctrl node name
  MIPS: mscc: ocelot: fix PHY interrupt pinctrl node name
  MIPS: mscc: ocelot: fix load/save GPIO pinctrl name
  MIPS: mscc: serval: fix pinctrl node names
  arm64: dts: sparx5: fix pinctrl node names
  ARM: dts: lan9662-pcb8291: fix pinctrl node name
  dt-bindings: pinctrl: convert ocelot-pinctrl to YAML format

 .../bindings/pinctrl/mscc,ocelot-pinctrl.txt  |  42 -------
 .../bindings/pinctrl/mscc,ocelot-pinctrl.yaml | 108 ++++++++++++++++++
 arch/arm/boot/dts/lan966x-pcb8291.dts         |   2 +-
 .../dts/microchip/sparx5_pcb134_board.dtsi    |  26 ++---
 .../dts/microchip/sparx5_pcb135_board.dtsi    |  10 +-
 arch/mips/boot/dts/mscc/jaguar2_pcb110.dts    |  10 +-
 arch/mips/boot/dts/mscc/jaguar2_pcb111.dts    |  10 +-
 arch/mips/boot/dts/mscc/jaguar2_pcb118.dts    |   6 +-
 arch/mips/boot/dts/mscc/ocelot.dtsi           |   4 +-
 arch/mips/boot/dts/mscc/ocelot_pcb120.dts     |   6 +-
 arch/mips/boot/dts/mscc/serval_common.dtsi    |  14 +--
 11 files changed, 152 insertions(+), 86 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml

-- 
2.30.2

[PATCH v2 1/8] MIPS: mscc: jaguar2: fix pinctrl nodes

[Michael Walle]

The pinctrl device tree binding will be converted to YAML format. All
the pin nodes should end with "-pins". Fix them.

Fixes: f84778f7d8c3 ("MIPS: mscc: Add jaguar2 support")
Signed-off-by: Michael Walle <michael@walle.cc>
---
 arch/mips/boot/dts/mscc/jaguar2_pcb110.dts | 10 +++++-----
 arch/mips/boot/dts/mscc/jaguar2_pcb111.dts | 10 +++++-----
 arch/mips/boot/dts/mscc/jaguar2_pcb118.dts |  6 +++---
 3 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/arch/mips/boot/dts/mscc/jaguar2_pcb110.dts b/arch/mips/boot/dts/mscc/jaguar2_pcb110.dts
index d80cd6842b2a..0ea7bc5b5746 100644
--- a/arch/mips/boot/dts/mscc/jaguar2_pcb110.dts
+++ b/arch/mips/boot/dts/mscc/jaguar2_pcb110.dts
@@ -180,27 +180,27 @@ synce_builtin_pins: synce-builtin-pins {
 		pins = "GPIO_49";
 		function = "si";
 	};
-	i2cmux_pins_i: i2cmux-pins-i {
+	i2cmux_pins_i: i2cmux-pins {
 		pins = "GPIO_17", "GPIO_18", "GPIO_20", "GPIO_21";
 		function = "twi_scl_m";
 		output-low;
 	};
-	i2cmux_0: i2cmux-0 {
+	i2cmux_0: i2cmux-0-pins {
 		pins = "GPIO_17";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_1: i2cmux-1 {
+	i2cmux_1: i2cmux-1-pins {
 		pins = "GPIO_18";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_2: i2cmux-2 {
+	i2cmux_2: i2cmux-2-pins {
 		pins = "GPIO_20";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_3: i2cmux-3 {
+	i2cmux_3: i2cmux-3-pins {
 		pins = "GPIO_21";
 		function = "twi_scl_m";
 		output-high;
diff --git a/arch/mips/boot/dts/mscc/jaguar2_pcb111.dts b/arch/mips/boot/dts/mscc/jaguar2_pcb111.dts
index 813c5e16013c..05d8c6a96dc4 100644
--- a/arch/mips/boot/dts/mscc/jaguar2_pcb111.dts
+++ b/arch/mips/boot/dts/mscc/jaguar2_pcb111.dts
@@ -79,27 +79,27 @@ cpld_fifo_pins: synce-builtin-pins {
 };
 
 &gpio {
-	i2cmux_pins_i: i2cmux-pins-i {
+	i2cmux_pins_i: i2cmux-pins {
 		pins = "GPIO_17", "GPIO_18";
 		function = "twi_scl_m";
 		output-low;
 	};
-	i2cmux_0: i2cmux-0 {
+	i2cmux_0: i2cmux-0-pins {
 		pins = "GPIO_17";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_1: i2cmux-1 {
+	i2cmux_1: i2cmux-1-pins {
 		pins = "GPIO_18";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_2: i2cmux-2 {
+	i2cmux_2: i2cmux-2-pins {
 		pins = "GPIO_20";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_3: i2cmux-3 {
+	i2cmux_3: i2cmux-3-pins {
 		pins = "GPIO_21";
 		function = "twi_scl_m";
 		output-high;
diff --git a/arch/mips/boot/dts/mscc/jaguar2_pcb118.dts b/arch/mips/boot/dts/mscc/jaguar2_pcb118.dts
index 27c644f2d17f..cf2cf591a211 100644
--- a/arch/mips/boot/dts/mscc/jaguar2_pcb118.dts
+++ b/arch/mips/boot/dts/mscc/jaguar2_pcb118.dts
@@ -39,17 +39,17 @@ i2c151: i2c@1 {
 };
 
 &gpio {
-	i2cmux_pins_i: i2cmux-pins-i {
+	i2cmux_pins_i: i2cmux-pins {
 		pins = "GPIO_17", "GPIO_16";
 		function = "twi_scl_m";
 		output-low;
 	};
-	i2cmux_0: i2cmux-0 {
+	i2cmux_0: i2cmux-0-pins {
 		pins = "GPIO_17";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_1: i2cmux-1 {
+	i2cmux_1: i2cmux-1-pins {
 		pins = "GPIO_16";
 		function = "twi_scl_m";
 		output-high;
-- 
2.30.2

[PATCH v2 2/8] MIPS: mscc: ocelot: fix MIIM1 pinctrl node name

[Michael Walle]

The pinctrl device tree binding will be converted to YAML format. All
the pin nodes should end with "-pins". Fix them.

Fixes: a0553e01f85b ("MIPS: mscc: ocelot: add MIIM1 bus")
Signed-off-by: Michael Walle <michael@walle.cc>
---
 arch/mips/boot/dts/mscc/ocelot.dtsi       | 4 ++--
 arch/mips/boot/dts/mscc/ocelot_pcb120.dts | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi b/arch/mips/boot/dts/mscc/ocelot.dtsi
index e51db651af13..cfc219a72bdd 100644
--- a/arch/mips/boot/dts/mscc/ocelot.dtsi
+++ b/arch/mips/boot/dts/mscc/ocelot.dtsi
@@ -225,7 +225,7 @@ uart2_pins: uart2-pins {
 				function = "uart2";
 			};
 
-			miim1: miim1 {
+			miim1_pins: miim1-pins {
 				pins = "GPIO_14", "GPIO_15";
 				function = "miim";
 			};
@@ -261,7 +261,7 @@ mdio1: mdio@10700c0 {
 			reg = <0x10700c0 0x24>;
 			interrupts = <15>;
 			pinctrl-names = "default";
-			pinctrl-0 = <&miim1>;
+			pinctrl-0 = <&miim1_pins>;
 			status = "disabled";
 		};
 
diff --git a/arch/mips/boot/dts/mscc/ocelot_pcb120.dts b/arch/mips/boot/dts/mscc/ocelot_pcb120.dts
index bd240690cb37..9d6b5717befb 100644
--- a/arch/mips/boot/dts/mscc/ocelot_pcb120.dts
+++ b/arch/mips/boot/dts/mscc/ocelot_pcb120.dts
@@ -40,7 +40,7 @@ &mdio0 {
 &mdio1 {
 	status = "okay";
 	pinctrl-names = "default";
-	pinctrl-0 = <&miim1>, <&phy_int_pins>, <&phy_load_save_pins>;
+	pinctrl-0 = <&miim1_pins>, <&phy_int_pins>, <&phy_load_save_pins>;
 
 	phy7: ethernet-phy@0 {
 		reg = <0>;
-- 
2.30.2

[PATCH v2 3/8] MIPS: mscc: ocelot: fix PHY interrupt pinctrl node name

[Michael Walle]

The pinctrl device tree binding will be converted to YAML format. All
the pin nodes should end with "-pins". Fix them.

Fixes: 116edf6e5239 ("MIPS: mscc: add DT for Ocelot PCB120")
Signed-off-by: Michael Walle <michael@walle.cc>
---
 arch/mips/boot/dts/mscc/ocelot_pcb120.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/mips/boot/dts/mscc/ocelot_pcb120.dts b/arch/mips/boot/dts/mscc/ocelot_pcb120.dts
index 9d6b5717befb..cda6c5ff58ad 100644
--- a/arch/mips/boot/dts/mscc/ocelot_pcb120.dts
+++ b/arch/mips/boot/dts/mscc/ocelot_pcb120.dts
@@ -22,7 +22,7 @@ memory@0 {
 };
 
 &gpio {
-	phy_int_pins: phy_int_pins {
+	phy_int_pins: phy-int-pins {
 		pins = "GPIO_4";
 		function = "gpio";
 	};
-- 
2.30.2

[PATCH v2 4/8] MIPS: mscc: ocelot: fix load/save GPIO pinctrl name

[Michael Walle]

The pinctrl device tree binding will be converted to YAML format. All
the pin nodes should end with "-pins". Fix them.

Fixes: 15324652f612 ("MIPS: dts: ocelot: describe the load/save GPIO")
Signed-off-by: Michael Walle <michael@walle.cc>
---
 arch/mips/boot/dts/mscc/ocelot_pcb120.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/mips/boot/dts/mscc/ocelot_pcb120.dts b/arch/mips/boot/dts/mscc/ocelot_pcb120.dts
index cda6c5ff58ad..d348742c233d 100644
--- a/arch/mips/boot/dts/mscc/ocelot_pcb120.dts
+++ b/arch/mips/boot/dts/mscc/ocelot_pcb120.dts
@@ -27,7 +27,7 @@ phy_int_pins: phy-int-pins {
 		function = "gpio";
 	};
 
-	phy_load_save_pins: phy_load_save_pins {
+	phy_load_save_pins: phy-load-save-pins {
 		pins = "GPIO_10";
 		function = "ptp2";
 	};
-- 
2.30.2

Re: [PATCH v2 4/8] MIPS: mscc: ocelot: fix load/save GPIO pinctrl name

[Krzysztof Kozlowski]

On 18/03/2022 21:25, Michael Walle wrote:
> The pinctrl device tree binding will be converted to YAML format. All
> the pin nodes should end with "-pins". Fix them.
> 
> Fixes: 15324652f612 ("MIPS: dts: ocelot: describe the load/save GPIO")

There is no bug here, so no need for fix.

> Signed-off-by: Michael Walle <michael@walle.cc>
> ---
>  arch/mips/boot/dts/mscc/ocelot_pcb120.dts | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/mips/boot/dts/mscc/ocelot_pcb120.dts b/arch/mips/boot/dts/mscc/ocelot_pcb120.dts
> index cda6c5ff58ad..d348742c233d 100644
> --- a/arch/mips/boot/dts/mscc/ocelot_pcb120.dts
> +++ b/arch/mips/boot/dts/mscc/ocelot_pcb120.dts
> @@ -27,7 +27,7 @@ phy_int_pins: phy-int-pins {
>  		function = "gpio";
>  	};
>  
> -	phy_load_save_pins: phy_load_save_pins {
> +	phy_load_save_pins: phy-load-save-pins {
>  		pins = "GPIO_10";

This should be squashed with previous patch or with the next one. There
is no point to align names with dtschema/dt spec one by one. Make the
conversion per entire board file or SoC.


Best regards,
Krzysztof

[PATCH v2 5/8] MIPS: mscc: serval: fix pinctrl node names

[Michael Walle]

The pinctrl device tree binding will be converted to YAML format. All
the pin nodes should end with "-pins". Fix them.

Fixes: fe0052018a84 ("MIPS: mscc: Add serval support")
Signed-off-by: Michael Walle <michael@walle.cc>
---
 arch/mips/boot/dts/mscc/serval_common.dtsi | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/mips/boot/dts/mscc/serval_common.dtsi b/arch/mips/boot/dts/mscc/serval_common.dtsi
index 5b404836db5e..0893de420e27 100644
--- a/arch/mips/boot/dts/mscc/serval_common.dtsi
+++ b/arch/mips/boot/dts/mscc/serval_common.dtsi
@@ -82,38 +82,38 @@ i2c_pins: i2c-pins {
 		pins = "GPIO_7"; /* No "default" scl for i2c0 */
 		function = "twi";
 	};
-	i2cmux_pins_i: i2cmux-pins-i {
+	i2cmux_pins_i: i2cmux-pins {
 		pins = "GPIO_11", "GPIO_12", "GPIO_18", "GPIO_19",
 			"GPIO_20", "GPIO_21";
 		function = "twi_scl_m";
 		output-low;
 	};
-	i2cmux_0: i2cmux-0 {
+	i2cmux_0: i2cmux-0-pins {
 		pins = "GPIO_11";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_1: i2cmux-1 {
+	i2cmux_1: i2cmux-1-pins {
 		pins = "GPIO_12";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_2: i2cmux-2 {
+	i2cmux_2: i2cmux-2-pins {
 		pins = "GPIO_18";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_3: i2cmux-3 {
+	i2cmux_3: i2cmux-3-pins {
 		pins = "GPIO_19";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_4: i2cmux-4 {
+	i2cmux_4: i2cmux-4-pins {
 		pins = "GPIO_20";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_5: i2cmux-5 {
+	i2cmux_5: i2cmux-5-pins {
 		pins = "GPIO_21";
 		function = "twi_scl_m";
 		output-high;
-- 
2.30.2

[PATCH v2 6/8] arm64: dts: sparx5: fix pinctrl node names

[Michael Walle]

The pinctrl device tree binding will be converted to YAML format. All
the pin nodes should end with "-pins". Fix them.

Fixes: ("arm64: dts: sparx5: Add i2c devices, i2c muxes")
Signed-off-by: Michael Walle <michael@walle.cc>
---
 .../dts/microchip/sparx5_pcb134_board.dtsi    | 26 +++++++++----------
 .../dts/microchip/sparx5_pcb135_board.dtsi    | 10 +++----
 2 files changed, 18 insertions(+), 18 deletions(-)

diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
index 33faf1f3264f..6f488e774215 100644
--- a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
@@ -325,69 +325,69 @@ &sgpio2 {
 };
 
 &gpio {
-	i2cmux_pins_i: i2cmux-pins-i {
+	i2cmux_pins_i: i2cmux-pins {
 	       pins = "GPIO_16", "GPIO_17", "GPIO_18", "GPIO_19",
 		      "GPIO_20", "GPIO_22", "GPIO_36", "GPIO_35",
 		      "GPIO_50", "GPIO_51", "GPIO_56", "GPIO_57";
 		function = "twi_scl_m";
 		output-low;
 	};
-	i2cmux_0: i2cmux-0 {
+	i2cmux_0: i2cmux-0-pins {
 		pins = "GPIO_16";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_1: i2cmux-1 {
+	i2cmux_1: i2cmux-1-pins {
 		pins = "GPIO_17";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_2: i2cmux-2 {
+	i2cmux_2: i2cmux-2-pins {
 		pins = "GPIO_18";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_3: i2cmux-3 {
+	i2cmux_3: i2cmux-3-pins {
 		pins = "GPIO_19";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_4: i2cmux-4 {
+	i2cmux_4: i2cmux-4-pins {
 		pins = "GPIO_20";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_5: i2cmux-5 {
+	i2cmux_5: i2cmux-5-pins {
 		pins = "GPIO_22";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_6: i2cmux-6 {
+	i2cmux_6: i2cmux-6-pins {
 		pins = "GPIO_36";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_7: i2cmux-7 {
+	i2cmux_7: i2cmux-7-pins {
 		pins = "GPIO_35";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_8: i2cmux-8 {
+	i2cmux_8: i2cmux-8-pins {
 		pins = "GPIO_50";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_9: i2cmux-9 {
+	i2cmux_9: i2cmux-9-pins {
 		pins = "GPIO_51";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_10: i2cmux-10 {
+	i2cmux_10: i2cmux-10-pins {
 		pins = "GPIO_56";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_11: i2cmux-11 {
+	i2cmux_11: i2cmux-11-pins {
 		pins = "GPIO_57";
 		function = "twi_scl_m";
 		output-high;
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi
index ef96e6d8c6b3..d9e519bfbf68 100644
--- a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi
@@ -59,28 +59,28 @@ led@7 {
 };
 
 &gpio {
-	i2cmux_pins_i: i2cmux-pins-i {
+	i2cmux_pins_i: i2cmux-pins {
 	       pins = "GPIO_35", "GPIO_36",
 		      "GPIO_50", "GPIO_51";
 		function = "twi_scl_m";
 		output-low;
 	};
-	i2cmux_s29: i2cmux-0 {
+	i2cmux_s29: i2cmux-0-pins {
 		pins = "GPIO_35";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_s30: i2cmux-1 {
+	i2cmux_s30: i2cmux-1-pins {
 		pins = "GPIO_36";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_s31: i2cmux-2 {
+	i2cmux_s31: i2cmux-2-pins {
 		pins = "GPIO_50";
 		function = "twi_scl_m";
 		output-high;
 	};
-	i2cmux_s32: i2cmux-3 {
+	i2cmux_s32: i2cmux-3-pins {
 		pins = "GPIO_51";
 		function = "twi_scl_m";
 		output-high;
-- 
2.30.2

Re: [PATCH v2 6/8] arm64: dts: sparx5: fix pinctrl node names

[Krzysztof Kozlowski]

On 18/03/2022 21:25, Michael Walle wrote:
> The pinctrl device tree binding will be converted to YAML format. All
> the pin nodes should end with "-pins". Fix them.
> 
> Fixes: ("arm64: dts: sparx5: Add i2c devices, i2c muxes")

Here and in all commits, there is no bug to be fixed. Please remove
"Fixes" and remove "fix" word from commit msg and commit subject,
because you trick stable-AUTOSEL to pick up this patch to stables. This
must not go to stables as you can break out of tree usages.

There is no bug and there is no fix.

Best regards,
Krzysztof

[PATCH v2 7/8] ARM: dts: lan9662-pcb8291: fix pinctrl node name

[Michael Walle]

The pinctrl device tree binding will be converted to YAML format. All
the pin nodes should end with "-pins". Fix them.

Fixes: 290deaa10c50 ("ARM: dts: add DT for lan966 SoC and 2-port board pcb8291")
Signed-off-by: Michael Walle <michael@walle.cc>
---
 arch/arm/boot/dts/lan966x-pcb8291.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/lan966x-pcb8291.dts b/arch/arm/boot/dts/lan966x-pcb8291.dts
index 3281af90ac6d..3c7e3a7d6f14 100644
--- a/arch/arm/boot/dts/lan966x-pcb8291.dts
+++ b/arch/arm/boot/dts/lan966x-pcb8291.dts
@@ -35,7 +35,7 @@ fc3_b_pins: fcb3-spi-pins {
 		function = "fc3_b";
 	};
 
-	can0_b_pins:  can0_b_pins {
+	can0_b_pins:  can0-b-pins {
 		/* RX, TX */
 		pins = "GPIO_35", "GPIO_36";
 		function = "can0_b";
-- 
2.30.2

Re: [PATCH v2 7/8] ARM: dts: lan9662-pcb8291: fix pinctrl node name

[Sergei Shtylyov]

Hello!

On 3/18/22 11:25 PM, Michael Walle wrote:

> The pinctrl device tree binding will be converted to YAML format. All
> the pin nodes should end with "-pins". Fix them.

   It does end with "pins" already, right?

> Fixes: 290deaa10c50 ("ARM: dts: add DT for lan966 SoC and 2-port board pcb8291")
> Signed-off-by: Michael Walle <michael@walle.cc>
> ---
>  arch/arm/boot/dts/lan966x-pcb8291.dts | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/lan966x-pcb8291.dts b/arch/arm/boot/dts/lan966x-pcb8291.dts
> index 3281af90ac6d..3c7e3a7d6f14 100644
> --- a/arch/arm/boot/dts/lan966x-pcb8291.dts
> +++ b/arch/arm/boot/dts/lan966x-pcb8291.dts
> @@ -35,7 +35,7 @@ fc3_b_pins: fcb3-spi-pins {
>  		function = "fc3_b";
>  	};
>  
> -	can0_b_pins:  can0_b_pins {
> +	can0_b_pins:  can0-b-pins {

   Mhm, I can't even see what is changed here... :-/

[...]

MBR, Sergey

Re: [PATCH v2 7/8] ARM: dts: lan9662-pcb8291: fix pinctrl node name

[Michael Walle]

Hi,

Am 2022-03-19 09:24, schrieb Sergei Shtylyov:
> Hello!
> 
> On 3/18/22 11:25 PM, Michael Walle wrote:
> 
>> The pinctrl device tree binding will be converted to YAML format. All
>> the pin nodes should end with "-pins". Fix them.
> 
>    It does end with "pins" already, right?

It ends with "_pins". Please note the underscore.

>> Fixes: 290deaa10c50 ("ARM: dts: add DT for lan966 SoC and 2-port board 
>> pcb8291")
>> Signed-off-by: Michael Walle <michael@walle.cc>
>> ---
>>  arch/arm/boot/dts/lan966x-pcb8291.dts | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>> 
>> diff --git a/arch/arm/boot/dts/lan966x-pcb8291.dts 
>> b/arch/arm/boot/dts/lan966x-pcb8291.dts
>> index 3281af90ac6d..3c7e3a7d6f14 100644
>> --- a/arch/arm/boot/dts/lan966x-pcb8291.dts
>> +++ b/arch/arm/boot/dts/lan966x-pcb8291.dts
>> @@ -35,7 +35,7 @@ fc3_b_pins: fcb3-spi-pins {
>>  		function = "fc3_b";
>>  	};
>> 
>> -	can0_b_pins:  can0_b_pins {
>> +	can0_b_pins:  can0-b-pins {
> 
>    Mhm, I can't even see what is changed here... :-/

The name of the node, s/_/-/

-michael

Re: [PATCH v2 7/8] ARM: dts: lan9662-pcb8291: fix pinctrl node name

[Sergei Shtylyov]

On 3/19/22 2:38 PM, Michael Walle wrote:

[...]
>>> The pinctrl device tree binding will be converted to YAML format. All
>>> the pin nodes should end with "-pins". Fix them.
>>
>>    It does end with "pins" already, right?
> 
> It ends with "_pins". Please note the underscore.

   Ah!

>>> Fixes: 290deaa10c50 ("ARM: dts: add DT for lan966 SoC and 2-port board pcb8291")
>>> Signed-off-by: Michael Walle <michael@walle.cc>
>>> ---
>>>  arch/arm/boot/dts/lan966x-pcb8291.dts | 2 +-
>>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm/boot/dts/lan966x-pcb8291.dts b/arch/arm/boot/dts/lan966x-pcb8291.dts
>>> index 3281af90ac6d..3c7e3a7d6f14 100644
>>> --- a/arch/arm/boot/dts/lan966x-pcb8291.dts
>>> +++ b/arch/arm/boot/dts/lan966x-pcb8291.dts
>>> @@ -35,7 +35,7 @@ fc3_b_pins: fcb3-spi-pins {
>>>          function = "fc3_b";
>>>      };
>>>
>>> -    can0_b_pins:  can0_b_pins {
>>> +    can0_b_pins:  can0-b-pins {
>>
>>    Mhm, I can't even see what is changed here... :-/
> 
> The name of the node, s/_/-/

   Indeed! I must have been blind then, sorry. :-)

> -michael

MBR, Sergey

[PATCH v2 8/8] dt-bindings: pinctrl: convert ocelot-pinctrl to YAML format

[Michael Walle]

Convert the ocelot-pinctrl device tree binding to the new YAML format.

Signed-off-by: Michael Walle <michael@walle.cc>
---
 .../bindings/pinctrl/mscc,ocelot-pinctrl.txt  |  42 -------
 .../bindings/pinctrl/mscc,ocelot-pinctrl.yaml | 108 ++++++++++++++++++
 2 files changed, 108 insertions(+), 42 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml

diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt
deleted file mode 100644
index 5d84fd299ccf..000000000000
--- a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt
+++ /dev/null
@@ -1,42 +0,0 @@
-Microsemi Ocelot pin controller Device Tree Bindings
-----------------------------------------------------
-
-Required properties:
- - compatible		: Should be "mscc,ocelot-pinctrl",
-			  "mscc,jaguar2-pinctrl", "microchip,sparx5-pinctrl",
-			  "mscc,luton-pinctrl", "mscc,serval-pinctrl",
-			  "microchip,lan966x-pinctrl" or "mscc,servalt-pinctrl"
- - reg			: Address and length of the register set for the device
- - gpio-controller	: Indicates this device is a GPIO controller
- - #gpio-cells		: Must be 2.
-			  The first cell is the pin number and the
-			  second cell specifies GPIO flags, as defined in
-			  <dt-bindings/gpio/gpio.h>.
- - gpio-ranges		: Range of pins managed by the GPIO controller.
-
-
-The ocelot-pinctrl driver uses the generic pin multiplexing and generic pin
-configuration documented in pinctrl-bindings.txt.
-
-The following generic properties are supported:
- - function
- - pins
-
-Example:
-	gpio: pinctrl@71070034 {
-		compatible = "mscc,ocelot-pinctrl";
-		reg = <0x71070034 0x28>;
-		gpio-controller;
-		#gpio-cells = <2>;
-		gpio-ranges = <&gpio 0 0 22>;
-
-		uart_pins: uart-pins {
-				pins = "GPIO_6", "GPIO_7";
-				function = "uart";
-		};
-
-		uart2_pins: uart2-pins {
-				pins = "GPIO_12", "GPIO_13";
-				function = "uart2";
-		};
-	};
diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml
new file mode 100644
index 000000000000..7149a6655623
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml
@@ -0,0 +1,108 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/mscc,ocelot-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microsemi Ocelot pin controller
+
+maintainers:
+  - Alexandre Belloni <alexandre.belloni@bootlin.com>
+  - Lars Povlsen <lars.povlsen@microchip.com>
+
+properties:
+  compatible:
+    enum:
+      - microchip,lan966x-pinctrl
+      - microchip,sparx5-pinctrl
+      - mscc,jaguar2-pinctrl
+      - mscc,luton-pinctrl
+      - mscc,ocelot-pinctrl
+      - mscc,serval-pinctrl
+      - mscc,servalt-pinctrl
+
+  reg:
+    items:
+      - description: Base address
+      - description: Extended pin configuration registers
+    minItems: 1
+
+  gpio-controller: true
+
+  '#gpio-cells':
+    const: 2
+
+  gpio-ranges: true
+
+  interrupts:
+    maxItems: 1
+
+  interrupt-controller: true
+
+  "#interrupt-cells":
+    const: 2
+
+patternProperties:
+  '-pins$':
+    type: object
+    allOf:
+      - $ref: "pinmux-node.yaml"
+      - $ref: "pincfg-node.yaml"
+
+    properties:
+      function: true
+      pins: true
+      output-high: true
+      output-low: true
+      drive-strength: true
+
+    required:
+      - function
+      - pins
+
+    additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - gpio-controller
+  - '#gpio-cells'
+  - gpio-ranges
+
+allOf:
+  - $ref: "pinctrl.yaml#"
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - microchip,lan966x-pinctrl
+              - microchip,sparx5-pinctrl
+    then:
+      properties:
+        reg:
+          minItems: 2
+
+additionalProperties: false
+
+examples:
+  - |
+    gpio: pinctrl@71070034 {
+        compatible = "mscc,ocelot-pinctrl";
+        reg = <0x71070034 0x28>;
+        gpio-controller;
+        #gpio-cells = <2>;
+        gpio-ranges = <&gpio 0 0 22>;
+
+        uart_pins: uart-pins {
+            pins = "GPIO_6", "GPIO_7";
+            function = "uart";
+        };
+
+        uart2_pins: uart2-pins {
+            pins = "GPIO_12", "GPIO_13";
+            function = "uart2";
+        };
+    };
+
+...
-- 
2.30.2

Re: [PATCH v2 8/8] dt-bindings: pinctrl: convert ocelot-pinctrl to YAML format

[Krzysztof Kozlowski]

On 18/03/2022 21:25, Michael Walle wrote:
> Convert the ocelot-pinctrl device tree binding to the new YAML format.
> 
> Signed-off-by: Michael Walle <michael@walle.cc>
> ---
>  .../bindings/pinctrl/mscc,ocelot-pinctrl.txt  |  42 -------
>  .../bindings/pinctrl/mscc,ocelot-pinctrl.yaml | 108 ++++++++++++++++++
>  2 files changed, 108 insertions(+), 42 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt
>  create mode 100644 Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml
> 
> diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt
> deleted file mode 100644
> index 5d84fd299ccf..000000000000
> --- a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt
> +++ /dev/null
> @@ -1,42 +0,0 @@
> -Microsemi Ocelot pin controller Device Tree Bindings
> -----------------------------------------------------
> -
> -Required properties:
> - - compatible		: Should be "mscc,ocelot-pinctrl",
> -			  "mscc,jaguar2-pinctrl", "microchip,sparx5-pinctrl",
> -			  "mscc,luton-pinctrl", "mscc,serval-pinctrl",
> -			  "microchip,lan966x-pinctrl" or "mscc,servalt-pinctrl"
> - - reg			: Address and length of the register set for the device
> - - gpio-controller	: Indicates this device is a GPIO controller
> - - #gpio-cells		: Must be 2.
> -			  The first cell is the pin number and the
> -			  second cell specifies GPIO flags, as defined in
> -			  <dt-bindings/gpio/gpio.h>.
> - - gpio-ranges		: Range of pins managed by the GPIO controller.
> -
> -
> -The ocelot-pinctrl driver uses the generic pin multiplexing and generic pin
> -configuration documented in pinctrl-bindings.txt.
> -
> -The following generic properties are supported:
> - - function
> - - pins
> -
> -Example:
> -	gpio: pinctrl@71070034 {
> -		compatible = "mscc,ocelot-pinctrl";
> -		reg = <0x71070034 0x28>;
> -		gpio-controller;
> -		#gpio-cells = <2>;
> -		gpio-ranges = <&gpio 0 0 22>;
> -
> -		uart_pins: uart-pins {
> -				pins = "GPIO_6", "GPIO_7";
> -				function = "uart";
> -		};
> -
> -		uart2_pins: uart2-pins {
> -				pins = "GPIO_12", "GPIO_13";
> -				function = "uart2";
> -		};
> -	};
> diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml
> new file mode 100644
> index 000000000000..7149a6655623
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.yaml
> @@ -0,0 +1,108 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/mscc,ocelot-pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Microsemi Ocelot pin controller
> +
> +maintainers:
> +  - Alexandre Belloni <alexandre.belloni@bootlin.com>
> +  - Lars Povlsen <lars.povlsen@microchip.com>
> +
> +properties:
> +  compatible:
> +    enum:
> +      - microchip,lan966x-pinctrl
> +      - microchip,sparx5-pinctrl
> +      - mscc,jaguar2-pinctrl
> +      - mscc,luton-pinctrl
> +      - mscc,ocelot-pinctrl
> +      - mscc,serval-pinctrl
> +      - mscc,servalt-pinctrl
> +
> +  reg:
> +    items:
> +      - description: Base address
> +      - description: Extended pin configuration registers
> +    minItems: 1
> +
> +  gpio-controller: true
> +
> +  '#gpio-cells':
> +    const: 2
> +
> +  gpio-ranges: true
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  interrupt-controller: true

These three interrupt related properties were not in original bindings.
Is this something new or was actually before, just not documented? In
any case mention it in commit msg.


Best regards,
Krzysztof