From: Krzysztof Kozlowski <krzk@kernel.org>
To: Christophe Leroy <christophe.leroy@csgroup.eu>,
Qiang Zhao <qiang.zhao@nxp.com>,
Linus Walleij <linus.walleij@linaro.org>,
Bartosz Golaszewski <brgl@bgdev.pl>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org,
linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org,
devicetree@vger.kernel.org
Subject: Re: [PATCH 4/4] dt-bindings: soc: fsl: qe: Add an interrupt controller for QUICC Engine Ports
Date: Tue, 12 Aug 2025 17:23:52 +0200 [thread overview]
Message-ID: <0fd6fefc-9fad-4ea6-a619-e9f480747ac0@kernel.org> (raw)
In-Reply-To: <0b56ef403a7c8d0f8305e847d68959a1037d365e.1754996033.git.christophe.leroy@csgroup.eu>
On 12/08/2025 13:02, Christophe Leroy wrote:
> The QUICC Engine provides interrupts for a few I/O ports. This is
> handled via a separate interrupt ID and managed via a triplet of
> dedicated registers hosted by the SoC.
>
> Implement an interrupt driver for it for that those IRQs can then
> be linked to the related GPIOs.
>
> Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
> ---
> .../soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml | 63 +++++++++++++++++++
> 1 file changed, 63 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml
>
> diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml
> new file mode 100644
> index 0000000000000..7c98706d03dd1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml
> @@ -0,0 +1,63 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +
> +title: Freescale QUICC Engine I/O Ports Interrupt Controller
> +
> +maintainers:
> + - name: Christophe Leroy
> + email: christophe.leroy@csgroup.eu
Oh no...
> +
> +description: |
> + Interrupt controller for the QUICC Engine I/O ports found on some
> + Freescale/NXP PowerQUICC and QorIQ SoCs.
> +
> +properties:
> + compatible:
> + enum:
> + - fsl,mpc8323-qe-ports-ic
> + - fsl,mpc8360-qe-ports-ic
> + - fsl,mpc8568-qe-ports-ic
> +
> + reg:
> + description: Base address and size of the QE I/O Ports Interrupt Controller registers.
> + minItems: 1
> + maxItems: 1
This was never tested but more important this and everything further
looks like generated by AI. Please don't do that or at least mark it
clearly, so I will prioritize accordingly (hint: AI generates poor code
and burden to decipher AI slop should not be on open source reviewers
but on users of AI, but as one of maintainers probably you already know
that, so sorry for lecturing).
Best regards,
Krzysztof
next prev parent reply other threads:[~2025-08-12 15:23 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-12 11:02 [PATCH 0/4] Add support of IRQs to QUICC ENGINE GPIOs Christophe Leroy
2025-08-12 11:02 ` [PATCH 1/4] soc: fsl: qe: Add an interrupt controller for QUICC Engine Ports Christophe Leroy
2025-08-13 7:49 ` kernel test robot
2025-08-12 11:02 ` [PATCH 2/4] soc: fsl: qe: Change GPIO driver to a proper platform driver Christophe Leroy
2025-08-12 14:16 ` Bartosz Golaszewski
2025-08-12 14:20 ` Bartosz Golaszewski
2025-08-12 11:02 ` [PATCH 3/4] soc: fsl: qe: Add support of IRQ in QE GPIO Christophe Leroy
2025-08-12 14:21 ` Bartosz Golaszewski
2025-08-18 8:33 ` Christophe Leroy
2025-08-12 15:30 ` Krzysztof Kozlowski
2025-08-12 11:02 ` [PATCH 4/4] dt-bindings: soc: fsl: qe: Add an interrupt controller for QUICC Engine Ports Christophe Leroy
2025-08-12 14:32 ` Rob Herring (Arm)
2025-08-12 15:23 ` Krzysztof Kozlowski [this message]
2025-08-12 17:16 ` Rob Herring
2025-08-18 8:39 ` Christophe Leroy
2025-08-18 8:37 ` Christophe Leroy
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=0fd6fefc-9fad-4ea6-a619-e9f480747ac0@kernel.org \
--to=krzk@kernel.org \
--cc=brgl@bgdev.pl \
--cc=christophe.leroy@csgroup.eu \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=krzk+dt@kernel.org \
--cc=linus.walleij@linaro.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-gpio@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linuxppc-dev@lists.ozlabs.org \
--cc=qiang.zhao@nxp.com \
--cc=robh@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).