From: claudiu beznea <claudiu.beznea@tuxon.dev>
To: Prabhakar <prabhakar.csengg@gmail.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Linus Walleij <linus.walleij@linaro.org>
Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org,
linux-kernel@vger.kernel.org,
Biju Das <biju.das.jz@bp.renesas.com>,
Fabrizio Castro <fabrizio.castro.jz@renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH 1/4] pinctrl: renesas: rzg2l: Update PIN_CFG_MASK() macro to be 32-bit wide
Date: Mon, 24 Jun 2024 07:56:51 +0300 [thread overview]
Message-ID: <10afc62d-b58a-499f-9cc4-ba8905cece64@tuxon.dev> (raw)
In-Reply-To: <20240618174831.415583-2-prabhakar.mahadev-lad.rj@bp.renesas.com>
On 18.06.2024 20:48, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Modify the `PIN_CFG_MASK()` macro to be 32-bit wide. The current maximum
> value for `PIN_CFG_*` is `BIT(21)`, which fits within a 32-bit mask.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> ---
> drivers/pinctrl/renesas/pinctrl-rzg2l.c | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> index 32945d4c8dc0..bfaeeb00ac4a 100644
> --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> @@ -89,7 +89,7 @@
>
> #define PIN_CFG_PIN_MAP_MASK GENMASK_ULL(62, 55)
> #define PIN_CFG_PIN_REG_MASK GENMASK_ULL(54, 47)
> -#define PIN_CFG_MASK GENMASK_ULL(46, 0)
> +#define PIN_CFG_MASK GENMASK_ULL(31, 0)
>
> /*
> * m indicates the bitmap of supported pins, a is the register index
> @@ -1187,7 +1187,7 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
> u64 *pin_data = pin->drv_data;
> unsigned int arg = 0;
> u32 off;
> - u64 cfg;
> + u32 cfg;
> int ret;
> u8 bit;
>
> @@ -1322,7 +1322,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
> u64 *pin_data = pin->drv_data;
> unsigned int i, arg, index;
> u32 off, param;
> - u64 cfg;
> + u32 cfg;
> int ret;
> u8 bit;
>
> @@ -2755,9 +2755,9 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen
>
> for (u32 port = 0; port < nports; port++) {
> bool has_iolh, has_ien;
> - u64 cfg, caps;
> + u32 off, caps;
> u8 pincnt;
> - u32 off;
> + u64 cfg;
>
> cfg = pctrl->data->port_pin_configs[port];
> off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg);
> @@ -2801,7 +2801,7 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen
> static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, bool suspend)
> {
> struct rzg2l_pinctrl_reg_cache *cache = pctrl->dedicated_cache;
> - u64 caps;
> + u32 caps;
> u32 i;
>
> /*
next prev parent reply other threads:[~2024-06-24 4:56 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-18 17:48 [PATCH 0/4] pinctrl: renesas: rzg2l: Macro Updates and Reorganization for Pin Configuration Prabhakar
2024-06-18 17:48 ` [PATCH 1/4] pinctrl: renesas: rzg2l: Update PIN_CFG_MASK() macro to be 32-bit wide Prabhakar
2024-06-21 12:14 ` Geert Uytterhoeven
2024-06-24 4:56 ` claudiu beznea [this message]
2024-06-18 17:48 ` [PATCH 2/4] pinctrl: renesas: rzg2l: Adjust bit masks for PIN_CFG_VARIABLE to use BIT(62) Prabhakar
2024-06-21 12:14 ` Geert Uytterhoeven
2024-06-24 4:57 ` claudiu beznea
2024-06-18 17:48 ` [PATCH 3/4] pinctrl: renesas: rzg2l: Move RZG2L_SINGLE_PIN definition to top of the file Prabhakar
2024-06-21 12:15 ` Geert Uytterhoeven
2024-06-24 4:57 ` claudiu beznea
2024-06-18 17:48 ` [PATCH 4/4] pinctrl: renesas: rzg2l: Reorganize variable configuration macro Prabhakar
2024-06-21 12:17 ` Geert Uytterhoeven
2024-06-21 12:34 ` Lad, Prabhakar
2024-06-24 4:57 ` claudiu beznea
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