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AJvYcCUHX/U+QMvqTjITu8BRtsfkEUey2sFZ4V9RSaSMAGa5o8V4NudvzoCADme+96YIDncfyV/40HTulgV6FQ/9ie7yEr9FyMSt+GEilw== X-Gm-Message-State: AOJu0YzYDsyVl75Tg7X1WPLAZ/2MkJZzX9bOkAmjKWsmeZxu6aEtqj4b 6w4MzU70lqOpso6SyodqV3SOl/gQgKACrECW0tFvmJYmr9uiBHcQVnys6ACcQsw= X-Google-Smtp-Source: AGHT+IHyBzk2CXG4/Qhw8e+uhBRG0J+M+VYIbsPIi8pyPckrwMs/nV4rQV2Emc4LsJMK0lOMIkSQiA== X-Received: by 2002:a2e:95d4:0:b0:2ec:40ab:694d with SMTP id 38308e7fff4ca-2ec593be836mr23803111fa.1.1719205013392; Sun, 23 Jun 2024 21:56:53 -0700 (PDT) Received: from [192.168.50.4] ([82.78.167.70]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-57d303d7aecsm4209761a12.20.2024.06.23.21.56.52 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 23 Jun 2024 21:56:52 -0700 (PDT) Message-ID: <10afc62d-b58a-499f-9cc4-ba8905cece64@tuxon.dev> Date: Mon, 24 Jun 2024 07:56:51 +0300 Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/4] pinctrl: renesas: rzg2l: Update PIN_CFG_MASK() macro to be 32-bit wide Content-Language: en-US To: Prabhakar , Geert Uytterhoeven , Linus Walleij Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Biju Das , Fabrizio Castro , Lad Prabhakar References: <20240618174831.415583-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20240618174831.415583-2-prabhakar.mahadev-lad.rj@bp.renesas.com> From: claudiu beznea In-Reply-To: <20240618174831.415583-2-prabhakar.mahadev-lad.rj@bp.renesas.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 18.06.2024 20:48, Prabhakar wrote: > From: Lad Prabhakar > > Modify the `PIN_CFG_MASK()` macro to be 32-bit wide. The current maximum > value for `PIN_CFG_*` is `BIT(21)`, which fits within a 32-bit mask. > > Signed-off-by: Lad Prabhakar Tested-by: Claudiu Beznea > --- > drivers/pinctrl/renesas/pinctrl-rzg2l.c | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c > index 32945d4c8dc0..bfaeeb00ac4a 100644 > --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c > +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c > @@ -89,7 +89,7 @@ > > #define PIN_CFG_PIN_MAP_MASK GENMASK_ULL(62, 55) > #define PIN_CFG_PIN_REG_MASK GENMASK_ULL(54, 47) > -#define PIN_CFG_MASK GENMASK_ULL(46, 0) > +#define PIN_CFG_MASK GENMASK_ULL(31, 0) > > /* > * m indicates the bitmap of supported pins, a is the register index > @@ -1187,7 +1187,7 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, > u64 *pin_data = pin->drv_data; > unsigned int arg = 0; > u32 off; > - u64 cfg; > + u32 cfg; > int ret; > u8 bit; > > @@ -1322,7 +1322,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, > u64 *pin_data = pin->drv_data; > unsigned int i, arg, index; > u32 off, param; > - u64 cfg; > + u32 cfg; > int ret; > u8 bit; > > @@ -2755,9 +2755,9 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen > > for (u32 port = 0; port < nports; port++) { > bool has_iolh, has_ien; > - u64 cfg, caps; > + u32 off, caps; > u8 pincnt; > - u32 off; > + u64 cfg; > > cfg = pctrl->data->port_pin_configs[port]; > off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg); > @@ -2801,7 +2801,7 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_pinctrl *pctrl, bool suspen > static void rzg2l_pinctrl_pm_setup_dedicated_regs(struct rzg2l_pinctrl *pctrl, bool suspend) > { > struct rzg2l_pinctrl_reg_cache *cache = pctrl->dedicated_cache; > - u64 caps; > + u32 caps; > u32 i; > > /*