* [PATCH 2/5] ARM: sa1100: merge both GPIO irqdomains
2014-12-22 10:05 [PATCH 1/5] ARM: sa1100: split irq handling for low GPIOs Dmitry Eremin-Solenikov
@ 2014-12-22 10:05 ` Dmitry Eremin-Solenikov
2014-12-22 10:05 ` [PATCH 3/5] ARM: sa1100: switch to irq_domain_add_simple() Dmitry Eremin-Solenikov
` (3 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Dmitry Eremin-Solenikov @ 2014-12-22 10:05 UTC (permalink / raw)
To: Russell King, Linus Walleij
Cc: Alexandre Courbot, linux-arm-kernel, linux-gpio
Now there is no difference between low and high GPIO irqdomains. Merge
them into single irqdomain handling all GPIOs.
Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
---
arch/arm/mach-sa1100/irq.c | 57 +++++++++-------------------------------------
1 file changed, 11 insertions(+), 46 deletions(-)
diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c
index 2dc6a2a..5589b23 100644
--- a/arch/arm/mach-sa1100/irq.c
+++ b/arch/arm/mach-sa1100/irq.c
@@ -154,10 +154,10 @@ static int sa1100_gpio_wake(struct irq_data *d, unsigned int on)
}
/*
- * This is for IRQs from 0 to 10.
+ * This is for GPIO IRQs
*/
-static struct irq_chip sa1100_low_gpio_chip = {
- .name = "GPIO-l",
+static struct irq_chip sa1100_gpio_chip = {
+ .name = "GPIO",
.irq_ack = sa1100_gpio_ack,
.irq_mask = sa1100_gpio_mask,
.irq_unmask = sa1100_gpio_unmask,
@@ -165,22 +165,22 @@ static struct irq_chip sa1100_low_gpio_chip = {
.irq_set_wake = sa1100_gpio_wake,
};
-static int sa1100_low_gpio_irqdomain_map(struct irq_domain *d,
+static int sa1100_gpio_irqdomain_map(struct irq_domain *d,
unsigned int irq, irq_hw_number_t hwirq)
{
- irq_set_chip_and_handler(irq, &sa1100_low_gpio_chip,
+ irq_set_chip_and_handler(irq, &sa1100_gpio_chip,
handle_edge_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
return 0;
}
-static struct irq_domain_ops sa1100_low_gpio_irqdomain_ops = {
- .map = sa1100_low_gpio_irqdomain_map,
+static struct irq_domain_ops sa1100_gpio_irqdomain_ops = {
+ .map = sa1100_gpio_irqdomain_map,
.xlate = irq_domain_xlate_onetwocell,
};
-static struct irq_domain *sa1100_low_gpio_irqdomain;
+static struct irq_domain *sa1100_gpio_irqdomain;
/*
* IRQ 0-11 (GPIO) handler. We enter here with the
@@ -212,37 +212,6 @@ sa1100_gpio_handler(unsigned int irq, struct irq_desc *desc)
} while (mask);
}
-/*
- * Like GPIO0 to 10, GPIO11-27 IRQs need to be handled specially.
- * In addition, the IRQs are all collected up into one bit in the
- * interrupt controller registers.
- */
-static struct irq_chip sa1100_high_gpio_chip = {
- .name = "GPIO-h",
- .irq_ack = sa1100_gpio_ack,
- .irq_mask = sa1100_gpio_mask,
- .irq_unmask = sa1100_gpio_unmask,
- .irq_set_type = sa1100_gpio_type,
- .irq_set_wake = sa1100_gpio_wake,
-};
-
-static int sa1100_high_gpio_irqdomain_map(struct irq_domain *d,
- unsigned int irq, irq_hw_number_t hwirq)
-{
- irq_set_chip_and_handler(irq, &sa1100_high_gpio_chip,
- handle_edge_irq);
- set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-
- return 0;
-}
-
-static struct irq_domain_ops sa1100_high_gpio_irqdomain_ops = {
- .map = sa1100_high_gpio_irqdomain_map,
- .xlate = irq_domain_xlate_onetwocell,
-};
-
-static struct irq_domain *sa1100_high_gpio_irqdomain;
-
static struct resource irq_resource =
DEFINE_RES_MEM_NAMED(0x90050000, SZ_64K, "irqs");
@@ -353,13 +322,9 @@ void __init sa1100_init_irq(void)
32, IRQ_GPIO0_SC, 0,
&sa1100_normal_irqdomain_ops, NULL);
- sa1100_low_gpio_irqdomain = irq_domain_add_legacy(NULL,
- 11, IRQ_GPIO0, 0,
- &sa1100_low_gpio_irqdomain_ops, NULL);
-
- sa1100_high_gpio_irqdomain = irq_domain_add_legacy(NULL,
- 17, IRQ_GPIO11, 11,
- &sa1100_high_gpio_irqdomain_ops, NULL);
+ sa1100_gpio_irqdomain = irq_domain_add_legacy(NULL,
+ 28, IRQ_GPIO0, 0,
+ &sa1100_gpio_irqdomain_ops, NULL);
/*
* Install handlers for GPIO 0-10 edge detect interrupts
--
2.1.3
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 3/5] ARM: sa1100: switch to irq_domain_add_simple()
2014-12-22 10:05 [PATCH 1/5] ARM: sa1100: split irq handling for low GPIOs Dmitry Eremin-Solenikov
2014-12-22 10:05 ` [PATCH 2/5] ARM: sa1100: merge both GPIO irqdomains Dmitry Eremin-Solenikov
@ 2014-12-22 10:05 ` Dmitry Eremin-Solenikov
2014-12-22 10:05 ` [PATCH 4/5] ARM: sa1100: move GPIO-related IRQ code to gpio driver Dmitry Eremin-Solenikov
` (2 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Dmitry Eremin-Solenikov @ 2014-12-22 10:05 UTC (permalink / raw)
To: Russell King, Linus Walleij
Cc: Alexandre Courbot, linux-arm-kernel, linux-gpio
As now both SC and GPIO irq domains start from 0 hwirq and do not
contain holes, switch to using irq_domain_add_simple() instead of
irq_domain_add_legacy().
Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
---
arch/arm/mach-sa1100/irq.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c
index 5589b23..a9dfe8e 100644
--- a/arch/arm/mach-sa1100/irq.c
+++ b/arch/arm/mach-sa1100/irq.c
@@ -318,12 +318,12 @@ void __init sa1100_init_irq(void)
*/
ICCR = 1;
- sa1100_normal_irqdomain = irq_domain_add_legacy(NULL,
- 32, IRQ_GPIO0_SC, 0,
+ sa1100_normal_irqdomain = irq_domain_add_simple(NULL,
+ 32, IRQ_GPIO0_SC,
&sa1100_normal_irqdomain_ops, NULL);
- sa1100_gpio_irqdomain = irq_domain_add_legacy(NULL,
- 28, IRQ_GPIO0, 0,
+ sa1100_gpio_irqdomain = irq_domain_add_simple(NULL,
+ 28, IRQ_GPIO0,
&sa1100_gpio_irqdomain_ops, NULL);
/*
--
2.1.3
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 4/5] ARM: sa1100: move GPIO-related IRQ code to gpio driver
2014-12-22 10:05 [PATCH 1/5] ARM: sa1100: split irq handling for low GPIOs Dmitry Eremin-Solenikov
2014-12-22 10:05 ` [PATCH 2/5] ARM: sa1100: merge both GPIO irqdomains Dmitry Eremin-Solenikov
2014-12-22 10:05 ` [PATCH 3/5] ARM: sa1100: switch to irq_domain_add_simple() Dmitry Eremin-Solenikov
@ 2014-12-22 10:05 ` Dmitry Eremin-Solenikov
2014-12-22 10:05 ` [PATCH 5/5] ARM: sa1100: use handle_domain_irq Dmitry Eremin-Solenikov
2015-01-14 9:35 ` [PATCH 1/5] ARM: sa1100: split irq handling for low GPIOs Linus Walleij
4 siblings, 0 replies; 7+ messages in thread
From: Dmitry Eremin-Solenikov @ 2014-12-22 10:05 UTC (permalink / raw)
To: Russell King, Linus Walleij
Cc: Alexandre Courbot, linux-arm-kernel, linux-gpio
As a part of driver consolidation, move GPIO-related IRQ code to
drivers/gpio/gpio-sa1100.c. The code does not use GPIOLIB_IRQCHIP (yet),
because sa1100 does not have a device for gpios, which is a requirement
for GPIOLIB_IRQCHIP. This will be the next step.
Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
---
arch/arm/mach-sa1100/irq.c | 174 ---------------------------------------
drivers/gpio/gpio-sa1100.c | 197 +++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 197 insertions(+), 174 deletions(-)
diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c
index a9dfe8e..a7d116a 100644
--- a/arch/arm/mach-sa1100/irq.c
+++ b/arch/arm/mach-sa1100/irq.c
@@ -80,138 +80,6 @@ static struct irq_domain_ops sa1100_normal_irqdomain_ops = {
static struct irq_domain *sa1100_normal_irqdomain;
-/*
- * SA1100 GPIO edge detection for IRQs:
- * IRQs are generated on Falling-Edge, Rising-Edge, or both.
- * Use this instead of directly setting GRER/GFER.
- */
-static int GPIO_IRQ_rising_edge;
-static int GPIO_IRQ_falling_edge;
-static int GPIO_IRQ_mask;
-
-static int sa1100_gpio_type(struct irq_data *d, unsigned int type)
-{
- unsigned int mask;
-
- mask = BIT(d->hwirq);
-
- if (type == IRQ_TYPE_PROBE) {
- if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask)
- return 0;
- type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
- }
-
- if (type & IRQ_TYPE_EDGE_RISING) {
- GPIO_IRQ_rising_edge |= mask;
- } else
- GPIO_IRQ_rising_edge &= ~mask;
- if (type & IRQ_TYPE_EDGE_FALLING) {
- GPIO_IRQ_falling_edge |= mask;
- } else
- GPIO_IRQ_falling_edge &= ~mask;
-
- GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
- GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
-
- return 0;
-}
-
-/*
- * GPIO IRQs must be acknowledged.
- */
-static void sa1100_gpio_ack(struct irq_data *d)
-{
- GEDR = BIT(d->hwirq);
-}
-
-static void sa1100_gpio_mask(struct irq_data *d)
-{
- unsigned int mask = BIT(d->hwirq);
-
- GPIO_IRQ_mask &= ~mask;
-
- GRER &= ~mask;
- GFER &= ~mask;
-}
-
-static void sa1100_gpio_unmask(struct irq_data *d)
-{
- unsigned int mask = BIT(d->hwirq);
-
- GPIO_IRQ_mask |= mask;
-
- GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
- GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
-}
-
-static int sa1100_gpio_wake(struct irq_data *d, unsigned int on)
-{
- if (on)
- PWER |= BIT(d->hwirq);
- else
- PWER &= ~BIT(d->hwirq);
- return 0;
-}
-
-/*
- * This is for GPIO IRQs
- */
-static struct irq_chip sa1100_gpio_chip = {
- .name = "GPIO",
- .irq_ack = sa1100_gpio_ack,
- .irq_mask = sa1100_gpio_mask,
- .irq_unmask = sa1100_gpio_unmask,
- .irq_set_type = sa1100_gpio_type,
- .irq_set_wake = sa1100_gpio_wake,
-};
-
-static int sa1100_gpio_irqdomain_map(struct irq_domain *d,
- unsigned int irq, irq_hw_number_t hwirq)
-{
- irq_set_chip_and_handler(irq, &sa1100_gpio_chip,
- handle_edge_irq);
- set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-
- return 0;
-}
-
-static struct irq_domain_ops sa1100_gpio_irqdomain_ops = {
- .map = sa1100_gpio_irqdomain_map,
- .xlate = irq_domain_xlate_onetwocell,
-};
-
-static struct irq_domain *sa1100_gpio_irqdomain;
-
-/*
- * IRQ 0-11 (GPIO) handler. We enter here with the
- * irq_controller_lock held, and IRQs disabled. Decode the IRQ
- * and call the handler.
- */
-static void
-sa1100_gpio_handler(unsigned int irq, struct irq_desc *desc)
-{
- unsigned int mask;
-
- mask = GEDR;
- do {
- /*
- * clear down all currently active IRQ sources.
- * We will be processing them all.
- */
- GEDR = mask;
-
- irq = IRQ_GPIO0;
- do {
- if (mask & 1)
- generic_handle_irq(irq);
- mask >>= 1;
- irq++;
- } while (mask);
-
- mask = GEDR;
- } while (mask);
-}
-
static struct resource irq_resource =
DEFINE_RES_MEM_NAMED(0x90050000, SZ_64K, "irqs");
@@ -238,17 +106,6 @@ static int sa1100irq_suspend(void)
IC_GPIO6|IC_GPIO5|IC_GPIO4|IC_GPIO3|IC_GPIO2|
IC_GPIO1|IC_GPIO0);
- /*
- * Set the appropriate edges for wakeup.
- */
- GRER = PWER & GPIO_IRQ_rising_edge;
- GFER = PWER & GPIO_IRQ_falling_edge;
-
- /*
- * Clear any pending GPIO interrupts.
- */
- GEDR = GEDR;
-
return 0;
}
@@ -260,9 +117,6 @@ static void sa1100irq_resume(void)
ICCR = st->iccr;
ICLR = st->iclr;
- GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
- GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
-
ICMR = st->icmr;
}
}
@@ -307,11 +161,6 @@ void __init sa1100_init_irq(void)
/* all IRQs are IRQ, not FIQ */
ICLR = 0;
- /* clear all GPIO edge detects */
- GFER = 0;
- GRER = 0;
- GEDR = -1;
-
/*
* Whatever the doc says, this has to be set for the wait-on-irq
* instruction to work... on a SA1100 rev 9 at least.
@@ -322,29 +171,6 @@ void __init sa1100_init_irq(void)
32, IRQ_GPIO0_SC,
&sa1100_normal_irqdomain_ops, NULL);
- sa1100_gpio_irqdomain = irq_domain_add_simple(NULL,
- 28, IRQ_GPIO0,
- &sa1100_gpio_irqdomain_ops, NULL);
-
- /*
- * Install handlers for GPIO 0-10 edge detect interrupts
- */
- irq_set_chained_handler(IRQ_GPIO0_SC, sa1100_gpio_handler);
- irq_set_chained_handler(IRQ_GPIO1_SC, sa1100_gpio_handler);
- irq_set_chained_handler(IRQ_GPIO2_SC, sa1100_gpio_handler);
- irq_set_chained_handler(IRQ_GPIO3_SC, sa1100_gpio_handler);
- irq_set_chained_handler(IRQ_GPIO4_SC, sa1100_gpio_handler);
- irq_set_chained_handler(IRQ_GPIO5_SC, sa1100_gpio_handler);
- irq_set_chained_handler(IRQ_GPIO6_SC, sa1100_gpio_handler);
- irq_set_chained_handler(IRQ_GPIO7_SC, sa1100_gpio_handler);
- irq_set_chained_handler(IRQ_GPIO8_SC, sa1100_gpio_handler);
- irq_set_chained_handler(IRQ_GPIO9_SC, sa1100_gpio_handler);
- irq_set_chained_handler(IRQ_GPIO10_SC, sa1100_gpio_handler);
- /*
- * Install handler for GPIO 11-27 edge detect interrupts
- */
- irq_set_chained_handler(IRQ_GPIO11_27, sa1100_gpio_handler);
-
set_handle_irq(sa1100_handle_irq);
sa1100_init_gpio();
diff --git a/drivers/gpio/gpio-sa1100.c b/drivers/gpio/gpio-sa1100.c
index 5b5d3c7..bec397a 100644
--- a/drivers/gpio/gpio-sa1100.c
+++ b/drivers/gpio/gpio-sa1100.c
@@ -11,6 +11,7 @@
#include <linux/init.h>
#include <linux/module.h>
#include <linux/io.h>
+#include <linux/syscore_ops.h>
#include <mach/hardware.h>
#include <mach/irqs.h>
@@ -64,7 +65,203 @@ static struct gpio_chip sa1100_gpio_chip = {
.ngpio = GPIO_MAX + 1,
};
+/*
+ * SA1100 GPIO edge detection for IRQs:
+ * IRQs are generated on Falling-Edge, Rising-Edge, or both.
+ * Use this instead of directly setting GRER/GFER.
+ */
+static int GPIO_IRQ_rising_edge;
+static int GPIO_IRQ_falling_edge;
+static int GPIO_IRQ_mask;
+
+static int sa1100_gpio_type(struct irq_data *d, unsigned int type)
+{
+ unsigned int mask;
+
+ mask = BIT(d->hwirq);
+
+ if (type == IRQ_TYPE_PROBE) {
+ if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask)
+ return 0;
+ type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
+ }
+
+ if (type & IRQ_TYPE_EDGE_RISING)
+ GPIO_IRQ_rising_edge |= mask;
+ else
+ GPIO_IRQ_rising_edge &= ~mask;
+ if (type & IRQ_TYPE_EDGE_FALLING)
+ GPIO_IRQ_falling_edge |= mask;
+ else
+ GPIO_IRQ_falling_edge &= ~mask;
+
+ GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
+ GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
+
+ return 0;
+}
+
+/*
+ * GPIO IRQs must be acknowledged.
+ */
+static void sa1100_gpio_ack(struct irq_data *d)
+{
+ GEDR = BIT(d->hwirq);
+}
+
+static void sa1100_gpio_mask(struct irq_data *d)
+{
+ unsigned int mask = BIT(d->hwirq);
+
+ GPIO_IRQ_mask &= ~mask;
+
+ GRER &= ~mask;
+ GFER &= ~mask;
+}
+
+static void sa1100_gpio_unmask(struct irq_data *d)
+{
+ unsigned int mask = BIT(d->hwirq);
+
+ GPIO_IRQ_mask |= mask;
+
+ GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
+ GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
+}
+
+static int sa1100_gpio_wake(struct irq_data *d, unsigned int on)
+{
+ if (on)
+ PWER |= BIT(d->hwirq);
+ else
+ PWER &= ~BIT(d->hwirq);
+ return 0;
+}
+
+/*
+ * This is for GPIO IRQs
+ */
+static struct irq_chip sa1100_gpio_irq_chip = {
+ .name = "GPIO",
+ .irq_ack = sa1100_gpio_ack,
+ .irq_mask = sa1100_gpio_mask,
+ .irq_unmask = sa1100_gpio_unmask,
+ .irq_set_type = sa1100_gpio_type,
+ .irq_set_wake = sa1100_gpio_wake,
+};
+
+static int sa1100_gpio_irqdomain_map(struct irq_domain *d,
+ unsigned int irq, irq_hw_number_t hwirq)
+{
+ irq_set_chip_and_handler(irq, &sa1100_gpio_irq_chip,
+ handle_edge_irq);
+ set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+
+ return 0;
+}
+
+static struct irq_domain_ops sa1100_gpio_irqdomain_ops = {
+ .map = sa1100_gpio_irqdomain_map,
+ .xlate = irq_domain_xlate_onetwocell,
+};
+
+static struct irq_domain *sa1100_gpio_irqdomain;
+
+/*
+ * IRQ 0-11 (GPIO) handler. We enter here with the
+ * irq_controller_lock held, and IRQs disabled. Decode the IRQ
+ * and call the handler.
+ */
+static void
+sa1100_gpio_handler(unsigned int irq, struct irq_desc *desc)
+{
+ unsigned int mask;
+
+ mask = GEDR;
+ do {
+ /*
+ * clear down all currently active IRQ sources.
+ * We will be processing them all.
+ */
+ GEDR = mask;
+
+ irq = IRQ_GPIO0;
+ do {
+ if (mask & 1)
+ generic_handle_irq(irq);
+ mask >>= 1;
+ irq++;
+ } while (mask);
+
+ mask = GEDR;
+ } while (mask);
+}
+
+static int sa1100_gpio_suspend(void)
+{
+ /*
+ * Set the appropriate edges for wakeup.
+ */
+ GRER = PWER & GPIO_IRQ_rising_edge;
+ GFER = PWER & GPIO_IRQ_falling_edge;
+
+ /*
+ * Clear any pending GPIO interrupts.
+ */
+ GEDR = GEDR;
+
+ return 0;
+}
+
+static void sa1100_gpio_resume(void)
+{
+ GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
+ GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
+}
+
+static struct syscore_ops sa1100_gpio_syscore_ops = {
+ .suspend = sa1100_gpio_suspend,
+ .resume = sa1100_gpio_resume,
+};
+
+static int __init sa1100_gpio_init_devicefs(void)
+{
+ register_syscore_ops(&sa1100_gpio_syscore_ops);
+ return 0;
+}
+
+device_initcall(sa1100_gpio_init_devicefs);
+
void __init sa1100_init_gpio(void)
{
+ /* clear all GPIO edge detects */
+ GFER = 0;
+ GRER = 0;
+ GEDR = -1;
+
gpiochip_add(&sa1100_gpio_chip);
+
+ sa1100_gpio_irqdomain = irq_domain_add_simple(NULL,
+ 28, IRQ_GPIO0,
+ &sa1100_gpio_irqdomain_ops, NULL);
+
+ /*
+ * Install handlers for GPIO 0-10 edge detect interrupts
+ */
+ irq_set_chained_handler(IRQ_GPIO0_SC, sa1100_gpio_handler);
+ irq_set_chained_handler(IRQ_GPIO1_SC, sa1100_gpio_handler);
+ irq_set_chained_handler(IRQ_GPIO2_SC, sa1100_gpio_handler);
+ irq_set_chained_handler(IRQ_GPIO3_SC, sa1100_gpio_handler);
+ irq_set_chained_handler(IRQ_GPIO4_SC, sa1100_gpio_handler);
+ irq_set_chained_handler(IRQ_GPIO5_SC, sa1100_gpio_handler);
+ irq_set_chained_handler(IRQ_GPIO6_SC, sa1100_gpio_handler);
+ irq_set_chained_handler(IRQ_GPIO7_SC, sa1100_gpio_handler);
+ irq_set_chained_handler(IRQ_GPIO8_SC, sa1100_gpio_handler);
+ irq_set_chained_handler(IRQ_GPIO9_SC, sa1100_gpio_handler);
+ irq_set_chained_handler(IRQ_GPIO10_SC, sa1100_gpio_handler);
+ /*
+ * Install handler for GPIO 11-27 edge detect interrupts
+ */
+ irq_set_chained_handler(IRQ_GPIO11_27, sa1100_gpio_handler);
+
}
--
2.1.3
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 5/5] ARM: sa1100: use handle_domain_irq
2014-12-22 10:05 [PATCH 1/5] ARM: sa1100: split irq handling for low GPIOs Dmitry Eremin-Solenikov
` (2 preceding siblings ...)
2014-12-22 10:05 ` [PATCH 4/5] ARM: sa1100: move GPIO-related IRQ code to gpio driver Dmitry Eremin-Solenikov
@ 2014-12-22 10:05 ` Dmitry Eremin-Solenikov
2015-01-14 9:35 ` [PATCH 1/5] ARM: sa1100: split irq handling for low GPIOs Linus Walleij
4 siblings, 0 replies; 7+ messages in thread
From: Dmitry Eremin-Solenikov @ 2014-12-22 10:05 UTC (permalink / raw)
To: Russell King, Linus Walleij
Cc: Alexandre Courbot, linux-arm-kernel, linux-gpio
Use handle_domain_irq instead of handle_IRQ to automatically map
hardware irq number to virq.
Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
---
arch/arm/mach-sa1100/irq.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c
index a7d116a..65aebfa 100644
--- a/arch/arm/mach-sa1100/irq.c
+++ b/arch/arm/mach-sa1100/irq.c
@@ -147,7 +147,8 @@ sa1100_handle_irq(struct pt_regs *regs)
if (mask == 0)
break;
- handle_IRQ(ffs(mask) - 1 + IRQ_GPIO0_SC, regs);
+ handle_domain_irq(sa1100_normal_irqdomain,
+ ffs(mask) - 1, regs);
} while (1);
}
--
2.1.3
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH 1/5] ARM: sa1100: split irq handling for low GPIOs
2014-12-22 10:05 [PATCH 1/5] ARM: sa1100: split irq handling for low GPIOs Dmitry Eremin-Solenikov
` (3 preceding siblings ...)
2014-12-22 10:05 ` [PATCH 5/5] ARM: sa1100: use handle_domain_irq Dmitry Eremin-Solenikov
@ 2015-01-14 9:35 ` Linus Walleij
2015-01-14 9:36 ` Dmitry Eremin-Solenikov
4 siblings, 1 reply; 7+ messages in thread
From: Linus Walleij @ 2015-01-14 9:35 UTC (permalink / raw)
To: Dmitry Eremin-Solenikov
Cc: Russell King, Alexandre Courbot,
linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org
On Mon, Dec 22, 2014 at 11:05 AM, Dmitry Eremin-Solenikov
<dbaryshkov@gmail.com> wrote:
> Low GPIO pins use an interrupt in SC interrupts space. However it's
> possible to handle them as if all the GPIO interrupts are instead tied
> to single GPIO handler, which later decodes GEDR register and
> chain-calls next IRQ handler. So split first 11 interrupts into system
> part (IRQ_GPIO0_SC - IRQ_GPIO10_SC) which work exactly like the rest of
> system controller interrupts and real GPIO interrupts
> (IRQ_GPIO0..IRQ_GPIO10). A single handler sa1100_gpio_handler then
> decodes and calls next handler.
>
> Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
I applied all 5 patches and tested on the Compaq iPAQ H3600
with some GPIO lines with IRQs and all work as before.
Tested-by: Linus Walleij <linus.walleij@linaro.org>
for all 5 patches.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH 1/5] ARM: sa1100: split irq handling for low GPIOs
2015-01-14 9:35 ` [PATCH 1/5] ARM: sa1100: split irq handling for low GPIOs Linus Walleij
@ 2015-01-14 9:36 ` Dmitry Eremin-Solenikov
0 siblings, 0 replies; 7+ messages in thread
From: Dmitry Eremin-Solenikov @ 2015-01-14 9:36 UTC (permalink / raw)
To: Linus Walleij
Cc: Russell King, Alexandre Courbot,
linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org
2015-01-14 12:35 GMT+03:00 Linus Walleij <linus.walleij@linaro.org>:
> On Mon, Dec 22, 2014 at 11:05 AM, Dmitry Eremin-Solenikov
> <dbaryshkov@gmail.com> wrote:
>
>> Low GPIO pins use an interrupt in SC interrupts space. However it's
>> possible to handle them as if all the GPIO interrupts are instead tied
>> to single GPIO handler, which later decodes GEDR register and
>> chain-calls next IRQ handler. So split first 11 interrupts into system
>> part (IRQ_GPIO0_SC - IRQ_GPIO10_SC) which work exactly like the rest of
>> system controller interrupts and real GPIO interrupts
>> (IRQ_GPIO0..IRQ_GPIO10). A single handler sa1100_gpio_handler then
>> decodes and calls next handler.
>>
>> Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
>
> I applied all 5 patches and tested on the Compaq iPAQ H3600
> with some GPIO lines with IRQs and all work as before.
>
> Tested-by: Linus Walleij <linus.walleij@linaro.org>
> for all 5 patches.
Thank you!
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 7+ messages in thread