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From: Maxime Coquelin <mcoquelin.stm32-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: u.kleine-koenig-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org,
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Subject: [PATCH v5 06/15] drivers: reset: Add STM32 reset driver
Date: Fri,  3 Apr 2015 19:01:12 +0200	[thread overview]
Message-ID: <1428080481-18591-7-git-send-email-mcoquelin.stm32@gmail.com> (raw)
In-Reply-To: <1428080481-18591-1-git-send-email-mcoquelin.stm32-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

The STM32 MCUs family IPs can be reset by accessing some registers
from the RCC block.

The list of available reset lines is documented in the DT bindings.

Tested-by: Chanwoo Choi <cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
Acked-by: Philipp Zabel <p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
Signed-off-by: Maxime Coquelin <mcoquelin.stm32-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 drivers/reset/Makefile      |   1 +
 drivers/reset/reset-stm32.c | 124 ++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 125 insertions(+)
 create mode 100644 drivers/reset/reset-stm32.c

diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 157d421..aed12d1 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -1,5 +1,6 @@
 obj-$(CONFIG_RESET_CONTROLLER) += core.o
 obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o
 obj-$(CONFIG_ARCH_BERLIN) += reset-berlin.o
+obj-$(CONFIG_ARCH_STM32) += reset-stm32.o
 obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o
 obj-$(CONFIG_ARCH_STI) += sti/
diff --git a/drivers/reset/reset-stm32.c b/drivers/reset/reset-stm32.c
new file mode 100644
index 0000000..2c41858
--- /dev/null
+++ b/drivers/reset/reset-stm32.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright (C) Maxime Coquelin 2015
+ * Author:  Maxime Coquelin <mcoquelin.stm32-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
+ * License terms:  GNU General Public License (GPL), version 2
+ *
+ * Heavily based on sunxi driver from Maxime Ripard.
+ */
+
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+
+struct stm32_reset_data {
+	spinlock_t			lock;
+	void __iomem			*membase;
+	struct reset_controller_dev	rcdev;
+};
+
+static int stm32_reset_assert(struct reset_controller_dev *rcdev,
+			      unsigned long id)
+{
+	struct stm32_reset_data *data = container_of(rcdev,
+						     struct stm32_reset_data,
+						     rcdev);
+	int bank = id / BITS_PER_LONG;
+	int offset = id % BITS_PER_LONG;
+	unsigned long flags;
+	u32 reg;
+
+	spin_lock_irqsave(&data->lock, flags);
+
+	reg = readl_relaxed(data->membase + (bank * 4));
+	writel_relaxed(reg | BIT(offset), data->membase + (bank * 4));
+
+	spin_unlock_irqrestore(&data->lock, flags);
+
+	return 0;
+}
+
+static int stm32_reset_deassert(struct reset_controller_dev *rcdev,
+				unsigned long id)
+{
+	struct stm32_reset_data *data = container_of(rcdev,
+						     struct stm32_reset_data,
+						     rcdev);
+	int bank = id / BITS_PER_LONG;
+	int offset = id % BITS_PER_LONG;
+	unsigned long flags;
+	u32 reg;
+
+	spin_lock_irqsave(&data->lock, flags);
+
+	reg = readl_relaxed(data->membase + (bank * 4));
+	writel_relaxed(reg & ~BIT(offset), data->membase + (bank * 4));
+
+	spin_unlock_irqrestore(&data->lock, flags);
+
+	return 0;
+}
+
+static struct reset_control_ops stm32_reset_ops = {
+	.assert		= stm32_reset_assert,
+	.deassert	= stm32_reset_deassert,
+};
+
+static const struct of_device_id stm32_reset_dt_ids[] = {
+	 { .compatible = "st,stm32-rcc", },
+	 { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, sstm32_reset_dt_ids);
+
+static int stm32_reset_probe(struct platform_device *pdev)
+{
+	struct stm32_reset_data *data;
+	struct resource *res;
+
+	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	data->membase = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(data->membase))
+		return PTR_ERR(data->membase);
+
+	spin_lock_init(&data->lock);
+
+	data->rcdev.owner = THIS_MODULE;
+	data->rcdev.nr_resets = resource_size(res) * 8;
+	data->rcdev.ops = &stm32_reset_ops;
+	data->rcdev.of_node = pdev->dev.of_node;
+
+	return reset_controller_register(&data->rcdev);
+}
+
+static int stm32_reset_remove(struct platform_device *pdev)
+{
+	struct stm32_reset_data *data = platform_get_drvdata(pdev);
+
+	reset_controller_unregister(&data->rcdev);
+
+	return 0;
+}
+
+static struct platform_driver stm32_reset_driver = {
+	.probe	= stm32_reset_probe,
+	.remove	= stm32_reset_remove,
+	.driver = {
+		.name		= "stm32-rcc-reset",
+		.of_match_table	= stm32_reset_dt_ids,
+	},
+};
+module_platform_driver(stm32_reset_driver);
+
+MODULE_AUTHOR("Maxime Coquelin <maxime.coquelin-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>");
+MODULE_DESCRIPTION("STM32 MCUs Reset Controller Driver");
+MODULE_LICENSE("GPL");
-- 
1.9.1

  parent reply	other threads:[~2015-04-03 17:01 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-04-03 17:01 [PATCH v5 00/15] Add support to STMicroelectronics STM32 family Maxime Coquelin
2015-04-03 17:01 ` [PATCH v5 02/15] ARM: ARMv7-M: Enlarge vector table up to 256 entries Maxime Coquelin
2015-04-03 17:01 ` [PATCH v5 03/15] dt-bindings: Document the ARM System timer bindings Maxime Coquelin
2015-04-03 17:09   ` Rob Herring
2015-04-03 17:01 ` [PATCH v5 04/15] clocksource/drivers: Add ARM System timer driver Maxime Coquelin
2015-04-03 17:01 ` [PATCH v5 05/15] dt-bindings: Document the STM32 reset bindings Maxime Coquelin
2015-04-03 17:01 ` [PATCH v5 07/15] dt-bindings: Document the STM32 timer bindings Maxime Coquelin
2015-04-03 17:10   ` Rob Herring
2015-04-03 17:01 ` [PATCH v5 08/15] clockevents/drivers: Add STM32 Timer driver Maxime Coquelin
2015-04-03 22:09   ` Andy Shevchenko
     [not found]     ` <CAHp75VfPn_+sg_1iR_CdR2KuTyWcR+SKFsuHCbCkCKB0Oeqgfg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2015-04-03 22:14       ` Andy Shevchenko
2015-04-03 17:01 ` [PATCH v5 10/15] serial: stm32-usart: Add STM32 USART Driver Maxime Coquelin
2015-04-03 17:29   ` Peter Hurley
     [not found]   ` <1428080481-18591-11-git-send-email-mcoquelin.stm32-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2015-04-03 17:43     ` Joe Perches
2015-04-07  7:56       ` Maxime Coquelin
2015-04-03 22:04   ` Andy Shevchenko
2015-04-07 16:05     ` Maxime Coquelin
     [not found] ` <1428080481-18591-1-git-send-email-mcoquelin.stm32-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2015-04-03 17:01   ` [PATCH v5 01/15] scripts: link-vmlinux: Don't pass page offset to kallsyms if XIP Kernel Maxime Coquelin
2015-04-03 17:01   ` Maxime Coquelin [this message]
2015-04-03 17:01   ` [PATCH v5 09/15] dt-bindings: Document the STM32 USART bindings Maxime Coquelin
     [not found]     ` <1428080481-18591-10-git-send-email-mcoquelin.stm32-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2015-04-03 17:14       ` Rob Herring
2015-04-07 15:49         ` Maxime Coquelin
2015-04-03 17:01   ` [PATCH v5 11/15] ARM: Add STM32 family machine Maxime Coquelin
2015-04-03 17:01   ` [PATCH v5 13/15] ARM: dts: Introduce STM32F429 MCU Maxime Coquelin
2015-04-03 17:01   ` [PATCH v5 15/15] MAINTAINERS: Add entry for STM32 MCUs Maxime Coquelin
2015-04-03 17:01 ` [PATCH v5 12/15] ARM: dts: Add ARM System timer as clockevent in armv7m Maxime Coquelin
2015-04-03 17:01 ` [PATCH v5 14/15] ARM: configs: Add STM32 defconfig Maxime Coquelin

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