* [PATCH 0/8] add basic support for i.mx6 ul chip
@ 2015-06-17 15:39 Frank.Li-KZfg59tc24xl57MIdRCFDg
2015-06-17 15:39 ` [PATCH 1/8] ARM: imx: add i.mx6ul msl support Frank.Li
` (3 more replies)
0 siblings, 4 replies; 16+ messages in thread
From: Frank.Li-KZfg59tc24xl57MIdRCFDg @ 2015-06-17 15:39 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
shawn.guo-QSEj5FYQhm4dnm+yROfE0A, shawnguo-DgEjT+Ai2ygdnm+yROfE0A,
linus.walleij-QSEj5FYQhm4dnm+yROfE0A,
lznuaa-Re5JQEeQqe8AvxtiuMwx3w
Cc: linux-gpio-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
devicetree-u79uwXL29TY76Z2rM5mHXA, Frank Li
From: Frank Li <Frank.Li-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
Add basic function support i.mx6ul.
add simple dts.
add full pin function define
add clock support.
add low level debug
Anson Huang (1):
ARM: imx: add low-level debug support for i.mx6ul
Frank Li (7):
ARM: imx: add i.mx6ul msl support
ARM: imx: add imx6ul clk tree support
Document: dt: binding: imx: update document for imx6ul support
ARM: pinctrl: imx: add i.mx6ul pinctrl driver
ARM: dts: add i.mx6ul pin function include file
ARM: dts: imx: add imx6ul and imx6ul evk board support
ARM: imx: imx_v6_v7_defconfig enable imx6ul support
.../devicetree/bindings/clock/imx6ul-clock.txt | 13 +
.../bindings/pinctrl/fsl,imx6ul-pinctrl.txt | 36 +
arch/arm/Kconfig.debug | 9 +
arch/arm/boot/dts/Makefile | 2 +
arch/arm/boot/dts/imx6ul-14x14-evk.dts | 337 ++++++++
arch/arm/boot/dts/imx6ul-pinfunc.h | 938 +++++++++++++++++++++
arch/arm/boot/dts/imx6ul.dtsi | 645 ++++++++++++++
arch/arm/configs/imx_v6_v7_defconfig | 1 +
arch/arm/include/debug/imx-uart.h | 13 +
arch/arm/mach-imx/Kconfig | 8 +
arch/arm/mach-imx/Makefile | 1 +
arch/arm/mach-imx/mach-imx6ul.c | 43 +
drivers/clk/imx/Makefile | 1 +
drivers/clk/imx/clk-imx6ul.c | 436 ++++++++++
drivers/pinctrl/freescale/Kconfig | 7 +
drivers/pinctrl/freescale/Makefile | 1 +
drivers/pinctrl/freescale/pinctrl-imx6ul.c | 323 +++++++
include/dt-bindings/clock/imx6ul-clock.h | 240 ++++++
18 files changed, 3054 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/imx6ul-clock.txt
create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx6ul-pinctrl.txt
create mode 100644 arch/arm/boot/dts/imx6ul-14x14-evk.dts
create mode 100644 arch/arm/boot/dts/imx6ul-pinfunc.h
create mode 100644 arch/arm/boot/dts/imx6ul.dtsi
create mode 100644 arch/arm/mach-imx/mach-imx6ul.c
create mode 100644 drivers/clk/imx/clk-imx6ul.c
create mode 100644 drivers/pinctrl/freescale/pinctrl-imx6ul.c
create mode 100644 include/dt-bindings/clock/imx6ul-clock.h
--
1.9.1
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^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH 1/8] ARM: imx: add i.mx6ul msl support 2015-06-17 15:39 [PATCH 0/8] add basic support for i.mx6 ul chip Frank.Li-KZfg59tc24xl57MIdRCFDg @ 2015-06-17 15:39 ` Frank.Li 2015-07-09 2:17 ` Shawn Guo 2015-06-17 15:39 ` [PATCH 3/8] Document: dt: binding: imx: update document for imx6ul support Frank.Li ` (2 subsequent siblings) 3 siblings, 1 reply; 16+ messages in thread From: Frank.Li @ 2015-06-17 15:39 UTC (permalink / raw) To: linux-arm-kernel, shawn.guo, shawnguo, linus.walleij, lznuaa Cc: linux-gpio, robh+dt, devicetree, Frank Li From: Frank Li <Frank.Li@freescale.com> i.MX6UL is a new SOC, add MSL support Signed-off-by: Frank Li <Frank.Li@freescale.com> --- arch/arm/mach-imx/Kconfig | 8 ++++++++ arch/arm/mach-imx/Makefile | 1 + arch/arm/mach-imx/mach-imx6ul.c | 43 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 52 insertions(+) create mode 100644 arch/arm/mach-imx/mach-imx6ul.c diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 573536f..8ceda28 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -548,6 +548,14 @@ config SOC_IMX6SX help This enables support for Freescale i.MX6 SoloX processor. +config SOC_IMX6UL + bool "i.MX6 UltraLite support" + select PINCTRL_IMX6UL + select SOC_IMX6 + + help + This enables support for Freescale i.MX6 UltraLite processor. + config SOC_IMX7D bool "i.MX7 Dual support" select PINCTRL_IMX7D diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 37c502a..fb689d8 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -83,6 +83,7 @@ endif obj-$(CONFIG_SOC_IMX6Q) += mach-imx6q.o obj-$(CONFIG_SOC_IMX6SL) += mach-imx6sl.o obj-$(CONFIG_SOC_IMX6SX) += mach-imx6sx.o +obj-$(CONFIG_SOC_IMX6UL) += mach-imx6ul.o obj-$(CONFIG_SOC_IMX7D) += mach-imx7d.o ifeq ($(CONFIG_SUSPEND),y) diff --git a/arch/arm/mach-imx/mach-imx6ul.c b/arch/arm/mach-imx/mach-imx6ul.c new file mode 100644 index 0000000..706d5f6 --- /dev/null +++ b/arch/arm/mach-imx/mach-imx6ul.c @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/irqchip.h> +#include <linux/of_platform.h> +#include <asm/mach/arch.h> +#include <asm/mach/map.h> + +#include "common.h" + +static void __init imx6ul_init_machine(void) +{ + struct device *parent; + + parent = imx_soc_device_init(); + if (parent == NULL) + pr_warn("failed to initialize soc device\n"); + + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); + imx_anatop_init(); +} + +static void __init imx6ul_init_irq(void) +{ + imx_init_revision_from_anatop(); + imx_src_init(); + irqchip_init(); +} + +static const char *imx6ul_dt_compat[] __initconst = { + "fsl,imx6ul", + NULL, +}; + +DT_MACHINE_START(IMX7D, "Freescale i.MX6 Ultralite (Device Tree)") + .init_irq = imx6ul_init_irq, + .init_machine = imx6ul_init_machine, + .dt_compat = imx6ul_dt_compat, +MACHINE_END -- 1.9.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH 1/8] ARM: imx: add i.mx6ul msl support 2015-06-17 15:39 ` [PATCH 1/8] ARM: imx: add i.mx6ul msl support Frank.Li @ 2015-07-09 2:17 ` Shawn Guo 0 siblings, 0 replies; 16+ messages in thread From: Shawn Guo @ 2015-07-09 2:17 UTC (permalink / raw) To: Frank.Li Cc: linux-arm-kernel, shawn.guo, linus.walleij, lznuaa, linux-gpio, robh+dt, devicetree On Wed, Jun 17, 2015 at 11:39:22PM +0800, Frank.Li@freescale.com wrote: > From: Frank Li <Frank.Li@freescale.com> > > i.MX6UL is a new SOC, add MSL support > > Signed-off-by: Frank Li <Frank.Li@freescale.com> > --- > arch/arm/mach-imx/Kconfig | 8 ++++++++ > arch/arm/mach-imx/Makefile | 1 + > arch/arm/mach-imx/mach-imx6ul.c | 43 +++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 52 insertions(+) > create mode 100644 arch/arm/mach-imx/mach-imx6ul.c > > diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig > index 573536f..8ceda28 100644 > --- a/arch/arm/mach-imx/Kconfig > +++ b/arch/arm/mach-imx/Kconfig > @@ -548,6 +548,14 @@ config SOC_IMX6SX > help > This enables support for Freescale i.MX6 SoloX processor. > > +config SOC_IMX6UL > + bool "i.MX6 UltraLite support" > + select PINCTRL_IMX6UL > + select SOC_IMX6 > + > + help > + This enables support for Freescale i.MX6 UltraLite processor. > + > config SOC_IMX7D > bool "i.MX7 Dual support" > select PINCTRL_IMX7D > diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile > index 37c502a..fb689d8 100644 > --- a/arch/arm/mach-imx/Makefile > +++ b/arch/arm/mach-imx/Makefile > @@ -83,6 +83,7 @@ endif > obj-$(CONFIG_SOC_IMX6Q) += mach-imx6q.o > obj-$(CONFIG_SOC_IMX6SL) += mach-imx6sl.o > obj-$(CONFIG_SOC_IMX6SX) += mach-imx6sx.o > +obj-$(CONFIG_SOC_IMX6UL) += mach-imx6ul.o > obj-$(CONFIG_SOC_IMX7D) += mach-imx7d.o > > ifeq ($(CONFIG_SUSPEND),y) > diff --git a/arch/arm/mach-imx/mach-imx6ul.c b/arch/arm/mach-imx/mach-imx6ul.c > new file mode 100644 > index 0000000..706d5f6 > --- /dev/null > +++ b/arch/arm/mach-imx/mach-imx6ul.c > @@ -0,0 +1,43 @@ > +/* > + * Copyright (C) 2015 Freescale Semiconductor, Inc. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + */ > +#include <linux/irqchip.h> > +#include <linux/of_platform.h> > +#include <asm/mach/arch.h> > +#include <asm/mach/map.h> > + > +#include "common.h" > + > +static void __init imx6ul_init_machine(void) > +{ > + struct device *parent; > + > + parent = imx_soc_device_init(); How does the soc_id of soc_device work? I do not see any patch adding imx6ul soc_id. Shawn > + if (parent == NULL) > + pr_warn("failed to initialize soc device\n"); > + > + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); > + imx_anatop_init(); > +} > + > +static void __init imx6ul_init_irq(void) > +{ > + imx_init_revision_from_anatop(); > + imx_src_init(); > + irqchip_init(); > +} > + > +static const char *imx6ul_dt_compat[] __initconst = { > + "fsl,imx6ul", > + NULL, > +}; > + > +DT_MACHINE_START(IMX7D, "Freescale i.MX6 Ultralite (Device Tree)") > + .init_irq = imx6ul_init_irq, > + .init_machine = imx6ul_init_machine, > + .dt_compat = imx6ul_dt_compat, > +MACHINE_END > -- > 1.9.1 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel > ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 3/8] Document: dt: binding: imx: update document for imx6ul support 2015-06-17 15:39 [PATCH 0/8] add basic support for i.mx6 ul chip Frank.Li-KZfg59tc24xl57MIdRCFDg 2015-06-17 15:39 ` [PATCH 1/8] ARM: imx: add i.mx6ul msl support Frank.Li @ 2015-06-17 15:39 ` Frank.Li 2015-07-09 2:36 ` Shawn Guo 2015-06-17 15:39 ` [PATCH 4/8] ARM: pinctrl: imx: add i.mx6ul pinctrl driver Frank.Li [not found] ` <1434555569-8237-1-git-send-email-Frank.Li-KZfg59tc24xl57MIdRCFDg@public.gmane.org> 3 siblings, 1 reply; 16+ messages in thread From: Frank.Li @ 2015-06-17 15:39 UTC (permalink / raw) To: linux-arm-kernel, shawn.guo, shawnguo, linus.walleij, lznuaa Cc: linux-gpio, robh+dt, devicetree, Frank Li From: Frank Li <Frank.Li@freescale.com> This part just add necessary change to boot imx6ul. Update clock and pinctrl for imx6ul Signed-off-by: Frank Li <Frank.Li@freescale.com> Signed-off-by: Frank Li <Frank.Li@freescale.com> --- .../devicetree/bindings/clock/imx6ul-clock.txt | 13 ++++++++ .../bindings/pinctrl/fsl,imx6ul-pinctrl.txt | 36 ++++++++++++++++++++++ 2 files changed, 49 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/imx6ul-clock.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx6ul-pinctrl.txt diff --git a/Documentation/devicetree/bindings/clock/imx6ul-clock.txt b/Documentation/devicetree/bindings/clock/imx6ul-clock.txt new file mode 100644 index 0000000..3ff362e --- /dev/null +++ b/Documentation/devicetree/bindings/clock/imx6ul-clock.txt @@ -0,0 +1,13 @@ +* Clock bindings for Freescale i.MX6 UltraLite + +Required properties: +- compatible: Should be "fsl,imx6ul-ccm" +- reg: Address and length of the register set +- #clock-cells: Should be <1> +- clocks: list of clock specifiers, must contain an entry for each required + entry in clock-names +- clock-names: should include entries "ckil", "osc", "ipp_di0" and "ipp_di1" + +The clock consumer should specify the desired clock by having the clock +ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6ul-clock.h +for the full list of i.MX6 UltraLite clock IDs. diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx6ul-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx6ul-pinctrl.txt new file mode 100644 index 0000000..a81bbf3 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx6ul-pinctrl.txt @@ -0,0 +1,36 @@ +* Freescale i.MX6 UltraLite IOMUX Controller + +Please refer to fsl,imx-pinctrl.txt in this directory for common binding part +and usage. + +Required properties: +- compatible: "fsl,imx6ul-iomuxc" +- fsl,pins: each entry consists of 6 integers and represents the mux and config + setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val + input_val> are specified using a PIN_FUNC_ID macro, which can be found in + imx6ul-pinfunc.h under device tree source folder. The last integer CONFIG is + the pad setting value like pull-up on this pin. Please refer to i.MX6 UltraLite + Reference Manual for detailed CONFIG settings. + +CONFIG bits definition: +PAD_CTL_HYS (1 << 16) +PAD_CTL_PUS_100K_DOWN (0 << 14) +PAD_CTL_PUS_47K_UP (1 << 14) +PAD_CTL_PUS_100K_UP (2 << 14) +PAD_CTL_PUS_22K_UP (3 << 14) +PAD_CTL_PUE (1 << 13) +PAD_CTL_PKE (1 << 12) +PAD_CTL_ODE (1 << 11) +PAD_CTL_SPEED_LOW (0 << 6) +PAD_CTL_SPEED_MED (1 << 6) +PAD_CTL_SPEED_HIGH (3 << 6) +PAD_CTL_DSE_DISABLE (0 << 3) +PAD_CTL_DSE_260ohm (1 << 3) +PAD_CTL_DSE_130ohm (2 << 3) +PAD_CTL_DSE_87ohm (3 << 3) +PAD_CTL_DSE_65ohm (4 << 3) +PAD_CTL_DSE_52ohm (5 << 3) +PAD_CTL_DSE_43ohm (6 << 3) +PAD_CTL_DSE_37ohm (7 << 3) +PAD_CTL_SRE_FAST (1 << 0) +PAD_CTL_SRE_SLOW (0 << 0) -- 1.9.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH 3/8] Document: dt: binding: imx: update document for imx6ul support 2015-06-17 15:39 ` [PATCH 3/8] Document: dt: binding: imx: update document for imx6ul support Frank.Li @ 2015-07-09 2:36 ` Shawn Guo 0 siblings, 0 replies; 16+ messages in thread From: Shawn Guo @ 2015-07-09 2:36 UTC (permalink / raw) To: Frank.Li Cc: linux-arm-kernel, shawn.guo, linus.walleij, lznuaa, linux-gpio, robh+dt, devicetree On Wed, Jun 17, 2015 at 11:39:24PM +0800, Frank.Li@freescale.com wrote: > From: Frank Li <Frank.Li@freescale.com> > > This part just add necessary change to boot imx6ul. > Update clock and pinctrl for imx6ul > > Signed-off-by: Frank Li <Frank.Li@freescale.com> > Signed-off-by: Frank Li <Frank.Li@freescale.com> Double SoB. Drop one. > --- > .../devicetree/bindings/clock/imx6ul-clock.txt | 13 ++++++++ > .../bindings/pinctrl/fsl,imx6ul-pinctrl.txt | 36 ++++++++++++++++++++++ > 2 files changed, 49 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/imx6ul-clock.txt > create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx6ul-pinctrl.txt > > diff --git a/Documentation/devicetree/bindings/clock/imx6ul-clock.txt b/Documentation/devicetree/bindings/clock/imx6ul-clock.txt > new file mode 100644 > index 0000000..3ff362e > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/imx6ul-clock.txt > @@ -0,0 +1,13 @@ > +* Clock bindings for Freescale i.MX6 UltraLite > + > +Required properties: > +- compatible: Should be "fsl,imx6ul-ccm" > +- reg: Address and length of the register set > +- #clock-cells: Should be <1> > +- clocks: list of clock specifiers, must contain an entry for each required > + entry in clock-names > +- clock-names: should include entries "ckil", "osc", "ipp_di0" and "ipp_di1" > + > +The clock consumer should specify the desired clock by having the clock > +ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6ul-clock.h > +for the full list of i.MX6 UltraLite clock IDs. ^^ Double spaces. Drop one. Shawn > diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx6ul-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx6ul-pinctrl.txt > new file mode 100644 > index 0000000..a81bbf3 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx6ul-pinctrl.txt > @@ -0,0 +1,36 @@ > +* Freescale i.MX6 UltraLite IOMUX Controller > + > +Please refer to fsl,imx-pinctrl.txt in this directory for common binding part > +and usage. > + > +Required properties: > +- compatible: "fsl,imx6ul-iomuxc" > +- fsl,pins: each entry consists of 6 integers and represents the mux and config > + setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val > + input_val> are specified using a PIN_FUNC_ID macro, which can be found in > + imx6ul-pinfunc.h under device tree source folder. The last integer CONFIG is > + the pad setting value like pull-up on this pin. Please refer to i.MX6 UltraLite > + Reference Manual for detailed CONFIG settings. > + > +CONFIG bits definition: > +PAD_CTL_HYS (1 << 16) > +PAD_CTL_PUS_100K_DOWN (0 << 14) > +PAD_CTL_PUS_47K_UP (1 << 14) > +PAD_CTL_PUS_100K_UP (2 << 14) > +PAD_CTL_PUS_22K_UP (3 << 14) > +PAD_CTL_PUE (1 << 13) > +PAD_CTL_PKE (1 << 12) > +PAD_CTL_ODE (1 << 11) > +PAD_CTL_SPEED_LOW (0 << 6) > +PAD_CTL_SPEED_MED (1 << 6) > +PAD_CTL_SPEED_HIGH (3 << 6) > +PAD_CTL_DSE_DISABLE (0 << 3) > +PAD_CTL_DSE_260ohm (1 << 3) > +PAD_CTL_DSE_130ohm (2 << 3) > +PAD_CTL_DSE_87ohm (3 << 3) > +PAD_CTL_DSE_65ohm (4 << 3) > +PAD_CTL_DSE_52ohm (5 << 3) > +PAD_CTL_DSE_43ohm (6 << 3) > +PAD_CTL_DSE_37ohm (7 << 3) > +PAD_CTL_SRE_FAST (1 << 0) > +PAD_CTL_SRE_SLOW (0 << 0) > -- > 1.9.1 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel > ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 4/8] ARM: pinctrl: imx: add i.mx6ul pinctrl driver 2015-06-17 15:39 [PATCH 0/8] add basic support for i.mx6 ul chip Frank.Li-KZfg59tc24xl57MIdRCFDg 2015-06-17 15:39 ` [PATCH 1/8] ARM: imx: add i.mx6ul msl support Frank.Li 2015-06-17 15:39 ` [PATCH 3/8] Document: dt: binding: imx: update document for imx6ul support Frank.Li @ 2015-06-17 15:39 ` Frank.Li 2015-07-09 2:38 ` Shawn Guo [not found] ` <1434555569-8237-1-git-send-email-Frank.Li-KZfg59tc24xl57MIdRCFDg@public.gmane.org> 3 siblings, 1 reply; 16+ messages in thread From: Frank.Li @ 2015-06-17 15:39 UTC (permalink / raw) To: linux-arm-kernel, shawn.guo, shawnguo, linus.walleij, lznuaa Cc: linux-gpio, robh+dt, devicetree, Frank Li, Anson Huang From: Frank Li <Frank.Li@freescale.com> Add i.MX6UL pinctrl driver support. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Frank Li <Frank.Li@freescale.com> --- drivers/pinctrl/freescale/Kconfig | 7 + drivers/pinctrl/freescale/Makefile | 1 + drivers/pinctrl/freescale/pinctrl-imx6ul.c | 323 +++++++++++++++++++++++++++++ 3 files changed, 331 insertions(+) create mode 100644 drivers/pinctrl/freescale/pinctrl-imx6ul.c diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig index 12ef544..debe121 100644 --- a/drivers/pinctrl/freescale/Kconfig +++ b/drivers/pinctrl/freescale/Kconfig @@ -87,6 +87,13 @@ config PINCTRL_IMX6SX help Say Y here to enable the imx6sx pinctrl driver +config PINCTRL_IMX6UL + bool "IMX6UL pinctrl driver" + depends on SOC_IMX6UL + select PINCTRL_IMX + help + Say Y here to enable the imx6ul pinctrl driver + config PINCTRL_IMX7D bool "IMX7D pinctrl driver" depends on SOC_IMX7D diff --git a/drivers/pinctrl/freescale/Makefile b/drivers/pinctrl/freescale/Makefile index 343cb43..d44c9e2 100644 --- a/drivers/pinctrl/freescale/Makefile +++ b/drivers/pinctrl/freescale/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6dl.o obj-$(CONFIG_PINCTRL_IMX6SL) += pinctrl-imx6sl.o obj-$(CONFIG_PINCTRL_IMX6SX) += pinctrl-imx6sx.o +obj-$(CONFIG_PINCTRL_IMX6UL) += pinctrl-imx6ul.o obj-$(CONFIG_PINCTRL_IMX7D) += pinctrl-imx7d.o obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o diff --git a/drivers/pinctrl/freescale/pinctrl-imx6ul.c b/drivers/pinctrl/freescale/pinctrl-imx6ul.c new file mode 100644 index 0000000..b182be7 --- /dev/null +++ b/drivers/pinctrl/freescale/pinctrl-imx6ul.c @@ -0,0 +1,323 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/err.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-imx.h" + +enum imx6ul_pads { + MX6UL_PAD_RESERVE0 = 0, + MX6UL_PAD_RESERVE1 = 1, + MX6UL_PAD_RESERVE2 = 2, + MX6UL_PAD_RESERVE3 = 3, + MX6UL_PAD_RESERVE4 = 4, + MX6UL_PAD_RESERVE5 = 5, + MX6UL_PAD_RESERVE6 = 6, + MX6UL_PAD_RESERVE7 = 7, + MX6UL_PAD_RESERVE8 = 8, + MX6UL_PAD_RESERVE9 = 9, + MX6UL_PAD_RESERVE10 = 10, + MX6UL_PAD_SNVS_TAMPER4 = 11, + MX6UL_PAD_RESERVE12 = 12, + MX6UL_PAD_RESERVE13 = 13, + MX6UL_PAD_RESERVE14 = 14, + MX6UL_PAD_RESERVE15 = 15, + MX6UL_PAD_RESERVE16 = 16, + MX6UL_PAD_JTAG_MOD = 17, + MX6UL_PAD_JTAG_TMS = 18, + MX6UL_PAD_JTAG_TDO = 19, + MX6UL_PAD_JTAG_TDI = 20, + MX6UL_PAD_JTAG_TCK = 21, + MX6UL_PAD_JTAG_TRST_B = 22, + MX6UL_PAD_GPIO1_IO00 = 23, + MX6UL_PAD_GPIO1_IO01 = 24, + MX6UL_PAD_GPIO1_IO02 = 25, + MX6UL_PAD_GPIO1_IO03 = 26, + MX6UL_PAD_GPIO1_IO04 = 27, + MX6UL_PAD_GPIO1_IO05 = 28, + MX6UL_PAD_GPIO1_IO06 = 29, + MX6UL_PAD_GPIO1_IO07 = 30, + MX6UL_PAD_GPIO1_IO08 = 31, + MX6UL_PAD_GPIO1_IO09 = 32, + MX6UL_PAD_UART1_TX_DATA = 33, + MX6UL_PAD_UART1_RX_DATA = 34, + MX6UL_PAD_UART1_CTS_B = 35, + MX6UL_PAD_UART1_RTS_B = 36, + MX6UL_PAD_UART2_TX_DATA = 37, + MX6UL_PAD_UART2_RX_DATA = 38, + MX6UL_PAD_UART2_CTS_B = 39, + MX6UL_PAD_UART2_RTS_B = 40, + MX6UL_PAD_UART3_TX_DATA = 41, + MX6UL_PAD_UART3_RX_DATA = 42, + MX6UL_PAD_UART3_CTS_B = 43, + MX6UL_PAD_UART3_RTS_B = 44, + MX6UL_PAD_UART4_TX_DATA = 45, + MX6UL_PAD_UART4_RX_DATA = 46, + MX6UL_PAD_UART5_TX_DATA = 47, + MX6UL_PAD_UART5_RX_DATA = 48, + MX6UL_PAD_ENET1_RX_DATA0 = 49, + MX6UL_PAD_ENET1_RX_DATA1 = 50, + MX6UL_PAD_ENET1_RX_EN = 51, + MX6UL_PAD_ENET1_TX_DATA0 = 52, + MX6UL_PAD_ENET1_TX_DATA1 = 53, + MX6UL_PAD_ENET1_TX_EN = 54, + MX6UL_PAD_ENET1_TX_CLK = 55, + MX6UL_PAD_ENET1_RX_ER = 56, + MX6UL_PAD_ENET2_RX_DATA0 = 57, + MX6UL_PAD_ENET2_RX_DATA1 = 58, + MX6UL_PAD_ENET2_RX_EN = 59, + MX6UL_PAD_ENET2_TX_DATA0 = 60, + MX6UL_PAD_ENET2_TX_DATA1 = 61, + MX6UL_PAD_ENET2_TX_EN = 62, + MX6UL_PAD_ENET2_TX_CLK = 63, + MX6UL_PAD_ENET2_RX_ER = 64, + MX6UL_PAD_LCD_CLK = 65, + MX6UL_PAD_LCD_ENABLE = 66, + MX6UL_PAD_LCD_HSYNC = 67, + MX6UL_PAD_LCD_VSYNC = 68, + MX6UL_PAD_LCD_RESET = 69, + MX6UL_PAD_LCD_DATA00 = 70, + MX6UL_PAD_LCD_DATA01 = 71, + MX6UL_PAD_LCD_DATA02 = 72, + MX6UL_PAD_LCD_DATA03 = 73, + MX6UL_PAD_LCD_DATA04 = 74, + MX6UL_PAD_LCD_DATA05 = 75, + MX6UL_PAD_LCD_DATA06 = 76, + MX6UL_PAD_LCD_DATA07 = 77, + MX6UL_PAD_LCD_DATA08 = 78, + MX6UL_PAD_LCD_DATA09 = 79, + MX6UL_PAD_LCD_DATA10 = 80, + MX6UL_PAD_LCD_DATA11 = 81, + MX6UL_PAD_LCD_DATA12 = 82, + MX6UL_PAD_LCD_DATA13 = 83, + MX6UL_PAD_LCD_DATA14 = 84, + MX6UL_PAD_LCD_DATA15 = 85, + MX6UL_PAD_LCD_DATA16 = 86, + MX6UL_PAD_LCD_DATA17 = 87, + MX6UL_PAD_LCD_DATA18 = 88, + MX6UL_PAD_LCD_DATA19 = 89, + MX6UL_PAD_LCD_DATA20 = 90, + MX6UL_PAD_LCD_DATA21 = 91, + MX6UL_PAD_LCD_DATA22 = 92, + MX6UL_PAD_LCD_DATA23 = 93, + MX6UL_PAD_NAND_RE_B = 94, + MX6UL_PAD_NAND_WE_B = 95, + MX6UL_PAD_NAND_DATA00 = 96, + MX6UL_PAD_NAND_DATA01 = 97, + MX6UL_PAD_NAND_DATA02 = 98, + MX6UL_PAD_NAND_DATA03 = 99, + MX6UL_PAD_NAND_DATA04 = 100, + MX6UL_PAD_NAND_DATA05 = 101, + MX6UL_PAD_NAND_DATA06 = 102, + MX6UL_PAD_NAND_DATA07 = 103, + MX6UL_PAD_NAND_ALE = 104, + MX6UL_PAD_NAND_WP_B = 105, + MX6UL_PAD_NAND_READY_B = 106, + MX6UL_PAD_NAND_CE0_B = 107, + MX6UL_PAD_NAND_CE1_B = 108, + MX6UL_PAD_NAND_CLE = 109, + MX6UL_PAD_NAND_DQS = 110, + MX6UL_PAD_SD1_CMD = 111, + MX6UL_PAD_SD1_CLK = 112, + MX6UL_PAD_SD1_DATA0 = 113, + MX6UL_PAD_SD1_DATA1 = 114, + MX6UL_PAD_SD1_DATA2 = 115, + MX6UL_PAD_SD1_DATA3 = 116, + MX6UL_PAD_CSI_MCLK = 117, + MX6UL_PAD_CSI_PIXCLK = 118, + MX6UL_PAD_CSI_VSYNC = 119, + MX6UL_PAD_CSI_HSYNC = 120, + MX6UL_PAD_CSI_DATA00 = 121, + MX6UL_PAD_CSI_DATA01 = 122, + MX6UL_PAD_CSI_DATA02 = 123, + MX6UL_PAD_CSI_DATA03 = 124, + MX6UL_PAD_CSI_DATA04 = 125, + MX6UL_PAD_CSI_DATA05 = 126, + MX6UL_PAD_CSI_DATA06 = 127, + MX6UL_PAD_CSI_DATA07 = 128, +}; + +/* Pad names for the pinmux subsystem */ +static const struct pinctrl_pin_desc imx6ul_pinctrl_pads[] = { + IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE0), + IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE1), + IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE2), + IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE3), + IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE4), + IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE5), + IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE6), + IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE7), + IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE8), + IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE9), + IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE10), + IMX_PINCTRL_PIN(MX6UL_PAD_SNVS_TAMPER4), + IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE12), + IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE13), + IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE14), + IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE15), + IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE16), + IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_MOD), + IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TMS), + IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TDO), + IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TDI), + IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TCK), + IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TRST_B), + IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO00), + IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO01), + IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO02), + IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO03), + IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO04), + IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO05), + IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO06), + IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO07), + IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO08), + IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO09), + IMX_PINCTRL_PIN(MX6UL_PAD_UART1_TX_DATA), + IMX_PINCTRL_PIN(MX6UL_PAD_UART1_RX_DATA), + IMX_PINCTRL_PIN(MX6UL_PAD_UART1_CTS_B), + IMX_PINCTRL_PIN(MX6UL_PAD_UART1_RTS_B), + IMX_PINCTRL_PIN(MX6UL_PAD_UART2_TX_DATA), + IMX_PINCTRL_PIN(MX6UL_PAD_UART2_RX_DATA), + IMX_PINCTRL_PIN(MX6UL_PAD_UART2_CTS_B), + IMX_PINCTRL_PIN(MX6UL_PAD_UART2_RTS_B), + IMX_PINCTRL_PIN(MX6UL_PAD_UART3_TX_DATA), + IMX_PINCTRL_PIN(MX6UL_PAD_UART3_RX_DATA), + IMX_PINCTRL_PIN(MX6UL_PAD_UART3_CTS_B), + IMX_PINCTRL_PIN(MX6UL_PAD_UART3_RTS_B), + IMX_PINCTRL_PIN(MX6UL_PAD_UART4_TX_DATA), + IMX_PINCTRL_PIN(MX6UL_PAD_UART4_RX_DATA), + IMX_PINCTRL_PIN(MX6UL_PAD_UART5_TX_DATA), + IMX_PINCTRL_PIN(MX6UL_PAD_UART5_RX_DATA), + IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_RX_DATA0), + IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_RX_DATA1), + IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_RX_EN), + IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_TX_DATA0), + IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_TX_DATA1), + IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_TX_EN), + IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_TX_CLK), + IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_RX_ER), + IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_RX_DATA0), + IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_RX_DATA1), + IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_RX_EN), + IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_TX_DATA0), + IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_TX_DATA1), + IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_TX_EN), + IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_TX_CLK), + IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_RX_ER), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_CLK), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_ENABLE), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_HSYNC), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_VSYNC), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_RESET), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA00), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA01), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA02), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA03), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA04), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA05), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA06), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA07), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA08), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA09), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA10), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA11), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA12), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA13), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA14), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA15), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA16), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA17), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA18), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA19), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA20), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA21), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA22), + IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA23), + IMX_PINCTRL_PIN(MX6UL_PAD_NAND_RE_B), + IMX_PINCTRL_PIN(MX6UL_PAD_NAND_WE_B), + IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA00), + IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA01), + IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA02), + IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA03), + IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA04), + IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA05), + IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA06), + IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA07), + IMX_PINCTRL_PIN(MX6UL_PAD_NAND_ALE), + IMX_PINCTRL_PIN(MX6UL_PAD_NAND_WP_B), + IMX_PINCTRL_PIN(MX6UL_PAD_NAND_READY_B), + IMX_PINCTRL_PIN(MX6UL_PAD_NAND_CE0_B), + IMX_PINCTRL_PIN(MX6UL_PAD_NAND_CE1_B), + IMX_PINCTRL_PIN(MX6UL_PAD_NAND_CLE), + IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DQS), + IMX_PINCTRL_PIN(MX6UL_PAD_SD1_CMD), + IMX_PINCTRL_PIN(MX6UL_PAD_SD1_CLK), + IMX_PINCTRL_PIN(MX6UL_PAD_SD1_DATA0), + IMX_PINCTRL_PIN(MX6UL_PAD_SD1_DATA1), + IMX_PINCTRL_PIN(MX6UL_PAD_SD1_DATA2), + IMX_PINCTRL_PIN(MX6UL_PAD_SD1_DATA3), + IMX_PINCTRL_PIN(MX6UL_PAD_CSI_MCLK), + IMX_PINCTRL_PIN(MX6UL_PAD_CSI_PIXCLK), + IMX_PINCTRL_PIN(MX6UL_PAD_CSI_VSYNC), + IMX_PINCTRL_PIN(MX6UL_PAD_CSI_HSYNC), + IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA00), + IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA01), + IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA02), + IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA03), + IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA04), + IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA05), + IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA06), + IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA07), +}; + +static struct imx_pinctrl_soc_info imx6ul_pinctrl_info = { + .pins = imx6ul_pinctrl_pads, + .npins = ARRAY_SIZE(imx6ul_pinctrl_pads), +}; + +static struct of_device_id imx6ul_pinctrl_of_match[] = { + { .compatible = "fsl,imx6ul-iomuxc", }, + { /* sentinel */ } +}; + +static int imx6ul_pinctrl_probe(struct platform_device *pdev) +{ + return imx_pinctrl_probe(pdev, &imx6ul_pinctrl_info); +} + +static struct platform_driver imx6ul_pinctrl_driver = { + .driver = { + .name = "imx6ul-pinctrl", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(imx6ul_pinctrl_of_match), + }, + .probe = imx6ul_pinctrl_probe, + .remove = imx_pinctrl_remove, +}; + +static int __init imx6ul_pinctrl_init(void) +{ + return platform_driver_register(&imx6ul_pinctrl_driver); +} +arch_initcall(imx6ul_pinctrl_init); + +static void __exit imx6ul_pinctrl_exit(void) +{ + platform_driver_unregister(&imx6ul_pinctrl_driver); +} +module_exit(imx6ul_pinctrl_exit); + +MODULE_AUTHOR("Anson Huang <Anson.Huang@freescale.com>"); +MODULE_DESCRIPTION("Freescale imx6ul pinctrl driver"); +MODULE_LICENSE("GPL v2"); -- 1.9.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH 4/8] ARM: pinctrl: imx: add i.mx6ul pinctrl driver 2015-06-17 15:39 ` [PATCH 4/8] ARM: pinctrl: imx: add i.mx6ul pinctrl driver Frank.Li @ 2015-07-09 2:38 ` Shawn Guo 0 siblings, 0 replies; 16+ messages in thread From: Shawn Guo @ 2015-07-09 2:38 UTC (permalink / raw) To: Frank.Li Cc: linux-arm-kernel, shawn.guo, linus.walleij, lznuaa, linux-gpio, Anson Huang, robh+dt, devicetree On Wed, Jun 17, 2015 at 11:39:25PM +0800, Frank.Li@freescale.com wrote: > From: Frank Li <Frank.Li@freescale.com> > > Add i.MX6UL pinctrl driver support. > > Signed-off-by: Anson Huang <b20788@freescale.com> > Signed-off-by: Frank Li <Frank.Li@freescale.com> Acked-by: Shawn Guo <shawnguo@kernel.org> ^ permalink raw reply [flat|nested] 16+ messages in thread
[parent not found: <1434555569-8237-1-git-send-email-Frank.Li-KZfg59tc24xl57MIdRCFDg@public.gmane.org>]
* [PATCH 2/8] ARM: imx: add imx6ul clk tree support [not found] ` <1434555569-8237-1-git-send-email-Frank.Li-KZfg59tc24xl57MIdRCFDg@public.gmane.org> @ 2015-06-17 15:39 ` Frank.Li-KZfg59tc24xl57MIdRCFDg 2015-06-18 5:40 ` Sascha Hauer 2015-06-17 15:39 ` [PATCH 5/8] ARM: dts: add i.mx6ul pin function include file Frank.Li-KZfg59tc24xl57MIdRCFDg ` (3 subsequent siblings) 4 siblings, 1 reply; 16+ messages in thread From: Frank.Li-KZfg59tc24xl57MIdRCFDg @ 2015-06-17 15:39 UTC (permalink / raw) To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, shawn.guo-QSEj5FYQhm4dnm+yROfE0A, shawnguo-DgEjT+Ai2ygdnm+yROfE0A, linus.walleij-QSEj5FYQhm4dnm+yROfE0A, lznuaa-Re5JQEeQqe8AvxtiuMwx3w Cc: linux-gpio-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A, devicetree-u79uwXL29TY76Z2rM5mHXA, Frank Li, Anson Huang, Bai Ping, Fugang Duan From: Frank Li <Frank.Li-KZfg59tc24xl57MIdRCFDg@public.gmane.org> Add imx6ul support Signed-off-by: Anson Huang <b20788-KZfg59tc24xl57MIdRCFDg@public.gmane.org> Signed-off-by: Bai Ping <b51503-KZfg59tc24xl57MIdRCFDg@public.gmane.org> Signed-off-by: Fugang Duan <B38611-KZfg59tc24xl57MIdRCFDg@public.gmane.org> Signed-off-by: Frank Li <Frank.Li-KZfg59tc24xl57MIdRCFDg@public.gmane.org> --- drivers/clk/imx/Makefile | 1 + drivers/clk/imx/clk-imx6ul.c | 436 +++++++++++++++++++++++++++++++ include/dt-bindings/clock/imx6ul-clock.h | 240 +++++++++++++++++ 3 files changed, 677 insertions(+) create mode 100644 drivers/clk/imx/clk-imx6ul.c create mode 100644 include/dt-bindings/clock/imx6ul-clock.h diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index 75fae16..1ada68a 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -22,5 +22,6 @@ obj-$(CONFIG_SOC_IMX5) += clk-imx51-imx53.o obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o obj-$(CONFIG_SOC_IMX6SX) += clk-imx6sx.o +obj-$(CONFIG_SOC_IMX6UL) += clk-imx6ul.o obj-$(CONFIG_SOC_IMX7D) += clk-imx7d.o obj-$(CONFIG_SOC_VF610) += clk-vf610.o diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c new file mode 100644 index 0000000..2137d5e --- /dev/null +++ b/drivers/clk/imx/clk-imx6ul.c @@ -0,0 +1,436 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include <dt-bindings/clock/imx6ul-clock.h> +#include <linux/clk.h> +#include <linux/clkdev.h> +#include <linux/err.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> +#include <linux/types.h> + +#include "clk.h" + +#define BM_CCM_CCDR_MMDC_CH0_MASK (0x2 << 16) +#define CCDR 0x4 + +static const char *pll_bypass_src_sels[] = { "osc", "dummy", }; +static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", }; +static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", }; +static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", }; +static const char *pll4_bypass_sels[] = { "pll4", "pll4_bypass_src", }; +static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", }; +static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", }; +static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", }; +static const char *ca7_secondary_sels[] = { "pll2_pfd2_396m", "pll2_bus", }; +static const char *step_sels[] = { "osc", "ca7_secondary_sel", }; +static const char *pll1_sw_sels[] = { "pll1_sys", "step", }; +static const char *axi_alt_sels[] = { "pll2_pfd2_396m", "pll3_pfd1_540m", }; +static const char *axi_sels[] = {"periph", "axi_alt_sel", }; +static const char *periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", }; +static const char *periph2_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll4_audio_div", }; +static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", }; +static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "osc", }; +static const char *periph_sels[] = { "periph_pre", "periph_clk2", }; +static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", }; +static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", }; +static const char *bch_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", }; +static const char *gpmi_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", }; +static const char *eim_slow_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll3_pfd0_720m", }; +static const char *spdif_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll5_video_div", "pll3_usb_otg", }; +static const char *sai_sels[] = { "pll3_pfd2_508m", "pll5_video_div", "pll4_audio_div", }; +static const char *lcdif_pre_sels[] = { "pll2_bus", "pll3_pfd3_454m", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd1_594m", "pll3_pfd1_540m", }; +static const char *sim_pre_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd2_508m", }; +static const char *ldb_di0_sels[] = { "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll2_pfd3_594m", "pll2_pfd1_594m", "pll3_pfd3_454m", }; +static const char *ldb_di0_div_sels[] = { "ldb_di0_div_3_5", "ldb_di0_div_7", }; +static const char *ldb_di1_div_sels[] = { "ldb_di1_div_3_5", "ldb_di1_div_7", }; +static const char *qspi1_sels[] = { "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll2_bus", "pll3_pfd3_454m", "pll3_pfd2_508m", }; +static const char *enfc_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", "pll3_pfd3_454m", "dummy", "dummy", "dummy", }; +static const char *can_sels[] = { "pll3_60m", "osc", "pll3_80m", "dummy", }; +static const char *ecspi_sels[] = { "pll3_60m", "osc", }; +static const char *uart_sels[] = { "pll3_80m", "osc", }; +static const char *perclk_sels[] = { "ipg", "osc", }; +static const char *lcdif_sels[] = { "lcdif_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", }; +static const char *csi_sels[] = { "osc", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", }; +static const char *sim_sels[] = { "sim_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", }; + +static struct clk *clks[IMX6UL_CLK_END]; +static struct clk_onecell_data clk_data; + +static int const clks_init_on[] __initconst = { + IMX6UL_CLK_AIPSTZ1, IMX6UL_CLK_AIPSTZ2, IMX6UL_CLK_AIPSTZ3, + IMX6UL_CLK_AXI, IMX6UL_CLK_ARM, IMX6UL_CLK_ROM, + IMX6UL_CLK_MMDC_P0_FAST, IMX6UL_CLK_MMDC_P0_IPG, +}; + +static struct clk_div_table clk_enet_ref_table[] = { + { .val = 0, .div = 20, }, + { .val = 1, .div = 10, }, + { .val = 2, .div = 5, }, + { .val = 3, .div = 4, }, + { } +}; + +static struct clk_div_table post_div_table[] = { + { .val = 2, .div = 1, }, + { .val = 1, .div = 2, }, + { .val = 0, .div = 4, }, + { } +}; + +static struct clk_div_table video_div_table[] = { + { .val = 0, .div = 1, }, + { .val = 1, .div = 2, }, + { .val = 2, .div = 1, }, + { .val = 3, .div = 4, }, + { } +}; + +static u32 share_count_asrc; +static u32 share_count_audio; +static u32 share_count_sai1; +static u32 share_count_sai2; +static u32 share_count_sai3; + +static void __init imx6ul_clocks_init(struct device_node *ccm_node) +{ + struct device_node *np; + void __iomem *base; + int i; + + clks[IMX6UL_CLK_DUMMY] = imx_clk_fixed("dummy", 0); + + clks[IMX6UL_CLK_CKIL] = of_clk_get_by_name(ccm_node, "ckil"); + clks[IMX6UL_CLK_OSC] = of_clk_get_by_name(ccm_node, "osc"); + + /* ipp_di clock is external input */ + clks[IMX6UL_CLK_IPP_DI0] = of_clk_get_by_name(ccm_node, "ipp_di0"); + clks[IMX6UL_CLK_IPP_DI1] = of_clk_get_by_name(ccm_node, "ipp_di1"); + + np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-anatop"); + base = of_iomap(np, 0); + WARN_ON(!base); + + clks[IMX6UL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); + clks[IMX6UL_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); + clks[IMX6UL_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); + clks[IMX6UL_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); + clks[IMX6UL_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); + clks[IMX6UL_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); + clks[IMX6UL_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); + + clks[IMX6UL_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1", "pll1_bypass_src", base + 0x00, 0x7f); + clks[IMX6UL_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", base + 0x30, 0x1); + clks[IMX6UL_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3", "pll3_bypass_src", base + 0x10, 0x3); + clks[IMX6UL_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "pll4_bypass_src", base + 0x70, 0x7f); + clks[IMX6UL_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5", "pll5_bypass_src", base + 0xa0, 0x7f); + clks[IMX6UL_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "pll6_bypass_src", base + 0xe0, 0x3); + clks[IMX6UL_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7", "pll7_bypass_src", base + 0x20, 0x3); + + clks[IMX6UL_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT); + clks[IMX6UL_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT); + clks[IMX6UL_PLL3_BYPASS] = imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT); + clks[IMX6UL_PLL4_BYPASS] = imx_clk_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT); + clks[IMX6UL_PLL5_BYPASS] = imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT); + clks[IMX6UL_PLL6_BYPASS] = imx_clk_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT); + clks[IMX6UL_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT); + clks[IMX6UL_CLK_CSI_SEL] = imx_clk_mux_flags("csi_sel", base + 0x3c, 9, 2, csi_sels, ARRAY_SIZE(csi_sels), CLK_SET_RATE_PARENT); + + /* Do not bypass PLLs initially */ + clk_set_parent(clks[IMX6UL_PLL1_BYPASS], clks[IMX6UL_CLK_PLL1]); + clk_set_parent(clks[IMX6UL_PLL2_BYPASS], clks[IMX6UL_CLK_PLL2]); + clk_set_parent(clks[IMX6UL_PLL3_BYPASS], clks[IMX6UL_CLK_PLL3]); + clk_set_parent(clks[IMX6UL_PLL4_BYPASS], clks[IMX6UL_CLK_PLL4]); + clk_set_parent(clks[IMX6UL_PLL5_BYPASS], clks[IMX6UL_CLK_PLL5]); + clk_set_parent(clks[IMX6UL_PLL6_BYPASS], clks[IMX6UL_CLK_PLL6]); + clk_set_parent(clks[IMX6UL_PLL7_BYPASS], clks[IMX6UL_CLK_PLL7]); + + clks[IMX6UL_CLK_PLL1_SYS] = imx_clk_fixed_factor("pll1_sys", "pll1_bypass", 1, 1); + clks[IMX6UL_CLK_PLL2_BUS] = imx_clk_gate("pll2_bus", "pll2_bypass", base + 0x30, 13); + clks[IMX6UL_CLK_PLL3_USB_OTG] = imx_clk_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13); + clks[IMX6UL_CLK_PLL4_AUDIO] = imx_clk_gate("pll4_audio", "pll4_bypass", base + 0x70, 13); + clks[IMX6UL_CLK_PLL5_VIDEO] = imx_clk_gate("pll5_video", "pll5_bypass", base + 0xa0, 13); + clks[IMX6UL_CLK_PLL6_ENET] = imx_clk_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13); + clks[IMX6UL_CLK_PLL7_USB_HOST] = imx_clk_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13); + + /* + * Bit 20 is the reserved and read-only bit, we do this only for: + * - Do nothing for usbphy clk_enable/disable + * - Keep refcount when do usbphy clk_enable/disable, in that case, + * the clk framework many need to enable/disable usbphy's parent + */ + clks[IMX6UL_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20); + clks[IMX6UL_CLK_USBPHY2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20); + + /* + * usbphy*_gate needs to be on after system boots up, and software + * never needs to control it anymore. + */ + clks[IMX6UL_CLK_USBPHY1_GATE] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6); + clks[IMX6UL_CLK_USBPHY2_GATE] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6); + + /* name parent_name reg idx */ + clks[IMX6UL_CLK_PLL2_PFD0] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0); + clks[IMX6UL_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1); + clks[IMX6UL_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2); + clks[IMX6UL_CLK_PLL2_PFD3] = imx_clk_pfd("pll2_pfd3_594m", "pll2_bus", base + 0x100, 3); + clks[IMX6UL_CLK_PLL3_PFD0] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0); + clks[IMX6UL_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1); + clks[IMX6UL_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2); + clks[IMX6UL_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3); + + clks[IMX6UL_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, + base + 0xe0, 0, 2, 0, clk_enet_ref_table, &imx_ccm_lock); + clks[IMX6UL_CLK_ENET2_REF] = clk_register_divider_table(NULL, "enet2_ref", "pll6_enet", 0, + base + 0xe0, 2, 2, 0, clk_enet_ref_table, &imx_ccm_lock); + + clks[IMX6UL_CLK_ENET2_REF_125M] = imx_clk_gate("enet_ref_125m", "enet2_ref", base + 0xe0, 20); + clks[IMX6UL_CLK_ENET_PTP_REF] = imx_clk_fixed_factor("enet_ptp_ref", "pll6_enet", 1, 20); + clks[IMX6UL_CLK_ENET_PTP] = imx_clk_gate("enet_ptp", "enet_ptp_ref", base + 0xe0, 21); + + clks[IMX6UL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", + CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); + clks[IMX6UL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", + CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 15, 1, 0, &imx_ccm_lock); + clks[IMX6UL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", + CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); + clks[IMX6UL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", + CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); + + /* name parent_name mult div */ + clks[IMX6UL_CLK_PLL2_198M] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2); + clks[IMX6UL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6); + clks[IMX6UL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8); + clks[IMX6UL_CLK_GPT_3M] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8); + + np = ccm_node; + base = of_iomap(np, 0); + WARN_ON(!base); + + clks[IMX6UL_CA7_SECONDARY_SEL] = imx_clk_mux("ca7_secondary_sel", base + 0xc, 3, 1, ca7_secondary_sels, ARRAY_SIZE(ca7_secondary_sels)); + clks[IMX6UL_CLK_STEP] = imx_clk_mux("step", base + 0x0c, 8, 1, step_sels, ARRAY_SIZE(step_sels)); + clks[IMX6UL_CLK_PLL1_SW] = imx_clk_mux_flags("pll1_sw", base + 0x0c, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels), 0); + clks[IMX6UL_CLK_AXI_ALT_SEL] = imx_clk_mux("axi_alt_sel", base + 0x14, 7, 1, axi_alt_sels, ARRAY_SIZE(axi_alt_sels)); + clks[IMX6UL_CLK_AXI_SEL] = imx_clk_mux_flags("axi_sel", base + 0x14, 6, 1, axi_sels, ARRAY_SIZE(axi_sels), 0); + clks[IMX6UL_CLK_PERIPH_PRE] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); + clks[IMX6UL_CLK_PERIPH2_PRE] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph2_pre_sels, ARRAY_SIZE(periph2_pre_sels)); + clks[IMX6UL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); + clks[IMX6UL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels)); + clks[IMX6UL_CLK_EIM_SLOW_SEL] = imx_clk_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_slow_sels, ARRAY_SIZE(eim_slow_sels)); + clks[IMX6UL_CLK_GPMI_SEL] = imx_clk_mux("gpmi_sel", base + 0x1c, 19, 1, gpmi_sels, ARRAY_SIZE(gpmi_sels)); + clks[IMX6UL_CLK_BCH_SEL] = imx_clk_mux("bch_sel", base + 0x1c, 18, 1, bch_sels, ARRAY_SIZE(bch_sels)); + clks[IMX6UL_CLK_USDHC2_SEL] = imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); + clks[IMX6UL_CLK_USDHC1_SEL] = imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); + clks[IMX6UL_CLK_SAI3_SEL] = imx_clk_mux("sai3_sel", base + 0x1c, 14, 2, sai_sels, ARRAY_SIZE(sai_sels)); + clks[IMX6UL_CLK_SAI2_SEL] = imx_clk_mux("sai2_sel", base + 0x1c, 12, 2, sai_sels, ARRAY_SIZE(sai_sels)); + clks[IMX6UL_CLK_SAI1_SEL] = imx_clk_mux("sai1_sel", base + 0x1c, 10, 2, sai_sels, ARRAY_SIZE(sai_sels)); + clks[IMX6UL_CLK_QSPI1_SEL] = imx_clk_mux("qspi1_sel", base + 0x1c, 7, 3, qspi1_sels, ARRAY_SIZE(qspi1_sels)); + clks[IMX6UL_CLK_PERCLK_SEL] = imx_clk_mux("perclk_sel", base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels)); + clks[IMX6UL_CLK_CAN_SEL] = imx_clk_mux("can_sel", base + 0x20, 8, 2, can_sels, ARRAY_SIZE(can_sels)); + clks[IMX6UL_CLK_UART_SEL] = imx_clk_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels)); + clks[IMX6UL_CLK_ENFC_SEL] = imx_clk_mux("enfc_sel", base + 0x2c, 15, 3, enfc_sels, ARRAY_SIZE(enfc_sels)); + clks[IMX6UL_CLK_LDB_DI0_SEL] = imx_clk_mux("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di0_sels, ARRAY_SIZE(ldb_di0_sels)); + clks[IMX6UL_CLK_SPDIF_SEL] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, spdif_sels, ARRAY_SIZE(spdif_sels)); + clks[IMX6UL_CLK_SIM_PRE_SEL] = imx_clk_mux("sim_pre_sel", base + 0x34, 15, 3, sim_pre_sels, ARRAY_SIZE(sim_pre_sels)); + clks[IMX6UL_CLK_SIM_SEL] = imx_clk_mux("sim_sel", base + 0x34, 9, 3, sim_sels, ARRAY_SIZE(sim_sels)); + clks[IMX6UL_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels)); + clks[IMX6UL_CLK_LCDIF_PRE_SEL] = imx_clk_mux("lcdif_pre_sel", base + 0x38, 15, 3, lcdif_pre_sels, ARRAY_SIZE(lcdif_pre_sels)); + clks[IMX6UL_CLK_LCDIF_SEL] = imx_clk_mux("lcdif_sel", base + 0x38, 9, 3, lcdif_sels, ARRAY_SIZE(lcdif_sels)); + + clks[IMX6UL_CLK_LDB_DI0_DIV_SEL] = imx_clk_mux("ldb_di0", base + 0x20, 10, 1, ldb_di0_div_sels, ARRAY_SIZE(ldb_di0_div_sels)); + clks[IMX6UL_CLK_LDB_DI1_DIV_SEL] = imx_clk_mux("ldb_di1", base + 0x20, 11, 1, ldb_di1_div_sels, ARRAY_SIZE(ldb_di1_div_sels)); + + clks[IMX6UL_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7); + clks[IMX6UL_CLK_LDB_DI0_DIV_7] = imx_clk_fixed_factor("ldb_di0_div_7", "ldb_di0_sel", 1, 7); + clks[IMX6UL_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "qspi1_sel", 2, 7); + clks[IMX6UL_CLK_LDB_DI1_DIV_7] = imx_clk_fixed_factor("ldb_di1_div_7", "qspi1_sel", 1, 7); + + clks[IMX6UL_CLK_PERIPH] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels)); + clks[IMX6UL_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels)); + + clks[IMX6UL_CLK_PERIPH_CLK2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3); + clks[IMX6UL_CLK_PERIPH2_CLK2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3); + clks[IMX6UL_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2); + clks[IMX6UL_CLK_LCDIF_PODF] = imx_clk_divider("lcdif_podf", "lcdif_pred", base + 0x18, 23, 3); + clks[IMX6UL_CLK_QSPI1_PDOF] = imx_clk_divider("qspi1_podf", "qspi1_sel", base + 0x1c, 26, 3); + clks[IMX6UL_CLK_EIM_SLOW_PODF] = imx_clk_divider("eim_slow_podf", "eim_slow_sel", base + 0x1c, 23, 3); + clks[IMX6UL_CLK_PERCLK] = imx_clk_divider("perclk", "perclk_sel", base + 0x1c, 0, 6); + clks[IMX6UL_CLK_CAN_PODF] = imx_clk_divider("can_podf", "can_sel", base + 0x20, 2, 6); + clks[IMX6UL_CLK_GPMI_PODF] = imx_clk_divider("gpmi_podf", "gpmi_sel", base + 0x24, 22, 3); + clks[IMX6UL_CLK_BCH_PODF] = imx_clk_divider("bch_podf", "bch_sel", base + 0x24, 19, 3); + clks[IMX6UL_CLK_USDHC2_PODF] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3); + clks[IMX6UL_CLK_USDHC1_PODF] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3); + clks[IMX6UL_CLK_UART_PODF] = imx_clk_divider("uart_podf", "uart_sel", base + 0x24, 0, 6); + clks[IMX6UL_CLK_SAI3_PRED] = imx_clk_divider("sai3_pred", "sai3_sel", base + 0x28, 22, 3); + clks[IMX6UL_CLK_SAI3_PODF] = imx_clk_divider("sai3_podf", "sai3_pred", base + 0x28, 16, 6); + clks[IMX6UL_CLK_SAI1_PRED] = imx_clk_divider("sai1_pred", "sai1_sel", base + 0x28, 6, 3); + clks[IMX6UL_CLK_SAI1_PODF] = imx_clk_divider("sai1_podf", "sai1_pred", base + 0x28, 0, 6); + clks[IMX6UL_CLK_ENFC_PRED] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3); + clks[IMX6UL_CLK_ENFC_PODF] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6); + clks[IMX6UL_CLK_SAI2_PRED] = imx_clk_divider("sai2_pred", "sai2_sel", base + 0x2c, 6, 3); + clks[IMX6UL_CLK_SAI2_PODF] = imx_clk_divider("sai2_podf", "sai2_pred", base + 0x2c, 0, 6); + clks[IMX6UL_CLK_SPDIF_PRED] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3); + clks[IMX6UL_CLK_SPDIF_PODF] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3); + clks[IMX6UL_CLK_SIM_PODF] = imx_clk_divider("sim_podf", "sim_pre_sel", base + 0x34, 12, 3); + clks[IMX6UL_CLK_ECSPI_PODF] = imx_clk_divider("ecspi_podf", "ecspi_sel", base + 0x38, 19, 6); + clks[IMX6UL_CLK_LCDIF_PRED] = imx_clk_divider("lcdif_pred", "lcdif_pre_sel", base + 0x38, 12, 3); + clks[IMX6UL_CLK_CSI_PODF] = imx_clk_divider("csi_podf", "csi_sel", base + 0x3c, 11, 3); + + clks[IMX6UL_CLK_ARM] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16); + clks[IMX6UL_CLK_MMDC_PODF] = imx_clk_busy_divider("mmdc_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2); + clks[IMX6UL_CLK_AXI_PODF] = imx_clk_busy_divider("axi_podf", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0); + clks[IMX6UL_CLK_AHB] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1); + + /* CCGR0 */ + clks[IMX6UL_CLK_AIPSTZ1] = imx_clk_gate2("aips_tz1", "ahb", base + 0x68, 0); + clks[IMX6UL_CLK_AIPSTZ2] = imx_clk_gate2("aips_tz2", "ahb", base + 0x68, 2); + clks[IMX6UL_CLK_APBHDMA] = imx_clk_gate2("apbh_dma", "bch_podf", base + 0x68, 4); + clks[IMX6UL_CLK_ASRC_IPG] = imx_clk_gate2_shared("asrc_ipg", "ahb", base + 0x68, 6, &share_count_asrc); + clks[IMX6UL_CLK_ASRC_MEM] = imx_clk_gate2_shared("asrc_mem", "ahb", base + 0x68, 6, &share_count_asrc); + clks[IMX6UL_CLK_CAAM_MEM] = imx_clk_gate2("caam_mem", "ahb", base + 0x68, 8); + clks[IMX6UL_CLK_CAAM_ACLK] = imx_clk_gate2("caam_aclk", "ahb", base + 0x68, 10); + clks[IMX6UL_CLK_CAAM_IPG] = imx_clk_gate2("caam_ipg", "ipg", base + 0x68, 12); + clks[IMX6UL_CLK_CAN1_IPG] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14); + clks[IMX6UL_CLK_CAN1_SERIAL] = imx_clk_gate2("can1_serial", "can_podf", base + 0x68, 16); + clks[IMX6UL_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18); + clks[IMX6UL_CLK_CAN2_SERIAL] = imx_clk_gate2("can2_serial", "can_podf", base + 0x68, 20); + clks[IMX6UL_CLK_GPT2_BUS] = imx_clk_gate2("gpt_bus", "perclk", base + 0x68, 24); + clks[IMX6UL_CLK_GPT2_SERIAL] = imx_clk_gate2("gpt_serial", "perclk", base + 0x68, 26); + clks[IMX6UL_CLK_UART2_IPG] = imx_clk_gate2("uart2_ipg", "ipg", base + 0x68, 28); + clks[IMX6UL_CLK_UART2_SERIAL] = imx_clk_gate2("uart2_serial", "uart_podf", base + 0x68, 28); + clks[IMX6UL_CLK_AIPSTZ3] = imx_clk_gate2("aips_tz3", "ahb", base + 0x68, 30); + + /* CCGR1 */ + clks[IMX6UL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_podf", base + 0x6c, 0); + clks[IMX6UL_CLK_ECSPI2] = imx_clk_gate2("ecspi2", "ecspi_podf", base + 0x6c, 2); + clks[IMX6UL_CLK_ECSPI3] = imx_clk_gate2("ecspi3", "ecspi_podf", base + 0x6c, 4); + clks[IMX6UL_CLK_ECSPI4] = imx_clk_gate2("ecspi4", "ecspi_podf", base + 0x6c, 6); + clks[IMX6UL_CLK_ADC2] = imx_clk_gate2("adc2", "ipg", base + 0x6c, 8); + clks[IMX6UL_CLK_UART3_IPG] = imx_clk_gate2("uart3_ipg", "ipg", base + 0x6c, 10); + clks[IMX6UL_CLK_UART3_SERIAL] = imx_clk_gate2("uart3_serial", "uart_podf", base + 0x6c, 10); + clks[IMX6UL_CLK_EPIT1] = imx_clk_gate2("epit1", "perclk", base + 0x6c, 12); + clks[IMX6UL_CLK_EPIT2] = imx_clk_gate2("epit2", "perclk", base + 0x6c, 14); + clks[IMX6UL_CLK_ADC1] = imx_clk_gate2("adc1", "ipg", base + 0x6c, 16); + clks[IMX6UL_CLK_GPT1_BUS] = imx_clk_gate2("gpt1_bus", "perclk", base + 0x6c, 20); + clks[IMX6UL_CLK_GPT1_SERIAL] = imx_clk_gate2("gpt1_serial", "perclk", base + 0x6c, 22); + clks[IMX6UL_CLK_UART4_IPG] = imx_clk_gate2("uart4_ipg", "ipg", base + 0x6c, 24); + clks[IMX6UL_CLK_UART4_SERIAL] = imx_clk_gate2("uart4_serail", "uart_podf", base + 0x6c, 24); + + /* CCGR2 */ + clks[IMX6UL_CLK_CSI] = imx_clk_gate2("csi", "csi_podf", base + 0x70, 2); + clks[IMX6UL_CLK_I2C1] = imx_clk_gate2("i2c1", "perclk", base + 0x70, 6); + clks[IMX6UL_CLK_I2C2] = imx_clk_gate2("i2c2", "perclk", base + 0x70, 8); + clks[IMX6UL_CLK_I2C3] = imx_clk_gate2("i2c3", "perclk", base + 0x70, 10); + clks[IMX6UL_CLK_OCOTP] = imx_clk_gate2("ocotp", "ipg", base + 0x70, 12); + clks[IMX6UL_CLK_IOMUXC] = imx_clk_gate2("iomuxc", "lcdif_podf", base + 0x70, 14); + clks[IMX6UL_CLK_LCDIF_APB] = imx_clk_gate2("lcdif_apb", "axi", base + 0x70, 28); + clks[IMX6UL_CLK_PXP] = imx_clk_gate2("pxp", "axi", base + 0x70, 30); + + /* CCGR3 */ + clks[IMX6UL_CLK_UART5_IPG] = imx_clk_gate2("uart5_ipg", "ipg", base + 0x74, 2); + clks[IMX6UL_CLK_UART5_SERIAL] = imx_clk_gate2("uart5_serial", "uart_podf", base + 0x74, 2); + clks[IMX6UL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x74, 4); + clks[IMX6UL_CLK_ENET_AHB] = imx_clk_gate2("enet_ahb", "ahb", base + 0x74, 4); + clks[IMX6UL_CLK_UART6_IPG] = imx_clk_gate2("uart6_ipg", "ipg", base + 0x74, 6); + clks[IMX6UL_CLK_UART6_SERIAL] = imx_clk_gate2("uart6_serial", "uart_podf", base + 0x74, 6); + clks[IMX6UL_CLK_LCDIF_PIX] = imx_clk_gate2("lcdif_pix", "lcdif_podf", base + 0x74, 10); + clks[IMX6UL_CLK_QSPI] = imx_clk_gate2("qspi1", "qspi1_podf", base + 0x74, 14); + clks[IMX6UL_CLK_WDOG1] = imx_clk_gate2("wdog1", "ipg", base + 0x74, 16); + clks[IMX6UL_CLK_MMDC_P0_FAST] = imx_clk_gate("mmdc_p0_fast", "mmdc_podf", base + 0x74, 20); + clks[IMX6UL_CLK_MMDC_P0_IPG] = imx_clk_gate2("mmdc_p0_ipg", "ipg", base + 0x74, 24); + clks[IMX6UL_CLK_AXI] = imx_clk_gate("axi", "axi_podf", base + 0x74, 28); + + /* CCGR4 */ + clks[IMX6UL_CLK_PER_BCH] = imx_clk_gate2("per_bch", "bch_podf", base + 0x78, 12); + clks[IMX6UL_CLK_PWM1] = imx_clk_gate2("pwm1", "perclk", base + 0x78, 16); + clks[IMX6UL_CLK_PWM2] = imx_clk_gate2("pwm2", "perclk", base + 0x78, 18); + clks[IMX6UL_CLK_PWM3] = imx_clk_gate2("pwm3", "perclk", base + 0x78, 20); + clks[IMX6UL_CLK_PWM4] = imx_clk_gate2("pwm4", "perclk", base + 0x78, 22); + clks[IMX6UL_CLK_GPMI_BCH_APB] = imx_clk_gate2("gpmi_bch_apb", "bch_podf", base + 0x78, 24); + clks[IMX6UL_CLK_GPMI_BCH] = imx_clk_gate2("gpmi_bch", "gpmi_podf", base + 0x78, 26); + clks[IMX6UL_CLK_GPMI_IO] = imx_clk_gate2("gpmi_io", "enfc_podf", base + 0x78, 28); + clks[IMX6UL_CLK_GPMI_APB] = imx_clk_gate2("gpmi_apb", "bch_podf", base + 0x78, 30); + + /* CCGR5 */ + clks[IMX6UL_CLK_ROM] = imx_clk_gate2("rom", "ahb", base + 0x7c, 0); + clks[IMX6UL_CLK_SDMA] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6); + clks[IMX6UL_CLK_WDOG2] = imx_clk_gate2("wdog2", "ipg", base + 0x7c, 10); + clks[IMX6UL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); + clks[IMX6UL_CLK_SPDIF] = imx_clk_gate2_shared("spdif", "spdif_podf", base + 0x7c, 14, &share_count_audio); + clks[IMX6UL_CLK_SPDIF_GCLK] = imx_clk_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_audio); + clks[IMX6UL_CLK_SAI3] = imx_clk_gate2_shared("sai3", "sai3_podf", base + 0x7c, 22, &share_count_sai3); + clks[IMX6UL_CLK_SAI3_IPG] = imx_clk_gate2_shared("sai3_ipg", "ipg", base + 0x7c, 22, &share_count_sai3); + clks[IMX6UL_CLK_UART1_IPG] = imx_clk_gate2("uart1_ipg", "ipg", base + 0x7c, 24); + clks[IMX6UL_CLK_UART1_SERIAL] = imx_clk_gate2("uart1_serial", "uart_podf", base + 0x7c, 24); + clks[IMX6UL_CLK_UART7_IPG] = imx_clk_gate2("uart7_ipg", "ipg", base + 0x7c, 26); + clks[IMX6UL_CLK_UART7_SERIAL] = imx_clk_gate2("uart7_serial", "uart_podf", base + 0x7c, 26); + clks[IMX6UL_CLK_SAI1] = imx_clk_gate2_shared("sai1", "sai1_podf", base + 0x7c, 28, &share_count_sai1); + clks[IMX6UL_CLK_SAI1_IPG] = imx_clk_gate2_shared("sai1_ipg", "ipg", base + 0x7c, 28, &share_count_sai1); + clks[IMX6UL_CLK_SAI2] = imx_clk_gate2_shared("sai2", "sai2_podf", base + 0x7c, 30, &share_count_sai2); + clks[IMX6UL_CLK_SAI2_IPG] = imx_clk_gate2_shared("sai2_ipg", "ipg", base + 0x7c, 30, &share_count_sai2); + + /* CCGR6 */ + clks[IMX6UL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0); + clks[IMX6UL_CLK_USDHC1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2); + clks[IMX6UL_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4); + clks[IMX6UL_CLK_SIM1] = imx_clk_gate2("sim1", "sim_sel", base + 0x80, 6); + clks[IMX6UL_CLK_SIM2] = imx_clk_gate2("sim2", "sim_sel", base + 0x80, 8); + clks[IMX6UL_CLK_EIM] = imx_clk_gate2("eim", "eim_slow_podf", base + 0x80, 10); + clks[IMX6UL_CLK_PWM8] = imx_clk_gate2("pwm8", "perclk", base + 0x80, 16); + clks[IMX6UL_CLK_UART8_IPG] = imx_clk_gate2("uart8_ipg", "ipg", base + 0x80, 14); + clks[IMX6UL_CLK_UART8_SERIAL] = imx_clk_gate2("uart8_serial", "uart_podf", base + 0x80, 14); + clks[IMX6UL_CLK_WDOG3] = imx_clk_gate2("wdog3", "ipg", base + 0x80, 20); + clks[IMX6UL_CLK_I2C4] = imx_clk_gate2("i2c4", "perclk", base + 0x80, 24); + clks[IMX6UL_CLK_PWM5] = imx_clk_gate2("pwm5", "perclk", base + 0x80, 26); + clks[IMX6UL_CLK_PWM6] = imx_clk_gate2("pwm6", "perclk", base + 0x80, 28); + clks[IMX6UL_CLK_PWM7] = imx_clk_gate2("Pwm7", "perclk", base + 0x80, 30); + + /* mask handshake of mmdc */ + writel_relaxed(BM_CCM_CCDR_MMDC_CH0_MASK, base + CCDR); + + for (i = 0; i < ARRAY_SIZE(clks); i++) + if (IS_ERR(clks[i])) + pr_err("i.MX6UL clk %d: register failed with %ld\n", i, PTR_ERR(clks[i])); + + clk_data.clks = clks; + clk_data.clk_num = ARRAY_SIZE(clks); + of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); + + clk_register_clkdev(clks[IMX6UL_CLK_GPT1_BUS], "ipg", "imx-gpt.0"); + clk_register_clkdev(clks[IMX6UL_CLK_GPT1_SERIAL], "per", "imx-gpt.0"); + clk_register_clkdev(clks[IMX6UL_CLK_GPT_3M], "gpt_3m", "imx-gpt.0"); + + /* set perclk to from OSC */ + clk_set_parent(clks[IMX6UL_CLK_PERCLK_SEL], clks[IMX6UL_CLK_OSC]); + + clk_set_rate(clks[IMX6UL_CLK_ENET_REF], 50000000); + clk_set_rate(clks[IMX6UL_CLK_ENET2_REF], 50000000); + clk_set_rate(clks[IMX6UL_CLK_CSI], 24000000); + + /* keep all the clks on just for bringup */ + for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) + clk_prepare_enable(clks[clks_init_on[i]]); + + if (IS_ENABLED(CONFIG_USB_MXS_PHY)) { + clk_prepare_enable(clks[IMX6UL_CLK_USBPHY1_GATE]); + clk_prepare_enable(clks[IMX6UL_CLK_USBPHY2_GATE]); + } + + clk_set_parent(clks[IMX6UL_CLK_CAN_SEL], clks[IMX6UL_CLK_PLL3_60M]); + clk_set_parent(clks[IMX6UL_CLK_SIM_PRE_SEL], clks[IMX6UL_CLK_PLL3_USB_OTG]); + + clk_set_parent(clks[IMX6UL_CLK_ENFC_SEL], clks[IMX6UL_CLK_PLL2_PFD2]); +} + +CLK_OF_DECLARE(imx6ul, "fsl,imx6ul-ccm", imx6ul_clocks_init); diff --git a/include/dt-bindings/clock/imx6ul-clock.h b/include/dt-bindings/clock/imx6ul-clock.h new file mode 100644 index 0000000..c343894 --- /dev/null +++ b/include/dt-bindings/clock/imx6ul-clock.h @@ -0,0 +1,240 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX6UL_H +#define __DT_BINDINGS_CLOCK_IMX6UL_H + +#define IMX6UL_CLK_DUMMY 0 +#define IMX6UL_CLK_CKIL 1 +#define IMX6UL_CLK_CKIH 2 +#define IMX6UL_CLK_OSC 3 +#define IMX6UL_PLL1_BYPASS_SRC 4 +#define IMX6UL_PLL2_BYPASS_SRC 5 +#define IMX6UL_PLL3_BYPASS_SRC 6 +#define IMX6UL_PLL4_BYPASS_SRC 7 +#define IMX6UL_PLL5_BYPASS_SRC 8 +#define IMX6UL_PLL6_BYPASS_SRC 9 +#define IMX6UL_PLL7_BYPASS_SRC 10 +#define IMX6UL_CLK_PLL1 11 +#define IMX6UL_CLK_PLL2 12 +#define IMX6UL_CLK_PLL3 13 +#define IMX6UL_CLK_PLL4 14 +#define IMX6UL_CLK_PLL5 15 +#define IMX6UL_CLK_PLL6 16 +#define IMX6UL_CLK_PLL7 17 +#define IMX6UL_PLL1_BYPASS 18 +#define IMX6UL_PLL2_BYPASS 19 +#define IMX6UL_PLL3_BYPASS 20 +#define IMX6UL_PLL4_BYPASS 21 +#define IMX6UL_PLL5_BYPASS 22 +#define IMX6UL_PLL6_BYPASS 23 +#define IMX6UL_PLL7_BYPASS 24 +#define IMX6UL_CLK_PLL1_SYS 25 +#define IMX6UL_CLK_PLL2_BUS 26 +#define IMX6UL_CLK_PLL3_USB_OTG 27 +#define IMX6UL_CLK_PLL4_AUDIO 28 +#define IMX6UL_CLK_PLL5_VIDEO 29 +#define IMX6UL_CLK_PLL6_ENET 30 +#define IMX6UL_CLK_PLL7_USB_HOST 31 +#define IMX6UL_CLK_USBPHY1 32 +#define IMX6UL_CLK_USBPHY2 33 +#define IMX6UL_CLK_USBPHY1_GATE 34 +#define IMX6UL_CLK_USBPHY2_GATE 35 +#define IMX6UL_CLK_PLL2_PFD0 36 +#define IMX6UL_CLK_PLL2_PFD1 37 +#define IMX6UL_CLK_PLL2_PFD2 38 +#define IMX6UL_CLK_PLL2_PFD3 39 +#define IMX6UL_CLK_PLL3_PFD0 40 +#define IMX6UL_CLK_PLL3_PFD1 41 +#define IMX6UL_CLK_PLL3_PFD2 42 +#define IMX6UL_CLK_PLL3_PFD3 43 +#define IMX6UL_CLK_ENET_REF 44 +#define IMX6UL_CLK_ENET2_REF 45 +#define IMX6UL_CLK_ENET2_REF_125M 46 +#define IMX6UL_CLK_ENET_PTP_REF 47 +#define IMX6UL_CLK_ENET_PTP 48 +#define IMX6UL_CLK_PLL4_POST_DIV 49 +#define IMX6UL_CLK_PLL4_AUDIO_DIV 50 +#define IMX6UL_CLK_PLL5_POST_DIV 51 +#define IMX6UL_CLK_PLL5_VIDEO_DIV 52 +#define IMX6UL_CLK_PLL2_198M 53 +#define IMX6UL_CLK_PLL3_80M 54 +#define IMX6UL_CLK_PLL3_60M 55 +#define IMX6UL_CLK_STEP 56 +#define IMX6UL_CLK_PLL1_SW 57 +#define IMX6UL_CLK_AXI_ALT_SEL 58 +#define IMX6UL_CLK_AXI_SEL 59 +#define IMX6UL_CLK_PERIPH_PRE 60 +#define IMX6UL_CLK_PERIPH2_PRE 61 +#define IMX6UL_CLK_PERIPH_CLK2_SEL 62 +#define IMX6UL_CLK_PERIPH2_CLK2_SEL 63 +#define IMX6UL_CLK_USDHC1_SEL 64 +#define IMX6UL_CLK_USDHC2_SEL 65 +#define IMX6UL_CLK_BCH_SEL 66 +#define IMX6UL_CLK_GPMI_SEL 67 +#define IMX6UL_CLK_EIM_SLOW_SEL 68 +#define IMX6UL_CLK_SPDIF_SEL 69 +#define IMX6UL_CLK_SAI1_SEL 70 +#define IMX6UL_CLK_SAI2_SEL 71 +#define IMX6UL_CLK_SAI3_SEL 72 +#define IMX6UL_CLK_LCDIF_PRE_SEL 73 +#define IMX6UL_CLK_SIM_PRE_SEL 74 +#define IMX6UL_CLK_LDB_DI0_SEL 75 +#define IMX6UL_CLK_LDB_DI1_SEL 76 +#define IMX6UL_CLK_ENFC_SEL 77 +#define IMX6UL_CLK_CAN_SEL 78 +#define IMX6UL_CLK_ECSPI_SEL 79 +#define IMX6UL_CLK_UART_SEL 80 +#define IMX6UL_CLK_QSPI1_SEL 81 +#define IMX6UL_CLK_PERCLK_SEL 82 +#define IMX6UL_CLK_LCDIF_SEL 83 +#define IMX6UL_CLK_SIM_SEL 84 +#define IMX6UL_CLK_PERIPH 85 +#define IMX6UL_CLK_PERIPH2 86 +#define IMX6UL_CLK_LDB_DI0_DIV_3_5 87 +#define IMX6UL_CLK_LDB_DI0_DIV_7 88 +#define IMX6UL_CLK_LDB_DI1_DIV_3_5 89 +#define IMX6UL_CLK_LDB_DI1_DIV_7 90 +#define IMX6UL_CLK_LDB_DI0_DIV_SEL 91 +#define IMX6UL_CLK_LDB_DI1_DIV_SEL 92 +#define IMX6UL_CLK_ARM 93 +#define IMX6UL_CLK_PERIPH_CLK2 94 +#define IMX6UL_CLK_PERIPH2_CLK2 95 +#define IMX6UL_CLK_AHB 96 +#define IMX6UL_CLK_MMDC_PODF 97 +#define IMX6UL_CLK_AXI_PODF 98 +#define IMX6UL_CLK_PERCLK 99 +#define IMX6UL_CLK_IPG 100 +#define IMX6UL_CLK_USDHC1_PODF 101 +#define IMX6UL_CLK_USDHC2_PODF 102 +#define IMX6UL_CLK_BCH_PODF 103 +#define IMX6UL_CLK_GPMI_PODF 104 +#define IMX6UL_CLK_EIM_SLOW_PODF 105 +#define IMX6UL_CLK_SPDIF_PRED 106 +#define IMX6UL_CLK_SPDIF_PODF 107 +#define IMX6UL_CLK_SAI1_PRED 108 +#define IMX6UL_CLK_SAI1_PODF 109 +#define IMX6UL_CLK_SAI2_PRED 110 +#define IMX6UL_CLK_SAI2_PODF 111 +#define IMX6UL_CLK_SAI3_PRED 112 +#define IMX6UL_CLK_SAI3_PODF 113 +#define IMX6UL_CLK_LCDIF_PRED 114 +#define IMX6UL_CLK_LCDIF_PODF 115 +#define IMX6UL_CLK_SIM_PODF 116 +#define IMX6UL_CLK_QSPI1_PDOF 117 +#define IMX6UL_CLK_ENFC_PRED 118 +#define IMX6UL_CLK_ENFC_PODF 119 +#define IMX6UL_CLK_CAN_PODF 120 +#define IMX6UL_CLK_ECSPI_PODF 121 +#define IMX6UL_CLK_UART_PODF 122 +#define IMX6UL_CLK_ADC1 123 +#define IMX6UL_CLK_ADC2 124 +#define IMX6UL_CLK_AIPSTZ1 125 +#define IMX6UL_CLK_AIPSTZ2 126 +#define IMX6UL_CLK_AIPSTZ3 127 +#define IMX6UL_CLK_APBHDMA 128 +#define IMX6UL_CLK_ASRC_IPG 129 +#define IMX6UL_CLK_ASRC_MEM 130 +#define IMX6UL_CLK_GPMI_BCH_APB 131 +#define IMX6UL_CLK_GPMI_BCH 132 +#define IMX6UL_CLK_GPMI_IO 133 +#define IMX6UL_CLK_GPMI_APB 134 +#define IMX6UL_CLK_CAAM_MEM 135 +#define IMX6UL_CLK_CAAM_ACLK 136 +#define IMX6UL_CLK_CAAM_IPG 137 +#define IMX6UL_CLK_CSI 138 +#define IMX6UL_CLK_ECSPI1 139 +#define IMX6UL_CLK_ECSPI2 140 +#define IMX6UL_CLK_ECSPI3 141 +#define IMX6UL_CLK_ECSPI4 142 +#define IMX6UL_CLK_EIM 143 +#define IMX6UL_CLK_ENET 144 +#define IMX6UL_CLK_ENET_AHB 145 +#define IMX6UL_CLK_EPIT1 146 +#define IMX6UL_CLK_EPIT2 147 +#define IMX6UL_CLK_CAN1_IPG 148 +#define IMX6UL_CLK_CAN1_SERIAL 149 +#define IMX6UL_CLK_CAN2_IPG 150 +#define IMX6UL_CLK_CAN2_SERIAL 151 +#define IMX6UL_CLK_GPT1_BUS 152 +#define IMX6UL_CLK_GPT1_SERIAL 153 +#define IMX6UL_CLK_GPT2_BUS 154 +#define IMX6UL_CLK_GPT2_SERIAL 155 +#define IMX6UL_CLK_I2C1 156 +#define IMX6UL_CLK_I2C2 157 +#define IMX6UL_CLK_I2C3 158 +#define IMX6UL_CLK_I2C4 159 +#define IMX6UL_CLK_IOMUXC 160 +#define IMX6UL_CLK_LCDIF_APB 161 +#define IMX6UL_CLK_LCDIF_PIX 162 +#define IMX6UL_CLK_MMDC_P0_FAST 163 +#define IMX6UL_CLK_MMDC_P0_IPG 164 +#define IMX6UL_CLK_OCOTP 165 +#define IMX6UL_CLK_OCRAM 166 +#define IMX6UL_CLK_PWM1 167 +#define IMX6UL_CLK_PWM2 168 +#define IMX6UL_CLK_PWM3 169 +#define IMX6UL_CLK_PWM4 170 +#define IMX6UL_CLK_PWM5 171 +#define IMX6UL_CLK_PWM6 172 +#define IMX6UL_CLK_PWM7 173 +#define IMX6UL_CLK_PWM8 174 +#define IMX6UL_CLK_PXP 175 +#define IMX6UL_CLK_QSPI 176 +#define IMX6UL_CLK_ROM 177 +#define IMX6UL_CLK_SAI1 178 +#define IMX6UL_CLK_SAI1_IPG 179 +#define IMX6UL_CLK_SAI2 180 +#define IMX6UL_CLK_SAI2_IPG 181 +#define IMX6UL_CLK_SAI3 182 +#define IMX6UL_CLK_SAI3_IPG 183 +#define IMX6UL_CLK_SDMA 184 +#define IMX6UL_CLK_SIM 185 +#define IMX6UL_CLK_SIM_S 186 +#define IMX6UL_CLK_SPBA 187 +#define IMX6UL_CLK_SPDIF 188 +#define IMX6UL_CLK_UART1_IPG 189 +#define IMX6UL_CLK_UART1_SERIAL 190 +#define IMX6UL_CLK_UART2_IPG 191 +#define IMX6UL_CLK_UART2_SERIAL 192 +#define IMX6UL_CLK_UART3_IPG 193 +#define IMX6UL_CLK_UART3_SERIAL 194 +#define IMX6UL_CLK_UART4_IPG 195 +#define IMX6UL_CLK_UART4_SERIAL 196 +#define IMX6UL_CLK_UART5_IPG 197 +#define IMX6UL_CLK_UART5_SERIAL 198 +#define IMX6UL_CLK_UART6_IPG 199 +#define IMX6UL_CLK_UART6_SERIAL 200 +#define IMX6UL_CLK_UART7_IPG 201 +#define IMX6UL_CLK_UART7_SERIAL 202 +#define IMX6UL_CLK_UART8_IPG 203 +#define IMX6UL_CLK_UART8_SERIAL 204 +#define IMX6UL_CLK_USBOH3 205 +#define IMX6UL_CLK_USDHC1 206 +#define IMX6UL_CLK_USDHC2 207 +#define IMX6UL_CLK_WDOG1 208 +#define IMX6UL_CLK_WDOG2 209 +#define IMX6UL_CLK_WDOG3 210 +#define IMX6UL_CLK_LDB_DI0 211 +#define IMX6UL_CLK_AXI 212 +#define IMX6UL_CLK_SPDIF_GCLK 213 +#define IMX6UL_CLK_GPT_3M 214 +#define IMX6UL_CLK_SIM2 215 +#define IMX6UL_CLK_SIM1 216 +#define IMX6UL_CLK_IPP_DI0 217 +#define IMX6UL_CLK_IPP_DI1 218 +#define IMX6UL_CA7_SECONDARY_SEL 219 +#define IMX6UL_CLK_PER_BCH 220 +#define IMX6UL_CLK_CSI_SEL 221 +#define IMX6UL_CLK_CSI_PODF 222 +#define IMX6UL_CLK_PLL3_120M 223 + +#define IMX6UL_CLK_END 224 + +#endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */ -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH 2/8] ARM: imx: add imx6ul clk tree support 2015-06-17 15:39 ` [PATCH 2/8] ARM: imx: add imx6ul clk tree support Frank.Li-KZfg59tc24xl57MIdRCFDg @ 2015-06-18 5:40 ` Sascha Hauer 0 siblings, 0 replies; 16+ messages in thread From: Sascha Hauer @ 2015-06-18 5:40 UTC (permalink / raw) To: Frank.Li Cc: linux-arm-kernel, shawn.guo, shawnguo, linus.walleij, lznuaa, linux-gpio, robh+dt, devicetree, Anson Huang, Bai Ping, Fugang Duan On Wed, Jun 17, 2015 at 11:39:23PM +0800, Frank.Li@freescale.com wrote: > From: Frank Li <Frank.Li@freescale.com> > > Add imx6ul support > > Signed-off-by: Anson Huang <b20788@freescale.com> > Signed-off-by: Bai Ping <b51503@freescale.com> > Signed-off-by: Fugang Duan <B38611@freescale.com> > Signed-off-by: Frank Li <Frank.Li@freescale.com> > --- > drivers/clk/imx/Makefile | 1 + > drivers/clk/imx/clk-imx6ul.c | 436 +++++++++++++++++++++++++++++++ > include/dt-bindings/clock/imx6ul-clock.h | 240 +++++++++++++++++ > 3 files changed, 677 insertions(+) > create mode 100644 drivers/clk/imx/clk-imx6ul.c > create mode 100644 include/dt-bindings/clock/imx6ul-clock.h > > diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile > index 75fae16..1ada68a 100644 > --- a/drivers/clk/imx/Makefile > +++ b/drivers/clk/imx/Makefile > @@ -22,5 +22,6 @@ obj-$(CONFIG_SOC_IMX5) += clk-imx51-imx53.o > obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o > obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o > obj-$(CONFIG_SOC_IMX6SX) += clk-imx6sx.o > +obj-$(CONFIG_SOC_IMX6UL) += clk-imx6ul.o > obj-$(CONFIG_SOC_IMX7D) += clk-imx7d.o > obj-$(CONFIG_SOC_VF610) += clk-vf610.o > + > + clk_register_clkdev(clks[IMX6UL_CLK_GPT1_BUS], "ipg", "imx-gpt.0"); > + clk_register_clkdev(clks[IMX6UL_CLK_GPT1_SERIAL], "per", "imx-gpt.0"); > + clk_register_clkdev(clks[IMX6UL_CLK_GPT_3M], "gpt_3m", "imx-gpt.0"); These are not needed. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 5/8] ARM: dts: add i.mx6ul pin function include file [not found] ` <1434555569-8237-1-git-send-email-Frank.Li-KZfg59tc24xl57MIdRCFDg@public.gmane.org> 2015-06-17 15:39 ` [PATCH 2/8] ARM: imx: add imx6ul clk tree support Frank.Li-KZfg59tc24xl57MIdRCFDg @ 2015-06-17 15:39 ` Frank.Li-KZfg59tc24xl57MIdRCFDg 2015-07-09 3:09 ` Shawn Guo 2015-06-17 15:39 ` [PATCH 6/8] ARM: dts: imx: add imx6ul and imx6ul evk board support Frank.Li-KZfg59tc24xl57MIdRCFDg ` (2 subsequent siblings) 4 siblings, 1 reply; 16+ messages in thread From: Frank.Li-KZfg59tc24xl57MIdRCFDg @ 2015-06-17 15:39 UTC (permalink / raw) To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, shawn.guo-QSEj5FYQhm4dnm+yROfE0A, shawnguo-DgEjT+Ai2ygdnm+yROfE0A, linus.walleij-QSEj5FYQhm4dnm+yROfE0A, lznuaa-Re5JQEeQqe8AvxtiuMwx3w Cc: linux-gpio-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A, devicetree-u79uwXL29TY76Z2rM5mHXA, Frank Li, Bai Ping, Anson Huang From: Frank Li <Frank.Li-KZfg59tc24xl57MIdRCFDg@public.gmane.org> add pin mux define file Signed-off-by: Bai Ping <b51503-KZfg59tc24xl57MIdRCFDg@public.gmane.org> Signed-off-by: Anson Huang <b20788-KZfg59tc24xl57MIdRCFDg@public.gmane.org> Signed-off-by: Frank Li <Frank.Li-KZfg59tc24xl57MIdRCFDg@public.gmane.org> --- arch/arm/boot/dts/imx6ul-pinfunc.h | 938 +++++++++++++++++++++++++++++++++++++ 1 file changed, 938 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ul-pinfunc.h diff --git a/arch/arm/boot/dts/imx6ul-pinfunc.h b/arch/arm/boot/dts/imx6ul-pinfunc.h new file mode 100644 index 0000000..1bb774b9 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-pinfunc.h @@ -0,0 +1,938 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DTS_IMX6UL_PINFUNC_H +#define __DTS_IMX6UL_PINFUNC_H + +/* + * The pin function ID is a tuple of + * <mux_reg conf_reg input_reg mux_mode input_val> + */ +#define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x0014 0x02A0 0x0000 5 0 +#define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x0018 0x02A4 0x0000 5 0 + +#define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x001C 0x02A8 0x0000 5 0 +#define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0020 0x02AC 0x0000 5 0 +#define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0024 0x02B0 0x0000 5 0 +#define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0028 0x02B4 0x0000 5 0 +#define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x002C 0x02B8 0x0000 5 0 +#define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0030 0x02BC 0x0000 5 0 +#define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0034 0x02C0 0x0000 5 0 +#define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0038 0x02C4 0x0000 5 0 +#define MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x003C 0x02C8 0x0000 5 0 +#define MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x0040 0x02CC 0x0000 5 0 + +#define MX6UL_PAD_JTAG_MOD__SJC_MOD 0x0044 0x02D0 0x0000 0 0 +#define MX6UL_PAD_JTAG_MOD__GPT2_CLK 0x0044 0x02D0 0x05A0 1 0 +#define MX6UL_PAD_JTAG_MOD__SPDIF_OUT 0x0044 0x02D0 0x0000 2 0 +#define MX6UL_PAD_JTAG_MOD__ENET1_REF_CLK_25M 0x0044 0x02D0 0x0000 3 0 +#define MX6UL_PAD_JTAG_MOD__CCM_PMIC_RDY 0x0044 0x02D0 0x04C0 4 0 +#define MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0044 0x02D0 0x0000 5 0 +#define MX6UL_PAD_JTAG_MOD__SDMA_EXT_EVENT00 0x0044 0x02D0 0x0000 6 0 +#define MX6UL_PAD_JTAG_TMS__SJC_TMS 0x0048 0x02D4 0x0000 0 0 +#define MX6UL_PAD_JTAG_TMS__GPT2_CAPTURE1 0x0048 0x02D4 0x0598 1 0 +#define MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x0048 0x02D4 0x0000 2 0 +#define MX6UL_PAD_JTAG_TMS__CCM_CLKO1 0x0048 0x02D4 0x0000 3 0 +#define MX6UL_PAD_JTAG_TMS__CCM_WAIT 0x0048 0x02D4 0x0000 4 0 +#define MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x0048 0x02D4 0x0000 5 0 +#define MX6UL_PAD_JTAG_TMS__SDMA_EXT_EVENT01 0x0048 0x02D4 0x0000 6 0 +#define MX6UL_PAD_JTAG_TMS__EPIT1_OUT 0x0048 0x02D4 0x0000 8 0 +#define MX6UL_PAD_JTAG_TDO__SJC_TDO 0x004C 0x02D8 0x0000 0 0 +#define MX6UL_PAD_JTAG_TDO__GPT2_CAPTURE2 0x004C 0x02D8 0x059C 1 0 +#define MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x004C 0x02D8 0x05FC 2 0 +#define MX6UL_PAD_JTAG_TDO__CCM_CLKO2 0x004C 0x02D8 0x0000 3 0 +#define MX6UL_PAD_JTAG_TDO__CCM_STOP 0x004C 0x02D8 0x0000 4 0 +#define MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x004C 0x02D8 0x0000 5 0 +#define MX6UL_PAD_JTAG_TDO__MQS_RIGHT 0x004C 0x02D8 0x0000 6 0 +#define MX6UL_PAD_JTAG_TDO__EPIT2_OUT 0x004C 0x02D8 0x0000 8 0 +#define MX6UL_PAD_JTAG_TDI__SJC_TDI 0x0050 0x02DC 0x0000 0 0 +#define MX6UL_PAD_JTAG_TDI__GPT2_COMPARE1 0x0050 0x02DC 0x0000 1 0 +#define MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x0050 0x02DC 0x05F8 2 0 +#define MX6UL_PAD_JTAG_TDI__PWM6_OUT 0x0050 0x02DC 0x0000 4 0 +#define MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x0050 0x02DC 0x0000 5 0 +#define MX6UL_PAD_JTAG_TDI__MQS_LEFT 0x0050 0x02DC 0x0000 6 0 +#define MX6UL_PAD_JTAG_TDI__SIM1_POWER_FAIL 0x0050 0x02DC 0x0000 8 0 +#define MX6UL_PAD_JTAG_TCK__SJC_TCK 0x0054 0x02E0 0x0000 0 0 +#define MX6UL_PAD_JTAG_TCK__GPT2_COMPARE2 0x0054 0x02E0 0x0000 1 0 +#define MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x0054 0x02E0 0x0000 2 0 +#define MX6UL_PAD_JTAG_TCK__PWM7_OUT 0x0054 0x02E0 0x0000 4 0 +#define MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x0054 0x02E0 0x0000 5 0 +#define MX6UL_PAD_JTAG_TCK__SIM2_POWER_FAIL 0x0054 0x02E0 0x0000 8 0 +#define MX6UL_PAD_JTAG_TRST_B__SJC_TRSTB 0x0058 0x02E4 0x0000 0 0 +#define MX6UL_PAD_JTAG_TRST_B__GPT2_COMPARE3 0x0058 0x02E4 0x0000 1 0 +#define MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x0058 0x02E4 0x0000 2 0 +#define MX6UL_PAD_JTAG_TRST_B__PWM8_OUT 0x0058 0x02E4 0x0000 4 0 +#define MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x0058 0x02E4 0x0000 5 0 +#define MX6UL_PAD_JTAG_TRST_B__CAAM_RNG_OSC_OBS 0x0058 0x02E4 0x0000 8 0 +#define MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x005C 0x02E8 0x05AC 0 1 +#define MX6UL_PAD_GPIO1_IO00__GPT1_CAPTURE1 0x005C 0x02E8 0x058C 1 0 +#define MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x005C 0x02E8 0x04B8 2 0 +#define MX6UL_PAD_GPIO1_IO00__ENET1_REF_CLK1 0x005C 0x02E8 0x0574 3 0 +#define MX6UL_PAD_GPIO1_IO00__MQS_RIGHT 0x005C 0x02E8 0x0000 4 0 +#define MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x005C 0x02E8 0x0000 5 0 +#define MX6UL_PAD_GPIO1_IO00__ENET1_1588_EVENT0_IN 0x005C 0x02E8 0x0000 6 0 +#define MX6UL_PAD_GPIO1_IO00__SRC_SYSTEM_RESET 0x005C 0x02E8 0x0000 7 0 +#define MX6UL_PAD_GPIO1_IO00__WDOG3_WDOG_B 0x005C 0x02E8 0x0000 8 0 +#define MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x0060 0x02EC 0x05B0 0 1 +#define MX6UL_PAD_GPIO1_IO01__GPT1_COMPARE1 0x0060 0x02EC 0x0000 1 0 +#define MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC 0x0060 0x02EC 0x0664 2 0 +#define MX6UL_PAD_GPIO1_IO01__ENET2_REF_CLK2 0x0060 0x02EC 0x057C 3 0 +#define MX6UL_PAD_GPIO1_IO01__MQS_LEFT 0x0060 0x02EC 0x0000 4 0 +#define MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x0060 0x02EC 0x0000 5 0 +#define MX6UL_PAD_GPIO1_IO01__ENET1_1588_EVENT0_OUT 0x0060 0x02EC 0x0000 6 0 +#define MX6UL_PAD_GPIO1_IO01__SRC_EARLY_RESET 0x0060 0x02EC 0x0000 7 0 +#define MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B 0x0060 0x02EC 0x0000 8 0 +#define MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x0064 0x02F0 0x05A4 0 0 +#define MX6UL_PAD_GPIO1_IO02__GPT1_COMPARE2 0x0064 0x02F0 0x0000 1 0 +#define MX6UL_PAD_GPIO1_IO02__USB_OTG2_PWR 0x0064 0x02F0 0x0000 2 0 +#define MX6UL_PAD_GPIO1_IO02__ENET1_REF_CLK_25M 0x0064 0x02F0 0x0000 3 0 +#define MX6UL_PAD_GPIO1_IO02__USDHC1_WP 0x0064 0x02F0 0x066C 4 0 +#define MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x0064 0x02F0 0x0000 5 0 +#define MX6UL_PAD_GPIO1_IO02__SDMA_EXT_EVENT00 0x0064 0x02F0 0x0000 6 0 +#define MX6UL_PAD_GPIO1_IO02__SRC_ANY_PU_RESET 0x0064 0x02F0 0x0000 7 0 +#define MX6UL_PAD_GPIO1_IO02__UART1_DCE_TX 0x0064 0x02F0 0x0000 8 0 +#define MX6UL_PAD_GPIO1_IO02__UART1_DTE_RX 0x0064 0x02F0 0x0624 8 0 +#define MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x0068 0x02F4 0x05A8 0 1 +#define MX6UL_PAD_GPIO1_IO03__GPT1_COMPARE3 0x0068 0x02F4 0x0000 1 0 +#define MX6UL_PAD_GPIO1_IO03__USB_OTG2_OC 0x0068 0x02F4 0x0660 2 0 +#define MX6UL_PAD_GPIO1_IO03__USDHC1_CD_B 0x0068 0x02F4 0x0668 4 0 +#define MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x0068 0x02F4 0x0000 5 0 +#define MX6UL_PAD_GPIO1_IO03__CCM_DI0_EXT_CLK 0x0068 0x02F4 0x0000 6 0 +#define MX6UL_PAD_GPIO1_IO03__SRC_TESTER_ACK 0x0068 0x02F4 0x0000 7 0 +#define MX6UL_PAD_GPIO1_IO03__UART1_DTE_TX 0x0068 0x02F4 0x0000 8 0 +#define MX6UL_PAD_GPIO1_IO03__UART1_DCE_RX 0x0068 0x02F4 0x0624 8 1 +#define MX6UL_PAD_GPIO1_IO04__ENET1_REF_CLK1 0x006C 0x02F8 0x0574 0 1 +#define MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x006C 0x02F8 0x0000 1 0 +#define MX6UL_PAD_GPIO1_IO04__USB_OTG1_PWR 0x006C 0x02F8 0x0000 2 0 +#define MX6UL_PAD_GPIO1_IO04__USDHC1_RESET_B 0x006C 0x02F8 0x0000 4 0 +#define MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x006C 0x02F8 0x0000 5 0 +#define MX6UL_PAD_GPIO1_IO04__ENET2_1588_EVENT0_IN 0x006C 0x02F8 0x0000 6 0 +#define MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x006C 0x02F8 0x0000 8 0 +#define MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x006C 0x02F8 0x0644 8 2 +#define MX6UL_PAD_GPIO1_IO05__ENET2_REF_CLK2 0x0070 0x02FC 0x057C 0 1 +#define MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x0070 0x02FC 0x0000 1 0 +#define MX6UL_PAD_GPIO1_IO05__ANATOP_OTG2_ID 0x0070 0x02FC 0x04BC 2 0 +#define MX6UL_PAD_GPIO1_IO05__CSI_FIELD 0x0070 0x02FC 0x0530 3 0 +#define MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x0070 0x02FC 0x0000 4 0 +#define MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x0070 0x02FC 0x0000 5 0 +#define MX6UL_PAD_GPIO1_IO05__ENET2_1588_EVENT0_OUT 0x0070 0x02FC 0x0000 6 0 +#define MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x0070 0x02FC 0x0644 8 3 +#define MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x0070 0x02FC 0x0000 8 0 +#define MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x0074 0x0300 0x0578 0 0 +#define MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x0074 0x0300 0x0580 1 0 +#define MX6UL_PAD_GPIO1_IO06__USB_OTG_PWR_WAKE 0x0074 0x0300 0x0000 2 0 +#define MX6UL_PAD_GPIO1_IO06__CSI_MCLK 0x0074 0x0300 0x0000 3 0 +#define MX6UL_PAD_GPIO1_IO06__USDHC2_WP 0x0074 0x0300 0x069C 4 0 +#define MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x0074 0x0300 0x0000 5 0 +#define MX6UL_PAD_GPIO1_IO06__CCM_WAIT 0x0074 0x0300 0x0000 6 0 +#define MX6UL_PAD_GPIO1_IO06__CCM_REF_EN_B 0x0074 0x0300 0x0000 7 0 +#define MX6UL_PAD_GPIO1_IO06__UART1_DCE_CTS 0x0074 0x0300 0x0000 8 0 +#define MX6UL_PAD_GPIO1_IO06__UART1_DTE_RTS 0x0074 0x0300 0x0620 8 0 +#define MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x0078 0x0304 0x0000 0 0 +#define MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x0078 0x0304 0x0000 1 0 +#define MX6UL_PAD_GPIO1_IO07__USB_OTG_HOST_MODE 0x0078 0x0304 0x0000 2 0 +#define MX6UL_PAD_GPIO1_IO07__CSI_PIXCLK 0x0078 0x0304 0x0528 3 0 +#define MX6UL_PAD_GPIO1_IO07__USDHC2_CD_B 0x0078 0x0304 0x0674 4 1 +#define MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0x0078 0x0304 0x0000 5 0 +#define MX6UL_PAD_GPIO1_IO07__CCM_STOP 0x0078 0x0304 0x0000 6 0 +#define MX6UL_PAD_GPIO1_IO07__UART1_DCE_RTS 0x0078 0x0304 0x0620 8 1 +#define MX6UL_PAD_GPIO1_IO07__UART1_DTE_CTS 0x0078 0x0304 0x0000 8 0 +#define MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x007C 0x0308 0x0000 0 0 +#define MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x007C 0x0308 0x0000 1 0 +#define MX6UL_PAD_GPIO1_IO08__SPDIF_OUT 0x007C 0x0308 0x0000 2 0 +#define MX6UL_PAD_GPIO1_IO08__CSI_VSYNC 0x007C 0x0308 0x052C 3 1 +#define MX6UL_PAD_GPIO1_IO08__USDHC2_VSELECT 0x007C 0x0308 0x0000 4 0 +#define MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x007C 0x0308 0x0000 5 0 +#define MX6UL_PAD_GPIO1_IO08__CCM_PMIC_RDY 0x007C 0x0308 0x04C0 6 1 +#define MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x007C 0x0308 0x0640 8 1 +#define MX6UL_PAD_GPIO1_IO08__UART5_DTE_CTS 0x007C 0x0308 0x0000 8 0 +#define MX6UL_PAD_GPIO1_IO09__PWM2_OUT 0x0080 0x030C 0x0000 0 0 +#define MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x0080 0x030C 0x0000 1 0 +#define MX6UL_PAD_GPIO1_IO09__SPDIF_IN 0x0080 0x030C 0x0618 2 0 +#define MX6UL_PAD_GPIO1_IO09__CSI_HSYNC 0x0080 0x030C 0x0524 3 1 +#define MX6UL_PAD_GPIO1_IO09__USDHC2_RESET_B 0x0080 0x030C 0x0000 4 0 +#define MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x0080 0x030C 0x0000 5 0 +#define MX6UL_PAD_GPIO1_IO09__USDHC1_RESET_B 0x0080 0x030C 0x0000 6 0 +#define MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x0080 0x030C 0x0000 8 0 +#define MX6UL_PAD_GPIO1_IO09__UART5_DTE_RTS 0x0080 0x030C 0x0640 8 2 +#define MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x0084 0x0310 0x0000 0 0 +#define MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x0084 0x0310 0x0624 0 2 +#define MX6UL_PAD_UART1_TX_DATA__ENET1_RDATA02 0x0084 0x0310 0x0000 1 0 +#define MX6UL_PAD_UART1_TX_DATA__I2C3_SCL 0x0084 0x0310 0x05B4 2 0 +#define MX6UL_PAD_UART1_TX_DATA__CSI_DATA02 0x0084 0x0310 0x0000 3 0 +#define MX6UL_PAD_UART1_TX_DATA__GPT1_COMPARE1 0x0084 0x0310 0x0000 4 0 +#define MX6UL_PAD_UART1_TX_DATA__GPIO1_IO16 0x0084 0x0310 0x0000 5 0 +#define MX6UL_PAD_UART1_TX_DATA__SPDIF_OUT 0x0084 0x0310 0x0000 8 0 +#define MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x0088 0x0314 0x0624 0 3 +#define MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x0088 0x0314 0x0000 0 0 +#define MX6UL_PAD_UART1_RX_DATA__ENET1_RDATA03 0x0088 0x0314 0x0000 1 0 +#define MX6UL_PAD_UART1_RX_DATA__I2C3_SDA 0x0088 0x0314 0x05B8 2 0 +#define MX6UL_PAD_UART1_RX_DATA__CSI_DATA03 0x0088 0x0314 0x0000 3 0 +#define MX6UL_PAD_UART1_RX_DATA__GPT1_CLK 0x0088 0x0314 0x0594 4 0 +#define MX6UL_PAD_UART1_RX_DATA__GPIO1_IO17 0x0088 0x0314 0x0000 5 0 +#define MX6UL_PAD_UART1_RX_DATA__SPDIF_IN 0x0088 0x0314 0x0000 8 0 +#define MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS 0x008C 0x0318 0x0000 0 0 +#define MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 0x008C 0x0318 0x0620 0 2 +#define MX6UL_PAD_UART1_CTS_B__ENET1_RX_CLK 0x008C 0x0318 0x0000 1 0 +#define MX6UL_PAD_UART1_CTS_B__USDHC1_WP 0x008C 0x0318 0x066C 2 1 +#define MX6UL_PAD_UART1_CTS_B__CSI_DATA04 0x008C 0x0318 0x0000 3 0 +#define MX6UL_PAD_UART1_CTS_B__ENET2_1588_EVENT1_IN 0x008C 0x0318 0x0000 4 0 +#define MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x008C 0x0318 0x0000 5 0 +#define MX6UL_PAD_UART1_CTS_B__USDHC2_WP 0x008C 0x0318 0x0000 8 0 +#define MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS 0x0090 0x031C 0x0620 0 3 +#define MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS 0x0090 0x031C 0x0000 0 0 +#define MX6UL_PAD_UART1_RTS_B__ENET1_TX_ER 0x0090 0x031C 0x0000 1 0 +#define MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B 0x0090 0x031C 0x0668 2 1 +#define MX6UL_PAD_UART1_RTS_B__CSI_DATA05 0x0090 0x031C 0x0000 3 0 +#define MX6UL_PAD_UART1_RTS_B__ENET2_1588_EVENT1_OUT 0x0090 0x031C 0x0000 4 0 +#define MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0090 0x031C 0x0000 5 0 +#define MX6UL_PAD_UART1_RTS_B__USDHC2_CD_B 0x0090 0x031C 0x0000 8 0 +#define MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x0094 0x0320 0x0000 0 0 +#define MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x0094 0x0320 0x062C 0 0 +#define MX6UL_PAD_UART2_TX_DATA__ENET1_TDATA02 0x0094 0x0320 0x0000 1 0 +#define MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x0094 0x0320 0x05BC 2 0 +#define MX6UL_PAD_UART2_TX_DATA__CSI_DATA06 0x0094 0x0320 0x0000 3 0 +#define MX6UL_PAD_UART2_TX_DATA__GPT1_CAPTURE1 0x0094 0x0320 0x058C 4 1 +#define MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x0094 0x0320 0x0000 5 0 +#define MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0 0x0094 0x0320 0x0000 8 0 +#define MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0098 0x0324 0x062C 0 1 +#define MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x0098 0x0324 0x0000 0 0 +#define MX6UL_PAD_UART2_RX_DATA__ENET1_TDATA03 0x0098 0x0324 0x0000 1 0 +#define MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x0098 0x0324 0x05C0 2 0 +#define MX6UL_PAD_UART2_RX_DATA__CSI_DATA07 0x0098 0x0324 0x0000 3 0 +#define MX6UL_PAD_UART2_RX_DATA__GPT1_CAPTURE2 0x0098 0x0324 0x0590 4 0 +#define MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 0x0098 0x0324 0x0000 5 0 +#define MX6UL_PAD_UART2_RX_DATA__SJC_DONE 0x0098 0x0324 0x0000 7 0 +#define MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x0098 0x0324 0x0000 8 0 +#define MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x009C 0x0328 0x0000 0 0 +#define MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x009C 0x0328 0x0628 0 0 +#define MX6UL_PAD_UART2_CTS_B__ENET1_CRS 0x009C 0x0328 0x0000 1 0 +#define MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x009C 0x0328 0x0000 2 0 +#define MX6UL_PAD_UART2_CTS_B__CSI_DATA08 0x009C 0x0328 0x0000 3 0 +#define MX6UL_PAD_UART2_CTS_B__GPT1_COMPARE2 0x009C 0x0328 0x0000 4 0 +#define MX6UL_PAD_UART2_CTS_B__GPIO1_IO22 0x009C 0x0328 0x0000 5 0 +#define MX6UL_PAD_UART2_CTS_B__SJC_DE_B 0x009C 0x0328 0x0000 7 0 +#define MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x009C 0x0328 0x0000 8 0 +#define MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x00A0 0x032C 0x0628 0 1 +#define MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x00A0 0x032C 0x0000 0 0 +#define MX6UL_PAD_UART2_RTS_B__ENET1_COL 0x00A0 0x032C 0x0000 1 0 +#define MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x00A0 0x032C 0x0588 2 0 +#define MX6UL_PAD_UART2_RTS_B__CSI_DATA09 0x00A0 0x032C 0x0000 3 0 +#define MX6UL_PAD_UART2_RTS_B__GPT1_COMPARE3 0x00A0 0x032C 0x0000 4 0 +#define MX6UL_PAD_UART2_RTS_B__GPIO1_IO23 0x00A0 0x032C 0x0000 5 0 +#define MX6UL_PAD_UART2_RTS_B__SJC_FAIL 0x00A0 0x032C 0x0000 7 0 +#define MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x00A0 0x032C 0x0000 8 0 +#define MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x00A4 0x0330 0x0000 0 0 +#define MX6UL_PAD_UART3_TX_DATA__UART3_DTE_RX 0x00A4 0x0330 0x0634 0 0 +#define MX6UL_PAD_UART3_TX_DATA__ENET2_RDATA02 0x00A4 0x0330 0x0000 1 0 +#define MX6UL_PAD_UART3_TX_DATA__SIM1_PORT0_PD 0x00A4 0x0330 0x0000 2 0 +#define MX6UL_PAD_UART3_TX_DATA__CSI_DATA01 0x00A4 0x0330 0x0000 3 0 +#define MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x00A4 0x0330 0x0000 4 0 +#define MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x00A4 0x0330 0x0628 4 2 +#define MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x00A4 0x0330 0x0000 5 0 +#define MX6UL_PAD_UART3_TX_DATA__SJC_JTAG_ACT 0x00A4 0x0330 0x0000 7 0 +#define MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID 0x00A4 0x0330 0x0000 8 0 +#define MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x00A8 0x0334 0x0634 0 1 +#define MX6UL_PAD_UART3_RX_DATA__UART3_DTE_TX 0x00A8 0x0334 0x0000 0 0 +#define MX6UL_PAD_UART3_RX_DATA__ENET2_RDATA03 0x00A8 0x0334 0x0000 1 0 +#define MX6UL_PAD_UART3_RX_DATA__SIM2_PORT0_PD 0x00A8 0x0334 0x0000 2 0 +#define MX6UL_PAD_UART3_RX_DATA__CSI_DATA00 0x00A8 0x0334 0x0000 3 0 +#define MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x00A8 0x0334 0x0628 4 3 +#define MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x00A8 0x0334 0x0000 4 0 +#define MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x00A8 0x0334 0x0000 5 0 +#define MX6UL_PAD_UART3_RX_DATA__EPIT1_OUT 0x00A8 0x0334 0x0000 8 0 +#define MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x00AC 0x0338 0x0000 0 0 +#define MX6UL_PAD_UART3_CTS_B__UART3_DTE_RTS 0x00AC 0x0338 0x0630 0 0 +#define MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK 0x00AC 0x0338 0x0000 1 0 +#define MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x00AC 0x0338 0x0000 2 0 +#define MX6UL_PAD_UART3_CTS_B__CSI_DATA10 0x00AC 0x0338 0x0000 3 0 +#define MX6UL_PAD_UART3_CTS_B__ENET1_1588_EVENT1_IN 0x00AC 0x0338 0x0000 4 0 +#define MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x00AC 0x0338 0x0000 5 0 +#define MX6UL_PAD_UART3_CTS_B__EPIT2_OUT 0x00AC 0x0338 0x0000 8 0 +#define MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x00B0 0x033C 0x0630 0 1 +#define MX6UL_PAD_UART3_RTS_B__UART3_DTE_CTS 0x00B0 0x033C 0x0000 0 0 +#define MX6UL_PAD_UART3_RTS_B__ENET2_TX_ER 0x00B0 0x033C 0x0000 1 0 +#define MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x00B0 0x033C 0x0584 2 0 +#define MX6UL_PAD_UART3_RTS_B__CSI_DATA11 0x00B0 0x033C 0x0000 3 0 +#define MX6UL_PAD_UART3_RTS_B__ENET1_1588_EVENT1_OUT 0x00B0 0x033C 0x0000 4 0 +#define MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x00B0 0x033C 0x0000 5 0 +#define MX6UL_PAD_UART3_RTS_B__WDOG1_WDOG_B 0x00B0 0x033C 0x0000 8 0 +#define MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x00B4 0x0340 0x0000 0 0 +#define MX6UL_PAD_UART4_TX_DATA__UART4_DTE_RX 0x00B4 0x0340 0x063C 0 0 +#define MX6UL_PAD_UART4_TX_DATA__ENET2_TDATA02 0x00B4 0x0340 0x0000 1 0 +#define MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x00B4 0x0340 0x05A4 2 1 +#define MX6UL_PAD_UART4_TX_DATA__CSI_DATA12 0x00B4 0x0340 0x0000 3 0 +#define MX6UL_PAD_UART4_TX_DATA__CSU_CSU_ALARM_AUT02 0x00B4 0x0340 0x0000 4 0 +#define MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x00B4 0x0340 0x0000 5 0 +#define MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x00B4 0x0340 0x0000 8 0 +#define MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x00B8 0x0344 0x063C 0 1 +#define MX6UL_PAD_UART4_RX_DATA__UART4_DTE_TX 0x00B8 0x0344 0x0000 0 0 +#define MX6UL_PAD_UART4_RX_DATA__ENET2_TDATA03 0x00B8 0x0344 0x0000 1 0 +#define MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x00B8 0x0344 0x05A8 2 2 +#define MX6UL_PAD_UART4_RX_DATA__CSI_DATA13 0x00B8 0x0344 0x0000 3 0 +#define MX6UL_PAD_UART4_RX_DATA__CSU_CSU_ALARM_AUT01 0x00B8 0x0344 0x0000 4 0 +#define MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x00B8 0x0344 0x0000 5 0 +#define MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0 0x00B8 0x0344 0x0000 8 0 +#define MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x00BC 0x0348 0x0000 5 0 +#define MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x00BC 0x0348 0x0000 8 0 +#define MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x00BC 0x0348 0x0000 0 0 +#define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX 0x00BC 0x0348 0x0644 0 4 +#define MX6UL_PAD_UART5_TX_DATA__ENET2_CRS 0x00BC 0x0348 0x0000 1 0 +#define MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x00BC 0x0348 0x05AC 2 2 +#define MX6UL_PAD_UART5_TX_DATA__CSI_DATA14 0x00BC 0x0348 0x0000 3 0 +#define MX6UL_PAD_UART5_TX_DATA__CSU_CSU_ALARM_AUT00 0x00BC 0x0348 0x0000 4 0 +#define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x00C0 0x034C 0x0644 0 5 +#define MX6UL_PAD_UART5_RX_DATA__UART5_DTE_TX 0x00C0 0x034C 0x0000 0 0 +#define MX6UL_PAD_UART5_RX_DATA__ENET2_COL 0x00C0 0x034C 0x0000 1 0 +#define MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x00C0 0x034C 0x05B0 2 2 +#define MX6UL_PAD_UART5_RX_DATA__CSI_DATA15 0x00C0 0x034C 0x0000 3 0 +#define MX6UL_PAD_UART5_RX_DATA__CSU_CSU_INT_DEB 0x00C0 0x034C 0x0000 4 0 +#define MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x00C0 0x034C 0x0000 5 0 +#define MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x00C0 0x034C 0x0000 8 0 +#define MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x00C4 0x0350 0x0000 0 0 +#define MX6UL_PAD_ENET1_RX_DATA0__UART4_DCE_RTS 0x00C4 0x0350 0x0638 1 0 +#define MX6UL_PAD_ENET1_RX_DATA0__UART4_DTE_CTS 0x00C4 0x0350 0x0000 1 0 +#define MX6UL_PAD_ENET1_RX_DATA0__PWM1_OUT 0x00C4 0x0350 0x0000 2 0 +#define MX6UL_PAD_ENET1_RX_DATA0__CSI_DATA16 0x00C4 0x0350 0x0000 3 0 +#define MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x00C4 0x0350 0x0000 4 0 +#define MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0x00C4 0x0350 0x0000 5 0 +#define MX6UL_PAD_ENET1_RX_DATA0__KPP_ROW00 0x00C4 0x0350 0x0000 6 0 +#define MX6UL_PAD_ENET1_RX_DATA0__USDHC1_LCTL 0x00C4 0x0350 0x0000 8 0 +#define MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x00C8 0x0354 0x0000 0 0 +#define MX6UL_PAD_ENET1_RX_DATA1__UART4_DCE_CTS 0x00C8 0x0354 0x0000 1 0 +#define MX6UL_PAD_ENET1_RX_DATA1__UART4_DTE_RTS 0x00C8 0x0354 0x0638 1 1 +#define MX6UL_PAD_ENET1_RX_DATA1__PWM2_OUT 0x00C8 0x0354 0x0000 2 0 +#define MX6UL_PAD_ENET1_RX_DATA1__CSI_DATA17 0x00C8 0x0354 0x0000 3 0 +#define MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x00C8 0x0354 0x0584 4 1 +#define MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0x00C8 0x0354 0x0000 5 0 +#define MX6UL_PAD_ENET1_RX_DATA1__KPP_COL00 0x00C8 0x0354 0x0000 6 0 +#define MX6UL_PAD_ENET1_RX_DATA1__USDHC2_LCTL 0x00C8 0x0354 0x0000 8 0 +#define MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x00CC 0x0358 0x0000 0 0 +#define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS 0x00CC 0x0358 0x0640 1 3 +#define MX6UL_PAD_ENET1_RX_EN__UART5_DTE_CTS 0x00CC 0x0358 0x0000 1 0 +#define MX6UL_PAD_ENET1_RX_EN__CSI_DATA18 0x00CC 0x0358 0x0000 3 0 +#define MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x00CC 0x0358 0x0000 4 0 +#define MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x00CC 0x0358 0x0000 5 0 +#define MX6UL_PAD_ENET1_RX_EN__KPP_ROW01 0x00CC 0x0358 0x0000 6 0 +#define MX6UL_PAD_ENET1_RX_EN__USDHC1_VSELECT 0x00CC 0x0358 0x0000 8 0 +#define MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x00D0 0x035C 0x0000 0 0 +#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DCE_CTS 0x00D0 0x035C 0x0000 1 0 +#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS 0x00D0 0x035C 0x0640 1 4 +#define MX6UL_PAD_ENET1_TX_DATA0__CSI_DATA19 0x00D0 0x035C 0x0000 3 0 +#define MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x00D0 0x035C 0x0588 4 1 +#define MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x00D0 0x035C 0x0000 5 0 +#define MX6UL_PAD_ENET1_TX_DATA0__KPP_COL01 0x00D0 0x035C 0x0000 6 0 +#define MX6UL_PAD_ENET1_TX_DATA0__USDHC2_VSELECT 0x00D0 0x035C 0x0000 8 0 +#define MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x00D4 0x0360 0x0000 0 0 +#define MX6UL_PAD_ENET1_TX_DATA1__UART6_DCE_CTS 0x00D4 0x0360 0x0000 1 0 +#define MX6UL_PAD_ENET1_TX_DATA1__UART6_DTE_RTS 0x00D4 0x0360 0x0648 1 2 +#define MX6UL_PAD_ENET1_TX_DATA1__PWM5_OUT 0x00D4 0x0360 0x0000 2 0 +#define MX6UL_PAD_ENET1_TX_DATA1__CSI_DATA20 0x00D4 0x0360 0x0000 3 0 +#define MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO 0x00D4 0x0360 0x0580 4 1 +#define MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x00D4 0x0360 0x0000 5 0 +#define MX6UL_PAD_ENET1_TX_DATA1__KPP_ROW02 0x00D4 0x0360 0x0000 6 0 +#define MX6UL_PAD_ENET1_TX_DATA1__WDOG1_WDOG_RST_B_DEB 0x00D4 0x0360 0x0000 8 0 +#define MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x00D8 0x0364 0x0000 0 0 +#define MX6UL_PAD_ENET1_TX_EN__UART6_DCE_RTS 0x00D8 0x0364 0x0648 1 3 +#define MX6UL_PAD_ENET1_TX_EN__UART6_DTE_CTS 0x00D8 0x0364 0x0000 1 0 +#define MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00D8 0x0364 0x0000 2 0 +#define MX6UL_PAD_ENET1_TX_EN__CSI_DATA21 0x00D8 0x0364 0x0000 3 0 +#define MX6UL_PAD_ENET1_TX_EN__ENET2_MDC 0x00D8 0x0364 0x0000 4 0 +#define MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05 0x00D8 0x0364 0x0000 5 0 +#define MX6UL_PAD_ENET1_TX_EN__KPP_COL02 0x00D8 0x0364 0x0000 6 0 +#define MX6UL_PAD_ENET1_TX_EN__WDOG2_WDOG_RST_B_DEB 0x00D8 0x0364 0x0000 8 0 +#define MX6UL_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x00DC 0x0368 0x0000 0 0 +#define MX6UL_PAD_ENET1_TX_CLK__UART7_DCE_CTS 0x00DC 0x0368 0x0000 1 0 +#define MX6UL_PAD_ENET1_TX_CLK__UART7_DTE_RTS 0x00DC 0x0368 0x0650 1 0 +#define MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00DC 0x0368 0x0000 2 0 +#define MX6UL_PAD_ENET1_TX_CLK__CSI_DATA22 0x00DC 0x0368 0x0000 3 0 +#define MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x00DC 0x0368 0x0574 4 2 +#define MX6UL_PAD_ENET1_TX_CLK__GPIO2_IO06 0x00DC 0x0368 0x0000 5 0 +#define MX6UL_PAD_ENET1_TX_CLK__KPP_ROW03 0x00DC 0x0368 0x0000 6 0 +#define MX6UL_PAD_ENET1_TX_CLK__GPT1_CLK 0x00DC 0x0368 0x0000 8 0 +#define MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x00E0 0x036C 0x0000 0 0 +#define MX6UL_PAD_ENET1_RX_ER__UART7_DCE_RTS 0x00E0 0x036C 0x0650 1 1 +#define MX6UL_PAD_ENET1_RX_ER__UART7_DTE_CTS 0x00E0 0x036C 0x0000 1 0 +#define MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x00E0 0x036C 0x0000 2 0 +#define MX6UL_PAD_ENET1_RX_ER__CSI_DATA23 0x00E0 0x036C 0x0000 3 0 +#define MX6UL_PAD_ENET1_RX_ER__EIM_CRE 0x00E0 0x036C 0x0000 4 0 +#define MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x00E0 0x036C 0x0000 5 0 +#define MX6UL_PAD_ENET1_RX_ER__KPP_COL03 0x00E0 0x036C 0x0000 6 0 +#define MX6UL_PAD_ENET1_RX_ER__GPT1_CAPTURE2 0x00E0 0x036C 0x0000 8 0 +#define MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x00E4 0x0370 0x0000 0 0 +#define MX6UL_PAD_ENET2_RX_DATA0__UART6_DCE_TX 0x00E4 0x0370 0x0000 1 0 +#define MX6UL_PAD_ENET2_RX_DATA0__UART6_DTE_RX 0x00E4 0x0370 0x064C 1 1 +#define MX6UL_PAD_ENET2_RX_DATA0__SIM1_PORT0_TRXD 0x00E4 0x0370 0x0000 2 0 +#define MX6UL_PAD_ENET2_RX_DATA0__I2C3_SCL 0x00E4 0x0370 0x05B4 3 1 +#define MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO 0x00E4 0x0370 0x0578 4 1 +#define MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x00E4 0x0370 0x0000 5 0 +#define MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04 0x00E4 0x0370 0x0000 6 0 +#define MX6UL_PAD_ENET2_RX_DATA0__USB_OTG1_PWR 0x00E4 0x0370 0x0000 8 0 +#define MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x00E8 0x0374 0x0000 0 0 +#define MX6UL_PAD_ENET2_RX_DATA1__UART6_DCE_RX 0x00E8 0x0374 0x064C 1 2 +#define MX6UL_PAD_ENET2_RX_DATA1__UART6_DTE_TX 0x00E8 0x0374 0x0000 1 0 +#define MX6UL_PAD_ENET2_RX_DATA1__SIM1_PORT0_CLK 0x00E8 0x0374 0x0000 2 0 +#define MX6UL_PAD_ENET2_RX_DATA1__I2C3_SDA 0x00E8 0x0374 0x05B8 3 1 +#define MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC 0x00E8 0x0374 0x0000 4 0 +#define MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x00E8 0x0374 0x0000 5 0 +#define MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04 0x00E8 0x0374 0x0000 6 0 +#define MX6UL_PAD_ENET2_RX_DATA1__USB_OTG1_OC 0x00E8 0x0374 0x0000 8 0 +#define MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x00EC 0x0378 0x0000 0 0 +#define MX6UL_PAD_ENET2_RX_EN__UART7_DCE_TX 0x00EC 0x0378 0x0000 1 0 +#define MX6UL_PAD_ENET2_RX_EN__UART7_DTE_RX 0x00EC 0x0378 0x0654 1 0 +#define MX6UL_PAD_ENET2_RX_EN__SIM1_PORT0_RST_B 0x00EC 0x0378 0x0000 2 0 +#define MX6UL_PAD_ENET2_RX_EN__I2C4_SCL 0x00EC 0x0378 0x05BC 3 1 +#define MX6UL_PAD_ENET2_RX_EN__EIM_ADDR26 0x00EC 0x0378 0x0000 4 0 +#define MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x00EC 0x0378 0x0000 5 0 +#define MX6UL_PAD_ENET2_RX_EN__KPP_ROW05 0x00EC 0x0378 0x0000 6 0 +#define MX6UL_PAD_ENET2_RX_EN__ENET1_REF_CLK_25M 0x00EC 0x0378 0x0000 8 0 +#define MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x00F0 0x037C 0x0000 0 0 +#define MX6UL_PAD_ENET2_TX_DATA0__UART7_DCE_RX 0x00F0 0x037C 0x0654 1 1 +#define MX6UL_PAD_ENET2_TX_DATA0__UART7_DTE_TX 0x00F0 0x037C 0x0000 1 0 +#define MX6UL_PAD_ENET2_TX_DATA0__SIM1_PORT0_SVEN 0x00F0 0x037C 0x0000 2 0 +#define MX6UL_PAD_ENET2_TX_DATA0__I2C4_SDA 0x00F0 0x037C 0x05C0 3 1 +#define MX6UL_PAD_ENET2_TX_DATA0__EIM_EB_B02 0x00F0 0x037C 0x0000 4 0 +#define MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x00F0 0x037C 0x0000 5 0 +#define MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05 0x00F0 0x037C 0x0000 6 0 +#define MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x00F4 0x0380 0x0000 0 0 +#define MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX 0x00F4 0x0380 0x0000 1 0 +#define MX6UL_PAD_ENET2_TX_DATA1__UART8_DTE_RX 0x00F4 0x0380 0x065C 1 0 +#define MX6UL_PAD_ENET2_TX_DATA1__SIM2_PORT0_TRXD 0x00F4 0x0380 0x0000 2 0 +#define MX6UL_PAD_ENET2_TX_DATA1__ECSPI4_SCLK 0x00F4 0x0380 0x0564 3 0 +#define MX6UL_PAD_ENET2_TX_DATA1__EIM_EB_B03 0x00F4 0x0380 0x0000 4 0 +#define MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x00F4 0x0380 0x0000 5 0 +#define MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06 0x00F4 0x0380 0x0000 6 0 +#define MX6UL_PAD_ENET2_TX_DATA1__USB_OTG2_PWR 0x00F4 0x0380 0x0000 8 0 +#define MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x00F8 0x0384 0x0000 0 0 +#define MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX 0x00F8 0x0384 0x065C 1 1 +#define MX6UL_PAD_ENET2_TX_EN__UART8_DTE_TX 0x00F8 0x0384 0x0000 1 0 +#define MX6UL_PAD_ENET2_TX_EN__SIM2_PORT0_CLK 0x00F8 0x0384 0x0000 2 0 +#define MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI 0x00F8 0x0384 0x056C 3 0 +#define MX6UL_PAD_ENET2_TX_EN__EIM_ACLK_FREERUN 0x00F8 0x0384 0x0000 4 0 +#define MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x00F8 0x0384 0x0000 5 0 +#define MX6UL_PAD_ENET2_TX_EN__KPP_COL06 0x00F8 0x0384 0x0000 6 0 +#define MX6UL_PAD_ENET2_TX_EN__USB_OTG2_OC 0x00F8 0x0384 0x0000 8 0 +#define MX6UL_PAD_ENET2_TX_CLK__ENET2_TX_CLK 0x00FC 0x0388 0x0000 0 0 +#define MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS 0x00FC 0x0388 0x0000 1 0 +#define MX6UL_PAD_ENET2_TX_CLK__UART8_DTE_RTS 0x00FC 0x0388 0x0658 1 0 +#define MX6UL_PAD_ENET2_TX_CLK__SIM2_PORT0_RST_B 0x00FC 0x0388 0x0000 2 0 +#define MX6UL_PAD_ENET2_TX_CLK__ECSPI4_MISO 0x00FC 0x0388 0x0568 3 0 +#define MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x00FC 0x0388 0x057C 4 2 +#define MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14 0x00FC 0x0388 0x0000 5 0 +#define MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07 0x00FC 0x0388 0x0000 6 0 +#define MX6UL_PAD_ENET2_TX_CLK__ANATOP_OTG2_ID 0x00FC 0x0388 0x0000 8 0 +#define MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x0100 0x038C 0x0000 0 0 +#define MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS 0x0100 0x038C 0x0658 1 1 +#define MX6UL_PAD_ENET2_RX_ER__UART8_DTE_CTS 0x0100 0x038C 0x0000 1 0 +#define MX6UL_PAD_ENET2_RX_ER__SIM2_PORT0_SVEN 0x0100 0x038C 0x0000 2 0 +#define MX6UL_PAD_ENET2_RX_ER__ECSPI4_SS0 0x0100 0x038C 0x0000 3 0 +#define MX6UL_PAD_ENET2_RX_ER__EIM_ADDR25 0x0100 0x038C 0x0000 4 0 +#define MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x0100 0x038C 0x0000 5 0 +#define MX6UL_PAD_ENET2_RX_ER__KPP_COL07 0x0100 0x038C 0x0000 6 0 +#define MX6UL_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY 0x0100 0x038C 0x0000 8 0 +#define MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x0104 0x0390 0x0000 0 0 +#define MX6UL_PAD_LCD_CLK__LCDIF_WR_RWN 0x0104 0x0390 0x0000 1 0 +#define MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x0104 0x0390 0x0000 2 0 +#define MX6UL_PAD_LCD_CLK__UART4_DTE_RX 0x0104 0x0390 0x063C 2 2 +#define MX6UL_PAD_LCD_CLK__SAI3_MCLK 0x0104 0x0390 0x0000 3 0 +#define MX6UL_PAD_LCD_CLK__EIM_CS2_B 0x0104 0x0390 0x0000 4 0 +#define MX6UL_PAD_LCD_CLK__GPIO3_IO00 0x0104 0x0390 0x0000 5 0 +#define MX6UL_PAD_LCD_CLK__WDOG1_WDOG_RST_B_DEB 0x0104 0x0390 0x0000 8 0 +#define MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x0108 0x0394 0x0000 0 0 +#define MX6UL_PAD_LCD_ENABLE__LCDIF_RD_E 0x0108 0x0394 0x0000 1 0 +#define MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x0108 0x0394 0x063C 2 3 +#define MX6UL_PAD_LCD_ENABLE__UART4_DTE_TX 0x0108 0x0394 0x0000 2 0 +#define MX6UL_PAD_LCD_ENABLE__SAI3_TX_SYNC 0x0108 0x0394 0x060C 3 0 +#define MX6UL_PAD_LCD_ENABLE__EIM_CS3_B 0x0108 0x0394 0x0000 4 0 +#define MX6UL_PAD_LCD_ENABLE__GPIO3_IO01 0x0108 0x0394 0x0000 5 0 +#define MX6UL_PAD_LCD_ENABLE__ECSPI2_RDY 0x0108 0x0394 0x0000 8 0 +#define MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x010C 0x0398 0x05DC 0 0 +#define MX6UL_PAD_LCD_HSYNC__LCDIF_RS 0x010C 0x0398 0x0000 1 0 +#define MX6UL_PAD_LCD_HSYNC__UART4_DCE_CTS 0x010C 0x0398 0x0000 2 0 +#define MX6UL_PAD_LCD_HSYNC__UART4_DTE_RTS 0x010C 0x0398 0x0638 2 2 +#define MX6UL_PAD_LCD_HSYNC__SAI3_TX_BCLK 0x010C 0x0398 0x0608 3 0 +#define MX6UL_PAD_LCD_HSYNC__WDOG3_WDOG_RST_B_DEB 0x010C 0x0398 0x0000 4 0 +#define MX6UL_PAD_LCD_HSYNC__GPIO3_IO02 0x010C 0x0398 0x0000 5 0 +#define MX6UL_PAD_LCD_HSYNC__ECSPI2_SS1 0x010C 0x0398 0x0000 8 0 +#define MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x0110 0x039C 0x0000 0 0 +#define MX6UL_PAD_LCD_VSYNC__LCDIF_BUSY 0x0110 0x039C 0x05DC 1 1 +#define MX6UL_PAD_LCD_VSYNC__UART4_DCE_RTS 0x0110 0x039C 0x0638 2 3 +#define MX6UL_PAD_LCD_VSYNC__UART4_DTE_CTS 0x0110 0x039C 0x0000 2 0 +#define MX6UL_PAD_LCD_VSYNC__SAI3_RX_DATA 0x0110 0x039C 0x0000 3 0 +#define MX6UL_PAD_LCD_VSYNC__WDOG2_WDOG_B 0x0110 0x039C 0x0000 4 0 +#define MX6UL_PAD_LCD_VSYNC__GPIO3_IO03 0x0110 0x039C 0x0000 5 0 +#define MX6UL_PAD_LCD_VSYNC__ECSPI2_SS2 0x0110 0x039C 0x0000 8 0 +#define MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x0114 0x03A0 0x0000 0 0 +#define MX6UL_PAD_LCD_RESET__LCDIF_CS 0x0114 0x03A0 0x0000 1 0 +#define MX6UL_PAD_LCD_RESET__CA7_MX6UL_EVENTI 0x0114 0x03A0 0x0000 2 0 +#define MX6UL_PAD_LCD_RESET__SAI3_TX_DATA 0x0114 0x03A0 0x0000 3 0 +#define MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x0114 0x03A0 0x0000 4 0 +#define MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0114 0x03A0 0x0000 5 0 +#define MX6UL_PAD_LCD_RESET__ECSPI2_SS3 0x0114 0x03A0 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x0118 0x03A4 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA00__PWM1_OUT 0x0118 0x03A4 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA00__ENET1_1588_EVENT2_IN 0x0118 0x03A4 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA00__I2C3_SDA 0x0118 0x03A4 0x05B8 4 2 +#define MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x0118 0x03A4 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA00__SRC_BT_CFG00 0x0118 0x03A4 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA00__SAI1_MCLK 0x0118 0x03A4 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x011C 0x03A8 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA01__PWM2_OUT 0x011C 0x03A8 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA01__ENET1_1588_EVENT2_OUT 0x011C 0x03A8 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA01__I2C3_SCL 0x011C 0x03A8 0x05B4 4 2 +#define MX6UL_PAD_LCD_DATA01__GPIO3_IO06 0x011C 0x03A8 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA01__SRC_BT_CFG01 0x011C 0x03A8 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA01__SAI1_TX_SYNC 0x011C 0x03A8 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x0120 0x03AC 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA02__PWM3_OUT 0x0120 0x03AC 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA02__ENET1_1588_EVENT3_IN 0x0120 0x03AC 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA02__I2C4_SDA 0x0120 0x03AC 0x05C0 4 2 +#define MX6UL_PAD_LCD_DATA02__GPIO3_IO07 0x0120 0x03AC 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA02__SRC_BT_CFG02 0x0120 0x03AC 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA02__SAI1_TX_BCLK 0x0120 0x03AC 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x0124 0x03B0 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA03__PWM4_OUT 0x0124 0x03B0 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA03__ENET1_1588_EVENT3_OUT 0x0124 0x03B0 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA03__I2C4_SCL 0x0124 0x03B0 0x05BC 4 2 +#define MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0x0124 0x03B0 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA03__SRC_BT_CFG03 0x0124 0x03B0 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA03__SAI1_RX_DATA 0x0124 0x03B0 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x0128 0x03B4 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA04__UART8_DCE_CTS 0x0128 0x03B4 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA04__UART8_DTE_RTS 0x0128 0x03B4 0x0658 1 2 +#define MX6UL_PAD_LCD_DATA04__ENET2_1588_EVENT2_IN 0x0128 0x03B4 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA04__SPDIF_SR_CLK 0x0128 0x03B4 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA04__GPIO3_IO09 0x0128 0x03B4 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA04__SRC_BT_CFG04 0x0128 0x03B4 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA04__SAI1_TX_DATA 0x0128 0x03B4 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x012C 0x03B8 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA05__UART8_DCE_RTS 0x012C 0x03B8 0x0658 1 3 +#define MX6UL_PAD_LCD_DATA05__UART8_DTE_CTS 0x012C 0x03B8 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA05__ENET2_1588_EVENT2_OUT 0x012C 0x03B8 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA05__SPDIF_OUT 0x012C 0x03B8 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x012C 0x03B8 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA05__SRC_BT_CFG05 0x012C 0x03B8 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA05__ECSPI1_SS1 0x012C 0x03B8 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x0130 0x03BC 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA06__UART7_DCE_CTS 0x0130 0x03BC 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA06__UART7_DTE_RTS 0x0130 0x03BC 0x0650 1 2 +#define MX6UL_PAD_LCD_DATA06__ENET2_1588_EVENT3_IN 0x0130 0x03BC 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA06__SPDIF_LOCK 0x0130 0x03BC 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x0130 0x03BC 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA06__SRC_BT_CFG06 0x0130 0x03BC 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA06__ECSPI1_SS2 0x0130 0x03BC 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x0134 0x03C0 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA07__UART7_DCE_RTS 0x0134 0x03C0 0x0650 1 3 +#define MX6UL_PAD_LCD_DATA07__UART7_DTE_CTS 0x0134 0x03C0 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA07__ENET2_1588_EVENT3_OUT 0x0134 0x03C0 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA07__SPDIF_EXT_CLK 0x0134 0x03C0 0x061C 4 0 +#define MX6UL_PAD_LCD_DATA07__GPIO3_IO12 0x0134 0x03C0 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA07__SRC_BT_CFG07 0x0134 0x03C0 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA07__ECSPI1_SS3 0x0134 0x03C0 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x0138 0x03C4 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA08__SPDIF_IN 0x0138 0x03C4 0x0618 1 2 +#define MX6UL_PAD_LCD_DATA08__CSI_DATA16 0x0138 0x03C4 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA08__EIM_DATA00 0x0138 0x03C4 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA08__GPIO3_IO13 0x0138 0x03C4 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA08__SRC_BT_CFG08 0x0138 0x03C4 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX 0x0138 0x03C4 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x013C 0x03C8 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA09__SAI3_MCLK 0x013C 0x03C8 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA09__CSI_DATA17 0x013C 0x03C8 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA09__EIM_DATA01 0x013C 0x03C8 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA09__GPIO3_IO14 0x013C 0x03C8 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA09__SRC_BT_CFG09 0x013C 0x03C8 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX 0x013C 0x03C8 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x0140 0x03CC 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA10__SAI3_RX_SYNC 0x0140 0x03CC 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA10__CSI_DATA18 0x0140 0x03CC 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA10__EIM_DATA02 0x0140 0x03CC 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA10__GPIO3_IO15 0x0140 0x03CC 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA10__SRC_BT_CFG10 0x0140 0x03CC 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA10__FLEXCAN2_TX 0x0140 0x03CC 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x0144 0x03D0 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA11__SAI3_RX_BCLK 0x0144 0x03D0 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA11__CSI_DATA19 0x0144 0x03D0 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA11__EIM_DATA03 0x0144 0x03D0 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA11__GPIO3_IO16 0x0144 0x03D0 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA11__SRC_BT_CFG11 0x0144 0x03D0 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA11__FLEXCAN2_RX 0x0144 0x03D0 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x0148 0x03D4 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA12__SAI3_TX_SYNC 0x0148 0x03D4 0x060C 1 1 +#define MX6UL_PAD_LCD_DATA12__CSI_DATA20 0x0148 0x03D4 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA12__EIM_DATA04 0x0148 0x03D4 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x0148 0x03D4 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA12__SRC_BT_CFG12 0x0148 0x03D4 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA12__ECSPI1_RDY 0x0148 0x03D4 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x014C 0x03D8 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA13__SAI3_TX_BCLK 0x014C 0x03D8 0x0608 1 1 +#define MX6UL_PAD_LCD_DATA13__CSI_DATA21 0x014C 0x03D8 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA13__EIM_DATA05 0x014C 0x03D8 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA13__GPIO3_IO18 0x014C 0x03D8 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA13__SRC_BT_CFG13 0x014C 0x03D8 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA13__USDHC2_RESET_B 0x014C 0x03D8 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x0150 0x03DC 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA14__SAI3_RX_DATA 0x0150 0x03DC 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA14__CSI_DATA22 0x0150 0x03DC 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA14__EIM_DATA06 0x0150 0x03DC 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA14__GPIO3_IO19 0x0150 0x03DC 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA14__SRC_BT_CFG14 0x0150 0x03DC 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA14__USDHC2_DATA4 0x0150 0x03DC 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x0154 0x03E0 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA15__SAI3_TX_DATA 0x0154 0x03E0 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA15__CSI_DATA23 0x0154 0x03E0 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA15__EIM_DATA07 0x0154 0x03E0 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA15__GPIO3_IO20 0x0154 0x03E0 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA15__SRC_BT_CFG15 0x0154 0x03E0 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA15__USDHC2_DATA5 0x0154 0x03E0 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x0158 0x03E4 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 0x0158 0x03E4 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA16__UART7_DTE_RX 0x0158 0x03E4 0x0654 1 2 +#define MX6UL_PAD_LCD_DATA16__CSI_DATA01 0x0158 0x03E4 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA16__EIM_DATA08 0x0158 0x03E4 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA16__GPIO3_IO21 0x0158 0x03E4 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA16__SRC_BT_CFG24 0x0158 0x03E4 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA16__USDHC2_DATA6 0x0158 0x03E4 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x015C 0x03E8 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 0x015C 0x03E8 0x0654 1 3 +#define MX6UL_PAD_LCD_DATA17__UART7_DTE_TX 0x015C 0x03E8 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA17__CSI_DATA00 0x015C 0x03E8 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA17__EIM_DATA09 0x015C 0x03E8 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA17__GPIO3_IO22 0x015C 0x03E8 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA17__SRC_BT_CFG25 0x015C 0x03E8 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA17__USDHC2_DATA7 0x015C 0x03E8 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x0160 0x03EC 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA18__PWM5_OUT 0x0160 0x03EC 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA18__CA7_MX6UL_EVENTO 0x0160 0x03EC 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA18__CSI_DATA10 0x0160 0x03EC 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA18__EIM_DATA10 0x0160 0x03EC 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x0160 0x03EC 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA18__SRC_BT_CFG26 0x0160 0x03EC 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA18__USDHC2_CMD 0x0160 0x03EC 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA19__EIM_DATA11 0x0164 0x03F0 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x0164 0x03F0 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA19__SRC_BT_CFG27 0x0164 0x03F0 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA19__USDHC2_CLK 0x0164 0x03F0 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x0164 0x03F0 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA19__PWM6_OUT 0x0164 0x03F0 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA19__WDOG1_WDOG_ANY 0x0164 0x03F0 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA19__CSI_DATA11 0x0164 0x03F0 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA20__EIM_DATA12 0x0168 0x03F4 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA20__GPIO3_IO25 0x0168 0x03F4 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA20__SRC_BT_CFG28 0x0168 0x03F4 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA20__USDHC2_DATA0 0x0168 0x03F4 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x0168 0x03F4 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA20__UART8_DCE_TX 0x0168 0x03F4 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA20__UART8_DTE_RX 0x0168 0x03F4 0x065C 1 2 +#define MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x0168 0x03F4 0x0534 2 0 +#define MX6UL_PAD_LCD_DATA20__CSI_DATA12 0x0168 0x03F4 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x016C 0x03F8 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA21__UART8_DCE_RX 0x016C 0x03F8 0x065C 1 3 +#define MX6UL_PAD_LCD_DATA21__UART8_DTE_TX 0x016C 0x03F8 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA21__ECSPI1_SS0 0x016C 0x03F8 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA21__CSI_DATA13 0x016C 0x03F8 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA21__EIM_DATA13 0x016C 0x03F8 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x016C 0x03F8 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA21__SRC_BT_CFG29 0x016C 0x03F8 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA21__USDHC2_DATA1 0x016C 0x03F8 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x0170 0x03FC 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA22__MQS_RIGHT 0x0170 0x03FC 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x0170 0x03FC 0x053C 2 0 +#define MX6UL_PAD_LCD_DATA22__CSI_DATA14 0x0170 0x03FC 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA22__EIM_DATA14 0x0170 0x03FC 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA22__GPIO3_IO27 0x0170 0x03FC 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA22__SRC_BT_CFG30 0x0170 0x03FC 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA22__USDHC2_DATA2 0x0170 0x03FC 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x0174 0x0400 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA23__MQS_LEFT 0x0174 0x0400 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x0174 0x0400 0x0538 2 0 +#define MX6UL_PAD_LCD_DATA23__CSI_DATA15 0x0174 0x0400 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA23__EIM_DATA15 0x0174 0x0400 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA23__GPIO3_IO28 0x0174 0x0400 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA23__SRC_BT_CFG31 0x0174 0x0400 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA23__USDHC2_DATA3 0x0174 0x0400 0x0000 8 0 +#define MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0178 0x0404 0x0000 0 0 +#define MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x0178 0x0404 0x0670 1 2 +#define MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK 0x0178 0x0404 0x0000 2 0 +#define MX6UL_PAD_NAND_RE_B__KPP_ROW00 0x0178 0x0404 0x0000 3 0 +#define MX6UL_PAD_NAND_RE_B__EIM_EB_B00 0x0178 0x0404 0x0000 4 0 +#define MX6UL_PAD_NAND_RE_B__GPIO4_IO00 0x0178 0x0404 0x0000 5 0 +#define MX6UL_PAD_NAND_RE_B__ECSPI3_SS2 0x0178 0x0404 0x0000 8 0 +#define MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x017C 0x0408 0x0000 0 0 +#define MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x017C 0x0408 0x0678 1 2 +#define MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B 0x017C 0x0408 0x0000 2 0 +#define MX6UL_PAD_NAND_WE_B__KPP_COL00 0x017C 0x0408 0x0000 3 0 +#define MX6UL_PAD_NAND_WE_B__EIM_EB_B01 0x017C 0x0408 0x0000 4 0 +#define MX6UL_PAD_NAND_WE_B__GPIO4_IO01 0x017C 0x0408 0x0000 5 0 +#define MX6UL_PAD_NAND_WE_B__ECSPI3_SS3 0x017C 0x0408 0x0000 8 0 +#define MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0180 0x040C 0x0000 0 0 +#define MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x0180 0x040C 0x067C 1 2 +#define MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B 0x0180 0x040C 0x0000 2 0 +#define MX6UL_PAD_NAND_DATA00__KPP_ROW01 0x0180 0x040C 0x0000 3 0 +#define MX6UL_PAD_NAND_DATA00__EIM_AD08 0x0180 0x040C 0x0000 4 0 +#define MX6UL_PAD_NAND_DATA00__GPIO4_IO02 0x0180 0x040C 0x0000 5 0 +#define MX6UL_PAD_NAND_DATA00__ECSPI4_RDY 0x0180 0x040C 0x0000 8 0 +#define MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0184 0x0410 0x0000 0 0 +#define MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x0184 0x0410 0x0680 1 2 +#define MX6UL_PAD_NAND_DATA01__QSPI_B_DQS 0x0184 0x0410 0x0000 2 0 +#define MX6UL_PAD_NAND_DATA01__KPP_COL01 0x0184 0x0410 0x0000 3 0 +#define MX6UL_PAD_NAND_DATA01__EIM_AD09 0x0184 0x0410 0x0000 4 0 +#define MX6UL_PAD_NAND_DATA01__GPIO4_IO03 0x0184 0x0410 0x0000 5 0 +#define MX6UL_PAD_NAND_DATA01__ECSPI4_SS1 0x0184 0x0410 0x0000 8 0 +#define MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0188 0x0414 0x0000 0 0 +#define MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x0188 0x0414 0x0684 1 1 +#define MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00 0x0188 0x0414 0x0000 2 0 +#define MX6UL_PAD_NAND_DATA02__KPP_ROW02 0x0188 0x0414 0x0000 3 0 +#define MX6UL_PAD_NAND_DATA02__EIM_AD10 0x0188 0x0414 0x0000 4 0 +#define MX6UL_PAD_NAND_DATA02__GPIO4_IO04 0x0188 0x0414 0x0000 5 0 +#define MX6UL_PAD_NAND_DATA02__ECSPI4_SS2 0x0188 0x0414 0x0000 8 0 +#define MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x018C 0x0418 0x0000 0 0 +#define MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x018C 0x0418 0x0688 1 2 +#define MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01 0x018C 0x0418 0x0000 2 0 +#define MX6UL_PAD_NAND_DATA03__KPP_COL02 0x018C 0x0418 0x0000 3 0 +#define MX6UL_PAD_NAND_DATA03__EIM_AD11 0x018C 0x0418 0x0000 4 0 +#define MX6UL_PAD_NAND_DATA03__GPIO4_IO05 0x018C 0x0418 0x0000 5 0 +#define MX6UL_PAD_NAND_DATA03__ECSPI4_SS3 0x018C 0x0418 0x0000 8 0 +#define MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0190 0x041C 0x0000 0 0 +#define MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x0190 0x041C 0x068C 1 1 +#define MX6UL_PAD_NAND_DATA04__QSPI_B_DATA02 0x0190 0x041C 0x0000 2 0 +#define MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK 0x0190 0x041C 0x0564 3 1 +#define MX6UL_PAD_NAND_DATA04__EIM_AD12 0x0190 0x041C 0x0000 4 0 +#define MX6UL_PAD_NAND_DATA04__GPIO4_IO06 0x0190 0x041C 0x0000 5 0 +#define MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x0190 0x041C 0x0000 8 0 +#define MX6UL_PAD_NAND_DATA04__UART2_DTE_RX 0x0190 0x041C 0x062C 8 2 +#define MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0194 0x0420 0x0000 0 0 +#define MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x0194 0x0420 0x0690 1 1 +#define MX6UL_PAD_NAND_DATA05__QSPI_B_DATA03 0x0194 0x0420 0x0000 2 0 +#define MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI 0x0194 0x0420 0x056C 3 1 +#define MX6UL_PAD_NAND_DATA05__EIM_AD13 0x0194 0x0420 0x0000 4 0 +#define MX6UL_PAD_NAND_DATA05__GPIO4_IO07 0x0194 0x0420 0x0000 5 0 +#define MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x0194 0x0420 0x062C 8 3 +#define MX6UL_PAD_NAND_DATA05__UART2_DTE_TX 0x0194 0x0420 0x0000 8 0 +#define MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0198 0x0424 0x0000 0 0 +#define MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x0198 0x0424 0x0694 1 1 +#define MX6UL_PAD_NAND_DATA06__SAI2_RX_BCLK 0x0198 0x0424 0x0000 2 0 +#define MX6UL_PAD_NAND_DATA06__ECSPI4_MISO 0x0198 0x0424 0x0568 3 1 +#define MX6UL_PAD_NAND_DATA06__EIM_AD14 0x0198 0x0424 0x0000 4 0 +#define MX6UL_PAD_NAND_DATA06__GPIO4_IO08 0x0198 0x0424 0x0000 5 0 +#define MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x0198 0x0424 0x0000 8 0 +#define MX6UL_PAD_NAND_DATA06__UART2_DTE_RTS 0x0198 0x0424 0x0628 8 4 +#define MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x019C 0x0428 0x0000 0 0 +#define MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x019C 0x0428 0x0698 1 1 +#define MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B 0x019C 0x0428 0x0000 2 0 +#define MX6UL_PAD_NAND_DATA07__ECSPI4_SS0 0x019C 0x0428 0x0000 3 0 +#define MX6UL_PAD_NAND_DATA07__EIM_AD15 0x019C 0x0428 0x0000 4 0 +#define MX6UL_PAD_NAND_DATA07__GPIO4_IO09 0x019C 0x0428 0x0000 5 0 +#define MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x019C 0x0428 0x0628 8 5 +#define MX6UL_PAD_NAND_DATA07__UART2_DTE_CTS 0x019C 0x0428 0x0000 8 0 +#define MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x01A0 0x042C 0x0000 0 0 +#define MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x01A0 0x042C 0x0000 1 0 +#define MX6UL_PAD_NAND_ALE__QSPI_A_DQS 0x01A0 0x042C 0x0000 2 0 +#define MX6UL_PAD_NAND_ALE__PWM3_OUT 0x01A0 0x042C 0x0000 3 0 +#define MX6UL_PAD_NAND_ALE__EIM_ADDR17 0x01A0 0x042C 0x0000 4 0 +#define MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x01A0 0x042C 0x0000 5 0 +#define MX6UL_PAD_NAND_ALE__ECSPI3_SS1 0x01A0 0x042C 0x0000 8 0 +#define MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x01A4 0x0430 0x0000 0 0 +#define MX6UL_PAD_NAND_WP_B__USDHC1_RESET_B 0x01A4 0x0430 0x0000 1 0 +#define MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x01A4 0x0430 0x0000 2 0 +#define MX6UL_PAD_NAND_WP_B__PWM4_OUT 0x01A4 0x0430 0x0000 3 0 +#define MX6UL_PAD_NAND_WP_B__EIM_BCLK 0x01A4 0x0430 0x0000 4 0 +#define MX6UL_PAD_NAND_WP_B__GPIO4_IO11 0x01A4 0x0430 0x0000 5 0 +#define MX6UL_PAD_NAND_WP_B__ECSPI3_RDY 0x01A4 0x0430 0x0000 8 0 +#define MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x01A8 0x0434 0x0000 0 0 +#define MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x01A8 0x0434 0x0000 1 0 +#define MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x01A8 0x0434 0x0000 2 0 +#define MX6UL_PAD_NAND_READY_B__ECSPI3_SS0 0x01A8 0x0434 0x0000 3 0 +#define MX6UL_PAD_NAND_READY_B__EIM_CS1_B 0x01A8 0x0434 0x0000 4 0 +#define MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x01A8 0x0434 0x0000 5 0 +#define MX6UL_PAD_NAND_READY_B__UART3_DCE_TX 0x01A8 0x0434 0x0000 8 0 +#define MX6UL_PAD_NAND_READY_B__UART3_DTE_RX 0x01A8 0x0434 0x0634 8 2 +#define MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x01AC 0x0438 0x0000 0 0 +#define MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x01AC 0x0438 0x0000 1 0 +#define MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x01AC 0x0438 0x0000 2 0 +#define MX6UL_PAD_NAND_CE0_B__ECSPI3_SCLK 0x01AC 0x0438 0x0554 3 1 +#define MX6UL_PAD_NAND_CE0_B__EIM_DTACK_B 0x01AC 0x0438 0x0000 4 0 +#define MX6UL_PAD_NAND_CE0_B__GPIO4_IO13 0x01AC 0x0438 0x0000 5 0 +#define MX6UL_PAD_NAND_CE0_B__UART3_DCE_RX 0x01AC 0x0438 0x0634 8 3 +#define MX6UL_PAD_NAND_CE0_B__UART3_DTE_TX 0x01AC 0x0438 0x0000 8 0 +#define MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0x01B0 0x043C 0x0000 0 0 +#define MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x01B0 0x043C 0x0000 1 0 +#define MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x01B0 0x043C 0x0000 2 0 +#define MX6UL_PAD_NAND_CE1_B__ECSPI3_MOSI 0x01B0 0x043C 0x055C 3 1 +#define MX6UL_PAD_NAND_CE1_B__EIM_ADDR18 0x01B0 0x043C 0x0000 4 0 +#define MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x01B0 0x043C 0x0000 5 0 +#define MX6UL_PAD_NAND_CE1_B__UART3_DCE_CTS 0x01B0 0x043C 0x0000 8 0 +#define MX6UL_PAD_NAND_CE1_B__UART3_DTE_RTS 0x01B0 0x043C 0x0630 8 2 +#define MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x01B4 0x0440 0x0000 0 0 +#define MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x01B4 0x0440 0x0000 1 0 +#define MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x01B4 0x0440 0x0000 2 0 +#define MX6UL_PAD_NAND_CLE__ECSPI3_MISO 0x01B4 0x0440 0x0558 3 1 +#define MX6UL_PAD_NAND_CLE__EIM_ADDR16 0x01B4 0x0440 0x0000 4 0 +#define MX6UL_PAD_NAND_CLE__GPIO4_IO15 0x01B4 0x0440 0x0000 5 0 +#define MX6UL_PAD_NAND_CLE__UART3_DCE_RTS 0x01B4 0x0440 0x0630 8 3 +#define MX6UL_PAD_NAND_CLE__UART3_DTE_CTS 0x01B4 0x0440 0x0000 8 0 +#define MX6UL_PAD_NAND_DQS__RAWNAND_DQS 0x01B8 0x0444 0x0000 0 0 +#define MX6UL_PAD_NAND_DQS__CSI_FIELD 0x01B8 0x0444 0x0530 1 1 +#define MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x01B8 0x0444 0x0000 2 0 +#define MX6UL_PAD_NAND_DQS__PWM5_OUT 0x01B8 0x0444 0x0000 3 0 +#define MX6UL_PAD_NAND_DQS__EIM_WAIT 0x01B8 0x0444 0x0000 4 0 +#define MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x01B8 0x0444 0x0000 5 0 +#define MX6UL_PAD_NAND_DQS__SDMA_EXT_EVENT01 0x01B8 0x0444 0x0000 6 0 +#define MX6UL_PAD_NAND_DQS__SPDIF_EXT_CLK 0x01B8 0x0444 0x0000 8 0 +#define MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x01BC 0x0448 0x0000 0 0 +#define MX6UL_PAD_SD1_CMD__GPT2_COMPARE1 0x01BC 0x0448 0x0000 1 0 +#define MX6UL_PAD_SD1_CMD__SAI2_RX_SYNC 0x01BC 0x0448 0x0000 2 0 +#define MX6UL_PAD_SD1_CMD__SPDIF_OUT 0x01BC 0x0448 0x0000 3 0 +#define MX6UL_PAD_SD1_CMD__EIM_ADDR19 0x01BC 0x0448 0x0000 4 0 +#define MX6UL_PAD_SD1_CMD__GPIO2_IO16 0x01BC 0x0448 0x0000 5 0 +#define MX6UL_PAD_SD1_CMD__SDMA_EXT_EVENT00 0x01BC 0x0448 0x0000 6 0 +#define MX6UL_PAD_SD1_CMD__USB_OTG1_PWR 0x01BC 0x0448 0x0000 8 0 +#define MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x01C0 0x044C 0x0000 0 0 +#define MX6UL_PAD_SD1_CLK__GPT2_COMPARE2 0x01C0 0x044C 0x0000 1 0 +#define MX6UL_PAD_SD1_CLK__SAI2_MCLK 0x01C0 0x044C 0x0000 2 0 +#define MX6UL_PAD_SD1_CLK__SPDIF_IN 0x01C0 0x044C 0x0618 3 3 +#define MX6UL_PAD_SD1_CLK__EIM_ADDR20 0x01C0 0x044C 0x0000 4 0 +#define MX6UL_PAD_SD1_CLK__GPIO2_IO17 0x01C0 0x044C 0x0000 5 0 +#define MX6UL_PAD_SD1_CLK__USB_OTG1_OC 0x01C0 0x044C 0x0000 8 0 +#define MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x01C4 0x0450 0x0000 0 0 +#define MX6UL_PAD_SD1_DATA0__GPT2_COMPARE3 0x01C4 0x0450 0x0000 1 0 +#define MX6UL_PAD_SD1_DATA0__SAI2_TX_SYNC 0x01C4 0x0450 0x05FC 2 1 +#define MX6UL_PAD_SD1_DATA0__FLEXCAN1_TX 0x01C4 0x0450 0x0000 3 0 +#define MX6UL_PAD_SD1_DATA0__EIM_ADDR21 0x01C4 0x0450 0x0000 4 0 +#define MX6UL_PAD_SD1_DATA0__GPIO2_IO18 0x01C4 0x0450 0x0000 5 0 +#define MX6UL_PAD_SD1_DATA0__ANATOP_OTG1_ID 0x01C4 0x0450 0x0000 8 0 +#define MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x01C8 0x0454 0x0000 0 0 +#define MX6UL_PAD_SD1_DATA1__GPT2_CLK 0x01C8 0x0454 0x05A0 1 1 +#define MX6UL_PAD_SD1_DATA1__SAI2_TX_BCLK 0x01C8 0x0454 0x05F8 2 1 +#define MX6UL_PAD_SD1_DATA1__FLEXCAN1_RX 0x01C8 0x0454 0x0584 3 3 +#define MX6UL_PAD_SD1_DATA1__EIM_ADDR22 0x01C8 0x0454 0x0000 4 0 +#define MX6UL_PAD_SD1_DATA1__GPIO2_IO19 0x01C8 0x0454 0x0000 5 0 +#define MX6UL_PAD_SD1_DATA1__USB_OTG2_PWR 0x01C8 0x0454 0x0000 8 0 +#define MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x01CC 0x0458 0x0000 0 0 +#define MX6UL_PAD_SD1_DATA2__GPT2_CAPTURE1 0x01CC 0x0458 0x0598 1 1 +#define MX6UL_PAD_SD1_DATA2__SAI2_RX_DATA 0x01CC 0x0458 0x05F4 2 1 +#define MX6UL_PAD_SD1_DATA2__FLEXCAN2_TX 0x01CC 0x0458 0x0000 3 0 +#define MX6UL_PAD_SD1_DATA2__EIM_ADDR23 0x01CC 0x0458 0x0000 4 0 +#define MX6UL_PAD_SD1_DATA2__GPIO2_IO20 0x01CC 0x0458 0x0000 5 0 +#define MX6UL_PAD_SD1_DATA2__CCM_CLKO1 0x01CC 0x0458 0x0000 6 0 +#define MX6UL_PAD_SD1_DATA2__USB_OTG2_OC 0x01CC 0x0458 0x0000 8 0 +#define MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x01D0 0x045C 0x0000 0 0 +#define MX6UL_PAD_SD1_DATA3__GPT2_CAPTURE2 0x01D0 0x045C 0x059C 1 1 +#define MX6UL_PAD_SD1_DATA3__SAI2_TX_DATA 0x01D0 0x045C 0x0000 2 0 +#define MX6UL_PAD_SD1_DATA3__FLEXCAN2_RX 0x01D0 0x045C 0x0588 3 3 +#define MX6UL_PAD_SD1_DATA3__EIM_ADDR24 0x01D0 0x045C 0x0000 4 0 +#define MX6UL_PAD_SD1_DATA3__GPIO2_IO21 0x01D0 0x045C 0x0000 5 0 +#define MX6UL_PAD_SD1_DATA3__CCM_CLKO2 0x01D0 0x045C 0x0000 6 0 +#define MX6UL_PAD_SD1_DATA3__ANATOP_OTG2_ID 0x01D0 0x045C 0x0000 8 0 +#define MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x01D4 0x0460 0x0000 0 0 +#define MX6UL_PAD_CSI_MCLK__USDHC2_CD_B 0x01D4 0x0460 0x0674 1 0 +#define MX6UL_PAD_CSI_MCLK__RAWNAND_CE2_B 0x01D4 0x0460 0x0000 2 0 +#define MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x01D4 0x0460 0x05A8 3 0 +#define MX6UL_PAD_CSI_MCLK__EIM_CS0_B 0x01D4 0x0460 0x0000 4 0 +#define MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x01D4 0x0460 0x0000 5 0 +#define MX6UL_PAD_CSI_MCLK__SNVS_HP_VIO_5_CTL 0x01D4 0x0460 0x0000 6 0 +#define MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x01D4 0x0460 0x0000 8 0 +#define MX6UL_PAD_CSI_MCLK__UART6_DTE_RX 0x01D4 0x0460 0x064C 8 0 +#define MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x01D8 0x0464 0x0528 0 1 +#define MX6UL_PAD_CSI_PIXCLK__USDHC2_WP 0x01D8 0x0464 0x069C 1 2 +#define MX6UL_PAD_CSI_PIXCLK__RAWNAND_CE3_B 0x01D8 0x0464 0x0000 2 0 +#define MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x01D8 0x0464 0x05A4 3 2 +#define MX6UL_PAD_CSI_PIXCLK__EIM_OE 0x01D8 0x0464 0x0000 4 0 +#define MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x01D8 0x0464 0x0000 5 0 +#define MX6UL_PAD_CSI_PIXCLK__SNVS_HP_VIO_5 0x01D8 0x0464 0x0000 6 0 +#define MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x01D8 0x0464 0x064C 8 3 +#define MX6UL_PAD_CSI_PIXCLK__UART6_DTE_TX 0x01D8 0x0464 0x0000 8 0 +#define MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x01DC 0x0468 0x052C 0 0 +#define MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x01DC 0x0468 0x0670 1 0 +#define MX6UL_PAD_CSI_VSYNC__SIM1_PORT1_CLK 0x01DC 0x0468 0x0000 2 0 +#define MX6UL_PAD_CSI_VSYNC__I2C2_SDA 0x01DC 0x0468 0x05B0 3 0 +#define MX6UL_PAD_CSI_VSYNC__EIM_RW 0x01DC 0x0468 0x0000 4 0 +#define MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x01DC 0x0468 0x0000 5 0 +#define MX6UL_PAD_CSI_VSYNC__PWM7_OUT 0x01DC 0x0468 0x0000 6 0 +#define MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS 0x01DC 0x0468 0x0648 8 0 +#define MX6UL_PAD_CSI_VSYNC__UART6_DTE_CTS 0x01DC 0x0468 0x0000 8 0 +#define MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x01E0 0x046C 0x0524 0 0 +#define MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x01E0 0x046C 0x0678 1 0 +#define MX6UL_PAD_CSI_HSYNC__SIM1_PORT1_PD 0x01E0 0x046C 0x0000 2 0 +#define MX6UL_PAD_CSI_HSYNC__I2C2_SCL 0x01E0 0x046C 0x05AC 3 0 +#define MX6UL_PAD_CSI_HSYNC__EIM_LBA_B 0x01E0 0x046C 0x0000 4 0 +#define MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x01E0 0x046C 0x0000 5 0 +#define MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x01E0 0x046C 0x0000 6 0 +#define MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS 0x01E0 0x046C 0x0000 8 0 +#define MX6UL_PAD_CSI_HSYNC__UART6_DTE_RTS 0x01E0 0x046C 0x0648 8 1 +#define MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x01E4 0x0470 0x04C4 0 0 +#define MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x01E4 0x0470 0x067C 1 0 +#define MX6UL_PAD_CSI_DATA00__SIM1_PORT1_RST_B 0x01E4 0x0470 0x0000 2 0 +#define MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x01E4 0x0470 0x0544 3 0 +#define MX6UL_PAD_CSI_DATA00__EIM_AD00 0x01E4 0x0470 0x0000 4 0 +#define MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x01E4 0x0470 0x0000 5 0 +#define MX6UL_PAD_CSI_DATA00__SRC_INT_BOOT 0x01E4 0x0470 0x0000 6 0 +#define MX6UL_PAD_CSI_DATA00__UART5_DCE_TX 0x01E4 0x0470 0x0000 8 0 +#define MX6UL_PAD_CSI_DATA00__UART5_DTE_RX 0x01E4 0x0470 0x0644 8 0 +#define MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x01E8 0x0474 0x04C8 0 0 +#define MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x01E8 0x0474 0x0680 1 0 +#define MX6UL_PAD_CSI_DATA01__SIM1_PORT1_SVEN 0x01E8 0x0474 0x0000 2 0 +#define MX6UL_PAD_CSI_DATA01__ECSPI2_SS0 0x01E8 0x0474 0x0000 3 0 +#define MX6UL_PAD_CSI_DATA01__EIM_AD01 0x01E8 0x0474 0x0000 4 0 +#define MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x01E8 0x0474 0x0000 5 0 +#define MX6UL_PAD_CSI_DATA01__SAI1_MCLK 0x01E8 0x0474 0x0000 6 0 +#define MX6UL_PAD_CSI_DATA01__UART5_DCE_RX 0x01E8 0x0474 0x0644 8 1 +#define MX6UL_PAD_CSI_DATA01__UART5_DTE_TX 0x01E8 0x0474 0x0000 8 0 +#define MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x01EC 0x0478 0x04D8 0 1 +#define MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x01EC 0x0478 0x0684 1 2 +#define MX6UL_PAD_CSI_DATA02__SIM1_PORT1_TRXD 0x01EC 0x0478 0x0000 2 0 +#define MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x01EC 0x0478 0x054C 3 1 +#define MX6UL_PAD_CSI_DATA02__EIM_AD02 0x01EC 0x0478 0x0000 4 0 +#define MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x01EC 0x0478 0x0000 5 0 +#define MX6UL_PAD_CSI_DATA02__SAI1_RX_SYNC 0x01EC 0x0478 0x0000 6 0 +#define MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS 0x01EC 0x0478 0x0640 8 5 +#define MX6UL_PAD_CSI_DATA02__UART5_DTE_CTS 0x01EC 0x0478 0x0000 8 0 +#define MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x01F0 0x047C 0x04CC 0 0 +#define MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x01F0 0x047C 0x0688 1 0 +#define MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0x01F0 0x047C 0x0000 2 0 +#define MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x01F0 0x047C 0x0548 3 0 +#define MX6UL_PAD_CSI_DATA03__EIM_AD03 0x01F0 0x047C 0x0000 4 0 +#define MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x01F0 0x047C 0x0000 5 0 +#define MX6UL_PAD_CSI_DATA03__SAI1_RX_BCLK 0x01F0 0x047C 0x0000 6 0 +#define MX6UL_PAD_CSI_DATA03__UART5_DCE_CTS 0x01F0 0x047C 0x0000 8 0 +#define MX6UL_PAD_CSI_DATA03__UART5_DTE_RTS 0x01F0 0x047C 0x0640 8 0 +#define MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x01F4 0x0480 0x04DC 0 1 +#define MX6UL_PAD_CSI_DATA04__USDHC2_DATA4 0x01F4 0x0480 0x068C 1 2 +#define MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x01F4 0x0480 0x0000 2 0 +#define MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x01F4 0x0480 0x0534 3 1 +#define MX6UL_PAD_CSI_DATA04__EIM_AD04 0x01F4 0x0480 0x0000 4 0 +#define MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x01F4 0x0480 0x0000 5 0 +#define MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x01F4 0x0480 0x05EC 6 1 +#define MX6UL_PAD_CSI_DATA04__USDHC1_WP 0x01F4 0x0480 0x0000 8 0 +#define MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x01F8 0x0484 0x04E0 0 1 +#define MX6UL_PAD_CSI_DATA05__USDHC2_DATA5 0x01F8 0x0484 0x0690 1 2 +#define MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0x01F8 0x0484 0x0000 2 0 +#define MX6UL_PAD_CSI_DATA05__ECSPI1_SS0 0x01F8 0x0484 0x0000 3 0 +#define MX6UL_PAD_CSI_DATA05__EIM_AD05 0x01F8 0x0484 0x0000 4 0 +#define MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x01F8 0x0484 0x0000 5 0 +#define MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x01F8 0x0484 0x05E8 6 1 +#define MX6UL_PAD_CSI_DATA05__USDHC1_CD_B 0x01F8 0x0484 0x0000 8 0 +#define MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x01FC 0x0488 0x04E4 0 1 +#define MX6UL_PAD_CSI_DATA06__USDHC2_DATA6 0x01FC 0x0488 0x0694 1 2 +#define MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0x01FC 0x0488 0x0000 2 0 +#define MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x01FC 0x0488 0x053C 3 1 +#define MX6UL_PAD_CSI_DATA06__EIM_AD06 0x01FC 0x0488 0x0000 4 0 +#define MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x01FC 0x0488 0x0000 5 0 +#define MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x01FC 0x0488 0x0000 6 0 +#define MX6UL_PAD_CSI_DATA06__USDHC1_RESET_B 0x01FC 0x0488 0x0000 8 0 +#define MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x0200 0x048C 0x04E8 0 1 +#define MX6UL_PAD_CSI_DATA07__USDHC2_DATA7 0x0200 0x048C 0x0698 1 2 +#define MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0x0200 0x048C 0x0000 2 0 +#define MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x0200 0x048C 0x0538 3 1 +#define MX6UL_PAD_CSI_DATA07__EIM_AD07 0x0200 0x048C 0x0000 4 0 +#define MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x0200 0x048C 0x0000 5 0 +#define MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x0200 0x048C 0x0000 6 0 +#define MX6UL_PAD_CSI_DATA07__USDHC1_VSELECT 0x0200 0x048C 0x0000 8 0 + +#endif /* __DTS_IMX6UL_PINFUNC_H */ -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH 5/8] ARM: dts: add i.mx6ul pin function include file 2015-06-17 15:39 ` [PATCH 5/8] ARM: dts: add i.mx6ul pin function include file Frank.Li-KZfg59tc24xl57MIdRCFDg @ 2015-07-09 3:09 ` Shawn Guo 0 siblings, 0 replies; 16+ messages in thread From: Shawn Guo @ 2015-07-09 3:09 UTC (permalink / raw) To: Frank.Li Cc: linux-arm-kernel, shawn.guo, linus.walleij, lznuaa, devicetree, linux-gpio, robh+dt, Anson Huang, Bai Ping On Wed, Jun 17, 2015 at 11:39:26PM +0800, Frank.Li@freescale.com wrote: > From: Frank Li <Frank.Li@freescale.com> > > add pin mux define file > > Signed-off-by: Bai Ping <b51503@freescale.com> > Signed-off-by: Anson Huang <b20788@freescale.com> > Signed-off-by: Frank Li <Frank.Li@freescale.com> > --- > arch/arm/boot/dts/imx6ul-pinfunc.h | 938 +++++++++++++++++++++++++++++++++++++ > 1 file changed, 938 insertions(+) > create mode 100644 arch/arm/boot/dts/imx6ul-pinfunc.h > > diff --git a/arch/arm/boot/dts/imx6ul-pinfunc.h b/arch/arm/boot/dts/imx6ul-pinfunc.h > new file mode 100644 > index 0000000..1bb774b9 > --- /dev/null > +++ b/arch/arm/boot/dts/imx6ul-pinfunc.h > @@ -0,0 +1,938 @@ > +/* > + * Copyright (C) 2015 Freescale Semiconductor, Inc. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > + */ > + > +#ifndef __DTS_IMX6UL_PINFUNC_H > +#define __DTS_IMX6UL_PINFUNC_H > + > +/* > + * The pin function ID is a tuple of > + * <mux_reg conf_reg input_reg mux_mode input_val> > + */ > +#define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x0014 0x02A0 0x0000 5 0 Please use space instead of tab between #define and macro. And if possible, please change your scripts to use lowercase in hex value, so that we are consistent with other i.MX pinfunc headers. Shawn ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 6/8] ARM: dts: imx: add imx6ul and imx6ul evk board support [not found] ` <1434555569-8237-1-git-send-email-Frank.Li-KZfg59tc24xl57MIdRCFDg@public.gmane.org> 2015-06-17 15:39 ` [PATCH 2/8] ARM: imx: add imx6ul clk tree support Frank.Li-KZfg59tc24xl57MIdRCFDg 2015-06-17 15:39 ` [PATCH 5/8] ARM: dts: add i.mx6ul pin function include file Frank.Li-KZfg59tc24xl57MIdRCFDg @ 2015-06-17 15:39 ` Frank.Li-KZfg59tc24xl57MIdRCFDg 2015-06-18 5:50 ` Sascha Hauer 2015-07-09 7:02 ` Shawn Guo 2015-06-17 15:39 ` [PATCH 7/8] ARM: imx: imx_v6_v7_defconfig enable imx6ul support Frank.Li-KZfg59tc24xl57MIdRCFDg 2015-06-17 15:39 ` [PATCH 8/8] ARM: imx: add low-level debug support for i.mx6ul Frank.Li-KZfg59tc24xl57MIdRCFDg 4 siblings, 2 replies; 16+ messages in thread From: Frank.Li-KZfg59tc24xl57MIdRCFDg @ 2015-06-17 15:39 UTC (permalink / raw) To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, shawn.guo-QSEj5FYQhm4dnm+yROfE0A, shawnguo-DgEjT+Ai2ygdnm+yROfE0A, linus.walleij-QSEj5FYQhm4dnm+yROfE0A, lznuaa-Re5JQEeQqe8AvxtiuMwx3w Cc: linux-gpio-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A, devicetree-u79uwXL29TY76Z2rM5mHXA, Frank Li, Anson Huang, Fugang Duan, Fancy Fang From: Frank Li <Frank.Li-KZfg59tc24xl57MIdRCFDg@public.gmane.org> Add new SOC i.MX6UL dtb file support, including evk board support i.MX6 Ultralite processor include one ARM cortext-A7 core. Offer high perfomance and lowest power consumption. Main included: - 4 MMC/SD/SDIO - 2 USB 2.0 OTG - 3 I2S/SAI/AC97 - 4 eCSPI - 4 I2C - 2 ENET - 2 CAN - 3 wdog - ASRC - 8 uart - LCDIF - PXP Signed-off-by: Anson Huang <b20788-KZfg59tc24xl57MIdRCFDg@public.gmane.org> Signed-off-by: Fugang Duan <B38611-KZfg59tc24xl57MIdRCFDg@public.gmane.org> Signed-off-by: Fancy Fang <chen.fang-KZfg59tc24xl57MIdRCFDg@public.gmane.org> Signed-off-by: Frank Li <Frank.Li-KZfg59tc24xl57MIdRCFDg@public.gmane.org> --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/imx6ul-14x14-evk.dts | 337 +++++++++++++++++ arch/arm/boot/dts/imx6ul.dtsi | 645 +++++++++++++++++++++++++++++++++ 3 files changed, 984 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ul-14x14-evk.dts create mode 100644 arch/arm/boot/dts/imx6ul.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 246473a..7c2fd63 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -331,6 +331,8 @@ dtb-$(CONFIG_SOC_IMX6SX) += \ imx6sx-sabreauto.dtb \ imx6sx-sdb-reva.dtb \ imx6sx-sdb.dtb +dtb-$(CONFIG_SOC_IMX6UL) += \ + imx6ul-14x14-evk.dtb dtb-$(CONFIG_SOC_IMX7D) += \ imx7d-sdb.dtb dtb-$(CONFIG_SOC_LS1021A) += \ diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dts b/arch/arm/boot/dts/imx6ul-14x14-evk.dts new file mode 100644 index 0000000..449b5d3 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dts @@ -0,0 +1,337 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include "imx6ul.dtsi" + +/ { + model = "Freescale i.MX6 UltraLite 14x14 EVK Board"; + compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul"; + + chosen { + stdout-path = &uart1; + }; + + memory { + reg = <0x80000000 0x20000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_sd1_vmmc: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; +}; + +&cpu0 { + arm-supply = <®_arm>; + soc-supply = <®_soc>; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + fsl,uart-has-rtscts; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart2dte>; */ + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio1 19 0>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; + keep-power-in-suspend; + enable-sdio-wakeup; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + imx6ul-evk { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ + MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ + >; + }; + + pinctrl_csi1: csi1grp { + fsl,pins = < + MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 + MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 + MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 + MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088 + MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088 + MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088 + MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088 + MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088 + MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088 + MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088 + MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088 + MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x80000000 + >; + }; + + pinctrl_flexcan1: flexcan1grp{ + fsl,pins = < + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2grp{ + fsl,pins = < + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 + /* used for lcd reset */ + MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 + >; + }; + + pinctrl_sim2_1: sim2grp-1 { + fsl,pins = < + MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0xb808 + MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x31 + MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0xb808 + MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb808 + MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb809 + MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 + MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 + >; + }; + + pinctrl_uart2dte: uart2dtegrp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x1b0b1 + MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + >; + }; + + pinctrl_tsc: tscgrp { + fsl,pin = < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 + MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 + MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059 + >; + }; + + pinctrl_spi4: spi4grp { + fsl,pins = < + MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1 + MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1 + MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1 + MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000 + >; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi new file mode 100644 index 0000000..e23a8c7 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -0,0 +1,645 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <dt-bindings/clock/imx6ul-clock.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include "imx6ul-pinfunc.h" +#include "skeleton.dtsi" + +/ { + aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + i2c3 = &i2c4; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + serial5 = &uart6; + serial6 = &uart7; + serial7 = &uart8; + spi0 = &ecspi1; + spi1 = &ecspi2; + spi2 = &ecspi3; + spi3 = &ecspi4; + usbphy0 = &usbphy1; + usbphy1 = &usbphy2; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + clock-latency = <61036>; /* two CLK32 periods */ + operating-points = < + /* kHz uV */ + 528000 1250000 + 396000 1150000 + 198000 1150000 + >; + fsl,soc-operating-points = < + /* KHz uV */ + 528000 1250000 + 396000 1150000 + 198000 1150000 + >; + clocks = <&clks IMX6UL_CLK_ARM>, + <&clks IMX6UL_CLK_PLL2_BUS>, + <&clks IMX6UL_CLK_PLL2_PFD2>, + <&clks IMX6UL_CA7_SECONDARY_SEL>, + <&clks IMX6UL_CLK_STEP>, + <&clks IMX6UL_CLK_PLL1_SW>, + <&clks IMX6UL_CLK_PLL1_SYS>, + <&clks IMX6UL_PLL1_BYPASS>, + <&clks IMX6UL_CLK_PLL1>, + <&clks IMX6UL_PLL1_BYPASS_SRC>, + <&clks IMX6UL_CLK_OSC>; + clock-names = "arm", "pll2_bus", "pll2_pfd2_396m", "secondary_sel", "step", + "pll1_sw", "pll1_sys", "pll1_bypass", "pll1", "pll1_bypass_src", "osc"; + }; + }; + + intc: interrupt-controller@00a01000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x00a01000 0x1000>, + <0x00a02000 0x1000>, + <0x00a04000 0x2000>, + <0x00a06000 0x2000>; + }; + + ckil: clock-cli { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ckil"; + }; + + osc: clock-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc"; + }; + + ipp_di0: clock-di0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "ipp_di0"; + }; + + ipp_di1: clock-di1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "ipp_di1"; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&intc>; + ranges; + + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + aips1: aips-bus@02000000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02000000 0x100000>; + ranges; + + spba-bus@02000000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02000000 0x40000>; + ranges; + + ecspi1: ecspi@02008000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + reg = <0x02008000 0x4000>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_ECSPI1>, + <&clks IMX6UL_CLK_ECSPI1>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi2: ecspi@0200c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + reg = <0x0200c000 0x4000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_ECSPI2>, + <&clks IMX6UL_CLK_ECSPI2>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi3: ecspi@02010000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + reg = <0x02010000 0x4000>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_ECSPI3>, + <&clks IMX6UL_CLK_ECSPI3>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi4: ecspi@02014000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + reg = <0x02014000 0x4000>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_ECSPI4>, + <&clks IMX6UL_CLK_ECSPI4>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart7: serial@02018000 { + compatible = "fsl,imx6ul-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x02018000 0x4000>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_UART7_IPG>, + <&clks IMX6UL_CLK_UART7_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart1: serial@02020000 { + compatible = "fsl,imx6ul-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x02020000 0x4000>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_UART1_IPG>, + <&clks IMX6UL_CLK_UART1_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart8: serial@02024000 { + compatible = "fsl,imx6ul-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x02024000 0x4000>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_UART8_IPG>, + <&clks IMX6UL_CLK_UART8_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + }; + + + pwm1: pwm@02080000 { + compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; + reg = <0x02080000 0x4000>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_PWM1>, + <&clks IMX6UL_CLK_PWM1>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + + pwm2: pwm@02084000 { + compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; + reg = <0x02084000 0x4000>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_DUMMY>, + <&clks IMX6UL_CLK_DUMMY>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + + pwm3: pwm@02088000 { + compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; + reg = <0x02088000 0x4000>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_DUMMY>, + <&clks IMX6UL_CLK_DUMMY>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + + pwm4: pwm@0208c000 { + compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; + reg = <0x0208c000 0x4000>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_DUMMY>, + <&clks IMX6UL_CLK_DUMMY>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + + gpt1: gpt@02098000 { + compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt"; + reg = <0x02098000 0x4000>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_GPT1_BUS>, + <&clks IMX6UL_CLK_GPT1_SERIAL>; + clock-names = "ipg", "per"; + }; + + gpio1: gpio@0209c000 { + compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; + reg = <0x0209c000 0x4000>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@020a0000 { + compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; + reg = <0x020a0000 0x4000>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@020a4000 { + compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; + reg = <0x020a4000 0x4000>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@020a8000 { + compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; + reg = <0x020a8000 0x4000>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio@020ac000 { + compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; + reg = <0x020ac000 0x4000>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + wdog1: wdog@020bc000 { + compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; + reg = <0x020bc000 0x4000>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_WDOG1>; + }; + + wdog2: wdog@020c0000 { + compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; + reg = <0x020c0000 0x4000>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_WDOG2>; + status = "disabled"; + }; + + clks: ccm@020c4000 { + compatible = "fsl,imx6ul-ccm"; + reg = <0x020c4000 0x4000>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; + #clock-cells = <1>; + clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; + clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; + }; + + anatop: anatop@020c8000 { + compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop", + "syscon", "simple-bus"; + reg = <0x020c8000 0x1000>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + + reg_3p0: regulator-3p0@120 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vdd3p0"; + regulator-min-microvolt = <2625000>; + regulator-max-microvolt = <3400000>; + anatop-reg-offset = <0x120>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <0>; + anatop-min-voltage = <2625000>; + anatop-max-voltage = <3400000>; + anatop-enable-bit = <0>; + }; + + reg_arm: regulator-vddcore@140 { + compatible = "fsl,anatop-regulator"; + regulator-name = "cpu"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1450000>; + regulator-always-on; + anatop-reg-offset = <0x140>; + anatop-vol-bit-shift = <0>; + anatop-vol-bit-width = <5>; + anatop-delay-reg-offset = <0x170>; + anatop-delay-bit-shift = <24>; + anatop-delay-bit-width = <2>; + anatop-min-bit-val = <1>; + anatop-min-voltage = <725000>; + anatop-max-voltage = <1450000>; + }; + + reg_soc: regulator-vddsoc@140 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vddsoc"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1450000>; + regulator-always-on; + anatop-reg-offset = <0x140>; + anatop-vol-bit-shift = <18>; + anatop-vol-bit-width = <5>; + anatop-delay-reg-offset = <0x170>; + anatop-delay-bit-shift = <28>; + anatop-delay-bit-width = <2>; + anatop-min-bit-val = <1>; + anatop-min-voltage = <725000>; + anatop-max-voltage = <1450000>; + }; + }; + + usbphy1: usbphy@020c9000 { + compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; + reg = <0x020c9000 0x1000>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_USBPHY1>; + phy-3p0-supply = <®_3p0>; + fsl,anatop = <&anatop>; + }; + + usbphy2: usbphy@020ca000 { + compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; + reg = <0x020ca000 0x1000>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_USBPHY2>; + phy-3p0-supply = <®_3p0>; + fsl,anatop = <&anatop>; + }; + + epit1: epit@020d0000 { + reg = <0x020d0000 0x4000>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; + }; + + epit2: epit@020d4000 { + reg = <0x020d4000 0x4000>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + }; + + src: src@020d8000 { + compatible = "fsl,imx6ul-src", "fsl,imx51-src"; + reg = <0x020d8000 0x4000>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + #reset-cells = <1>; + }; + + gpc: gpc@020dc000 { + compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc"; + reg = <0x020dc000 0x4000>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + fsl,mf-mix-wakeup-irq = <0x7c00000 0x3d00 0x0 0x1400240>; + }; + + iomuxc: iomuxc@020e0000 { + compatible = "fsl,imx6ul-iomuxc"; + reg = <0x020e0000 0x4000>; + }; + + gpr: iomuxc-gpr@020e4000 { + compatible = "fsl,imx6ul-iomuxc-gpr", "syscon"; + reg = <0x020e4000 0x4000>; + }; + + gpt2: gpt@020e8000 { + compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt"; + reg = <0x020e8000 0x4000>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_DUMMY>, + <&clks IMX6UL_CLK_DUMMY>; + clock-names = "ipg", "per"; + }; + + pwm5: pwm@020f0000 { + compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; + reg = <0x020f0000 0x4000>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_DUMMY>, + <&clks IMX6UL_CLK_DUMMY>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + + pwm6: pwm@020f4000 { + compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; + reg = <0x020f4000 0x4000>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_DUMMY>, + <&clks IMX6UL_CLK_DUMMY>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + + pwm7: pwm@020f8000 { + compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; + reg = <0x020f8000 0x4000>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_DUMMY>, + <&clks IMX6UL_CLK_DUMMY>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + + pwm8: pwm@020fc000 { + compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; + reg = <0x020fc000 0x4000>; + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_DUMMY>, + <&clks IMX6UL_CLK_DUMMY>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + }; + + aips2: aips-bus@02100000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02100000 0x100000>; + ranges; + + usdhc1: usdhc@02190000 { + compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; + reg = <0x02190000 0x4000>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_USDHC1>, + <&clks IMX6UL_CLK_USDHC1>, + <&clks IMX6UL_CLK_USDHC1>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + usdhc2: usdhc@02194000 { + compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; + reg = <0x02194000 0x4000>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_USDHC2>, + <&clks IMX6UL_CLK_USDHC2>, + <&clks IMX6UL_CLK_USDHC2>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + i2c1: i2c@021a0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; + reg = <0x021a0000 0x4000>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_I2C1>; + status = "disabled"; + }; + + i2c2: i2c@021a4000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; + reg = <0x021a4000 0x4000>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_I2C2>; + status = "disabled"; + }; + + i2c3: i2c@021a8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; + reg = <0x021a8000 0x4000>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_I2C3>; + status = "disabled"; + }; + + uart2: serial@021e8000 { + compatible = "fsl,imx6ul-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x021e8000 0x4000>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_UART2_IPG>, + <&clks IMX6UL_CLK_UART2_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart3: serial@021ec000 { + compatible = "fsl,imx6ul-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x021ec000 0x4000>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_UART3_IPG>, + <&clks IMX6UL_CLK_UART3_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart4: serial@021f0000 { + compatible = "fsl,imx6ul-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x021f0000 0x4000>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_UART4_IPG>, + <&clks IMX6UL_CLK_UART4_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart5: serial@021f4000 { + compatible = "fsl,imx6ul-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x021f4000 0x4000>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_UART5_IPG>, + <&clks IMX6UL_CLK_UART5_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + i2c4: i2c@021f8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; + reg = <0x021f8000 0x4000>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_I2C4>; + status = "disabled"; + }; + + uart6: serial@021fc000 { + compatible = "fsl,imx6ul-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x021fc000 0x4000>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_UART6_IPG>, + <&clks IMX6UL_CLK_UART6_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + }; + }; +}; -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH 6/8] ARM: dts: imx: add imx6ul and imx6ul evk board support 2015-06-17 15:39 ` [PATCH 6/8] ARM: dts: imx: add imx6ul and imx6ul evk board support Frank.Li-KZfg59tc24xl57MIdRCFDg @ 2015-06-18 5:50 ` Sascha Hauer 2015-07-09 7:02 ` Shawn Guo 1 sibling, 0 replies; 16+ messages in thread From: Sascha Hauer @ 2015-06-18 5:50 UTC (permalink / raw) To: Frank.Li Cc: linux-arm-kernel, shawn.guo, shawnguo, linus.walleij, lznuaa, linux-gpio, robh+dt, devicetree, Anson Huang, Fugang Duan, Fancy Fang On Wed, Jun 17, 2015 at 11:39:27PM +0800, Frank.Li@freescale.com wrote: > From: Frank Li <Frank.Li@freescale.com> > > +&uart1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart1>; > + status = "okay"; > +}; > + > +&uart2 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart2>; > + fsl,uart-has-rtscts; > + /* for DTE mode, add below change */ > + /* fsl,dte-mode; */ > + /* pinctrl-0 = <&pinctrl_uart2dte>; */ > + status = "okay"; > +}; > + > +&usdhc1 { > + pinctrl-names = "default", "state_100mhz", "state_200mhz"; > + pinctrl-0 = <&pinctrl_usdhc1>; > + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; > + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; > + cd-gpios = <&gpio1 19 0>; Use the correct polarity here. This is probably GPIO_ACTIVE_LOW. > + keep-power-in-suspend; > + enable-sdio-wakeup; > + vmmc-supply = <®_sd1_vmmc>; > + status = "okay"; > +}; > + > +&usdhc2 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_usdhc2>; > + no-1-8-v; > + keep-power-in-suspend; > + enable-sdio-wakeup; > + status = "okay"; > +}; > + > +&iomuxc { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_hog_1>; > + imx6ul-evk { You can put the pinctrl nodes directly under the iomux node since: 5fcdf6a pinctrl: imx: Allow parsing DT without function nodes Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 6/8] ARM: dts: imx: add imx6ul and imx6ul evk board support 2015-06-17 15:39 ` [PATCH 6/8] ARM: dts: imx: add imx6ul and imx6ul evk board support Frank.Li-KZfg59tc24xl57MIdRCFDg 2015-06-18 5:50 ` Sascha Hauer @ 2015-07-09 7:02 ` Shawn Guo 1 sibling, 0 replies; 16+ messages in thread From: Shawn Guo @ 2015-07-09 7:02 UTC (permalink / raw) To: Frank.Li Cc: linux-arm-kernel, shawn.guo, linus.walleij, lznuaa, devicetree, Fancy Fang, linux-gpio, robh+dt, Fugang Duan, Anson Huang On Wed, Jun 17, 2015 at 11:39:27PM +0800, Frank.Li@freescale.com wrote: > From: Frank Li <Frank.Li@freescale.com> > > Add new SOC i.MX6UL dtb file support, including evk board > support > > i.MX6 Ultralite processor include one ARM cortext-A7 core. > Offer high perfomance and lowest power consumption. > > Main included: > - 4 MMC/SD/SDIO > - 2 USB 2.0 OTG > - 3 I2S/SAI/AC97 > - 4 eCSPI > - 4 I2C > - 2 ENET > - 2 CAN > - 3 wdog > - ASRC > - 8 uart > - LCDIF > - PXP > > Signed-off-by: Anson Huang <b20788@freescale.com> > Signed-off-by: Fugang Duan <B38611@freescale.com> > Signed-off-by: Fancy Fang <chen.fang@freescale.com> > Signed-off-by: Frank Li <Frank.Li@freescale.com> > --- > arch/arm/boot/dts/Makefile | 2 + > arch/arm/boot/dts/imx6ul-14x14-evk.dts | 337 +++++++++++++++++ > arch/arm/boot/dts/imx6ul.dtsi | 645 +++++++++++++++++++++++++++++++++ > 3 files changed, 984 insertions(+) > create mode 100644 arch/arm/boot/dts/imx6ul-14x14-evk.dts > create mode 100644 arch/arm/boot/dts/imx6ul.dtsi > > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile > index 246473a..7c2fd63 100644 > --- a/arch/arm/boot/dts/Makefile > +++ b/arch/arm/boot/dts/Makefile > @@ -331,6 +331,8 @@ dtb-$(CONFIG_SOC_IMX6SX) += \ > imx6sx-sabreauto.dtb \ > imx6sx-sdb-reva.dtb \ > imx6sx-sdb.dtb > +dtb-$(CONFIG_SOC_IMX6UL) += \ > + imx6ul-14x14-evk.dtb > dtb-$(CONFIG_SOC_IMX7D) += \ > imx7d-sdb.dtb > dtb-$(CONFIG_SOC_LS1021A) += \ > diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dts b/arch/arm/boot/dts/imx6ul-14x14-evk.dts > new file mode 100644 > index 0000000..449b5d3 > --- /dev/null > +++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dts > @@ -0,0 +1,337 @@ > +/* > + * Copyright (C) 2015 Freescale Semiconductor, Inc. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + */ > + > +/dts-v1/; > + > +#include <dt-bindings/input/input.h> > +#include "imx6ul.dtsi" > + > +/ { > + model = "Freescale i.MX6 UltraLite 14x14 EVK Board"; > + compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul"; > + > + chosen { > + stdout-path = &uart1; > + }; > + > + memory { > + reg = <0x80000000 0x20000000>; > + }; > + > + regulators { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <0>; > + > + reg_sd1_vmmc: regulator@1 { There should be a 'reg' property when unit-address is coded in node name. Also, the numbering starts from 0. > + compatible = "regulator-fixed"; > + regulator-name = "VSD_3V3"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + }; > + }; > +}; > + > +&cpu0 { > + arm-supply = <®_arm>; > + soc-supply = <®_soc>; These two can be the default cases to be put in the <soc>.dtsi, and for the boards with board level supply design, their <board>.dts can overwrite. > +}; > + > +&uart1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart1>; > + status = "okay"; > +}; > + > +&uart2 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart2>; > + fsl,uart-has-rtscts; > + /* for DTE mode, add below change */ > + /* fsl,dte-mode; */ > + /* pinctrl-0 = <&pinctrl_uart2dte>; */ For given board design, whether DTE mode is supported should be determined. Why these commenting? > + status = "okay"; > +}; > + > +&usdhc1 { > + pinctrl-names = "default", "state_100mhz", "state_200mhz"; > + pinctrl-0 = <&pinctrl_usdhc1>; > + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; > + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; > + cd-gpios = <&gpio1 19 0>; > + keep-power-in-suspend; > + enable-sdio-wakeup; > + vmmc-supply = <®_sd1_vmmc>; > + status = "okay"; > +}; > + > +&usdhc2 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_usdhc2>; > + no-1-8-v; > + keep-power-in-suspend; > + enable-sdio-wakeup; > + status = "okay"; > +}; > + > +&iomuxc { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_hog_1>; Have new line between property list and sub-nodes. > + imx6ul-evk { > + pinctrl_hog_1: hoggrp-1 { The suffix "1" makes no sense. Drop it. > + fsl,pins = < > + MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 Should be in the wdog pinctrl? > + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ > + MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ > + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ Should be in the SD1 pinctrl group? > + >; > + }; > + > + pinctrl_csi1: csi1grp { > + fsl,pins = < > + MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 > + MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 > + MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 > + MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088 > + MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088 > + MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088 > + MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088 > + MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088 > + MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088 > + MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088 > + MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088 > + MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088 > + >; > + }; > + > + pinctrl_enet1: enet1grp { > + fsl,pins = < > + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 > + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 > + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 > + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 > + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 > + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 > + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 > + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 > + >; > + }; > + > + pinctrl_enet2: enet2grp { > + fsl,pins = < > + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 > + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 > + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 > + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 > + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 > + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 > + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 > + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 > + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 > + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 > + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x80000000 Do not use 0x80000000 but an explicit pad configuration value. > + >; > + }; > + > + pinctrl_flexcan1: flexcan1grp{ > + fsl,pins = < > + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 > + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 > + >; > + }; > + > + pinctrl_flexcan2: flexcan2grp{ > + fsl,pins = < > + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 > + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 > + >; > + }; > + > + pinctrl_lcdif_dat: lcdifdatgrp { > + fsl,pins = < > + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 > + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 > + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 > + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 > + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 > + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 > + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 > + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 > + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 > + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 > + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 > + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 > + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 > + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 > + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 > + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 > + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 > + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 > + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 > + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 > + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 > + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 > + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 > + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 > + >; > + }; > + > + pinctrl_lcdif_ctrl: lcdifctrlgrp { > + fsl,pins = < > + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 > + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 > + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 > + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 > + /* used for lcd reset */ > + MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 > + >; > + }; > + > + pinctrl_pwm1: pwm1grp { > + fsl,pins = < > + MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 > + >; > + }; > + > + pinctrl_sim2_1: sim2grp-1 { Drop "1" suffix. > + fsl,pins = < > + MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0xb808 > + MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x31 > + MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0xb808 > + MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb808 > + MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb809 > + MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008 > + >; > + }; > + > + pinctrl_uart1: uart1grp { > + fsl,pins = < > + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 > + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 > + >; > + }; > + > + pinctrl_uart2: uart2grp { > + fsl,pins = < > + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 > + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 > + MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 > + MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 > + >; > + }; > + > + pinctrl_uart2dte: uart2dtegrp { > + fsl,pins = < > + MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 > + MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 > + MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x1b0b1 > + MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x1b0b1 > + >; > + }; > + > + pinctrl_usdhc1: usdhc1grp { > + fsl,pins = < > + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 > + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 > + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 > + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 > + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 > + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 > + >; > + }; > + > + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { > + fsl,pins = < > + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 > + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 > + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 > + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 > + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 > + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 > + >; > + }; > + > + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { > + fsl,pins = < > + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 > + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 > + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 > + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 > + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 > + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 > + >; > + }; > + > + pinctrl_usdhc2: usdhc2grp { > + fsl,pins = < > + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059 > + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 > + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 > + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 > + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 > + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 > + >; > + }; > + > + pinctrl_tsc: tscgrp { Please keep these pinctrl group nodes sort alphabetically. > + fsl,pin = < > + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 > + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 > + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 > + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 > + >; > + }; > + > + pinctrl_i2c1: i2c1grp { > + fsl,pins = < > + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 > + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 > + >; > + }; > + > + pinctrl_i2c2: i2c2grp { > + fsl,pins = < > + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 > + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 > + >; > + }; > + > + pinctrl_qspi: qspigrp { > + fsl,pins = < > + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 > + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 > + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 > + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 > + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 > + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 > + >; > + }; > + > + pinctrl_sai2: sai2grp { > + fsl,pins = < > + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 > + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 > + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 > + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 > + MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 > + MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059 > + >; > + }; > + > + pinctrl_spi4: spi4grp { > + fsl,pins = < > + MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1 > + MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1 > + MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1 > + MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000 Use an explicit pad configuration value. > + >; > + }; > + }; > +}; > diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi > new file mode 100644 > index 0000000..e23a8c7 > --- /dev/null > +++ b/arch/arm/boot/dts/imx6ul.dtsi > @@ -0,0 +1,645 @@ > +/* > + * Copyright 2015 Freescale Semiconductor, Inc. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + */ > + > +#include <dt-bindings/clock/imx6ul-clock.h> > +#include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include "imx6ul-pinfunc.h" > +#include "skeleton.dtsi" > + > +/ { > + aliases { > + gpio0 = &gpio1; > + gpio1 = &gpio2; > + gpio2 = &gpio3; > + gpio3 = &gpio4; > + gpio4 = &gpio5; > + i2c0 = &i2c1; > + i2c1 = &i2c2; > + i2c2 = &i2c3; > + i2c3 = &i2c4; > + mmc0 = &usdhc1; > + mmc1 = &usdhc2; > + serial0 = &uart1; > + serial1 = &uart2; > + serial2 = &uart3; > + serial3 = &uart4; > + serial4 = &uart5; > + serial5 = &uart6; > + serial6 = &uart7; > + serial7 = &uart8; > + spi0 = &ecspi1; > + spi1 = &ecspi2; > + spi2 = &ecspi3; > + spi3 = &ecspi4; > + usbphy0 = &usbphy1; > + usbphy1 = &usbphy2; > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu0: cpu@0 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <0>; > + clock-latency = <61036>; /* two CLK32 periods */ > + operating-points = < > + /* kHz uV */ > + 528000 1250000 > + 396000 1150000 > + 198000 1150000 > + >; > + fsl,soc-operating-points = < > + /* KHz uV */ > + 528000 1250000 > + 396000 1150000 > + 198000 1150000 > + >; > + clocks = <&clks IMX6UL_CLK_ARM>, > + <&clks IMX6UL_CLK_PLL2_BUS>, > + <&clks IMX6UL_CLK_PLL2_PFD2>, > + <&clks IMX6UL_CA7_SECONDARY_SEL>, > + <&clks IMX6UL_CLK_STEP>, > + <&clks IMX6UL_CLK_PLL1_SW>, > + <&clks IMX6UL_CLK_PLL1_SYS>, > + <&clks IMX6UL_PLL1_BYPASS>, > + <&clks IMX6UL_CLK_PLL1>, > + <&clks IMX6UL_PLL1_BYPASS_SRC>, > + <&clks IMX6UL_CLK_OSC>; > + clock-names = "arm", "pll2_bus", "pll2_pfd2_396m", "secondary_sel", "step", > + "pll1_sw", "pll1_sys", "pll1_bypass", "pll1", "pll1_bypass_src", "osc"; Wrap these two lines to make them a bit shorter. > + }; > + }; > + > + intc: interrupt-controller@00a01000 { > + compatible = "arm,cortex-a7-gic"; > + #interrupt-cells = <3>; > + interrupt-controller; > + reg = <0x00a01000 0x1000>, > + <0x00a02000 0x1000>, > + <0x00a04000 0x2000>, > + <0x00a06000 0x2000>; > + }; > + > + ckil: clock-cli { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <32768>; > + clock-output-names = "ckil"; > + }; > + > + osc: clock-osc { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <24000000>; > + clock-output-names = "osc"; > + }; > + > + ipp_di0: clock-di0 { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <0>; > + clock-output-names = "ipp_di0"; > + }; > + > + ipp_di1: clock-di1 { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <0>; > + clock-output-names = "ipp_di1"; > + }; > + > + soc { > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = "simple-bus"; > + interrupt-parent = <&intc>; > + ranges; > + > + pmu { > + compatible = "arm,cortex-a7-pmu"; > + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + }; > + > + aips1: aips-bus@02000000 { > + compatible = "fsl,aips-bus", "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + reg = <0x02000000 0x100000>; > + ranges; > + > + spba-bus@02000000 { > + compatible = "fsl,spba-bus", "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + reg = <0x02000000 0x40000>; > + ranges; > + > + ecspi1: ecspi@02008000 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; > + reg = <0x02008000 0x4000>; > + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX6UL_CLK_ECSPI1>, > + <&clks IMX6UL_CLK_ECSPI1>; > + clock-names = "ipg", "per"; > + status = "disabled"; > + }; > + > + ecspi2: ecspi@0200c000 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; > + reg = <0x0200c000 0x4000>; > + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX6UL_CLK_ECSPI2>, > + <&clks IMX6UL_CLK_ECSPI2>; > + clock-names = "ipg", "per"; > + status = "disabled"; > + }; > + > + ecspi3: ecspi@02010000 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; > + reg = <0x02010000 0x4000>; > + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX6UL_CLK_ECSPI3>, > + <&clks IMX6UL_CLK_ECSPI3>; > + clock-names = "ipg", "per"; > + status = "disabled"; > + }; > + > + ecspi4: ecspi@02014000 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; > + reg = <0x02014000 0x4000>; > + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX6UL_CLK_ECSPI4>, > + <&clks IMX6UL_CLK_ECSPI4>; > + clock-names = "ipg", "per"; > + status = "disabled"; > + }; > + > + uart7: serial@02018000 { > + compatible = "fsl,imx6ul-uart", > + "fsl,imx6q-uart", "fsl,imx21-uart"; "fsl,imx21-uart" can just be dropped? > + reg = <0x02018000 0x4000>; > + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX6UL_CLK_UART7_IPG>, > + <&clks IMX6UL_CLK_UART7_SERIAL>; > + clock-names = "ipg", "per"; > + status = "disabled"; > + }; > + > + uart1: serial@02020000 { > + compatible = "fsl,imx6ul-uart", > + "fsl,imx6q-uart", "fsl,imx21-uart"; > + reg = <0x02020000 0x4000>; > + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX6UL_CLK_UART1_IPG>, > + <&clks IMX6UL_CLK_UART1_SERIAL>; > + clock-names = "ipg", "per"; > + status = "disabled"; > + }; > + > + uart8: serial@02024000 { > + compatible = "fsl,imx6ul-uart", > + "fsl,imx6q-uart", "fsl,imx21-uart"; > + reg = <0x02024000 0x4000>; > + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX6UL_CLK_UART8_IPG>, > + <&clks IMX6UL_CLK_UART8_SERIAL>; > + clock-names = "ipg", "per"; > + status = "disabled"; > + }; > + }; > + > + One new line is enough. > + pwm1: pwm@02080000 { > + compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; > + reg = <0x02080000 0x4000>; > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX6UL_CLK_PWM1>, > + <&clks IMX6UL_CLK_PWM1>; > + clock-names = "ipg", "per"; > + #pwm-cells = <2>; > + }; > + > + pwm2: pwm@02084000 { > + compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; > + reg = <0x02084000 0x4000>; > + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX6UL_CLK_DUMMY>, > + <&clks IMX6UL_CLK_DUMMY>; Why all other pwm devices except pwm1 are using dummy clock? > + clock-names = "ipg", "per"; > + #pwm-cells = <2>; > + }; > + > + pwm3: pwm@02088000 { > + compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; > + reg = <0x02088000 0x4000>; > + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX6UL_CLK_DUMMY>, > + <&clks IMX6UL_CLK_DUMMY>; > + clock-names = "ipg", "per"; > + #pwm-cells = <2>; > + }; > + > + pwm4: pwm@0208c000 { > + compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; > + reg = <0x0208c000 0x4000>; > + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX6UL_CLK_DUMMY>, > + <&clks IMX6UL_CLK_DUMMY>; > + clock-names = "ipg", "per"; > + #pwm-cells = <2>; > + }; > + > + gpt1: gpt@02098000 { > + compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt"; > + reg = <0x02098000 0x4000>; > + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX6UL_CLK_GPT1_BUS>, > + <&clks IMX6UL_CLK_GPT1_SERIAL>; > + clock-names = "ipg", "per"; > + }; > + > + gpio1: gpio@0209c000 { > + compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; > + reg = <0x0209c000 0x4000>; > + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpio2: gpio@020a0000 { > + compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; > + reg = <0x020a0000 0x4000>; > + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpio3: gpio@020a4000 { > + compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; > + reg = <0x020a4000 0x4000>; > + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpio4: gpio@020a8000 { > + compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; > + reg = <0x020a8000 0x4000>; > + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpio5: gpio@020ac000 { > + compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; > + reg = <0x020ac000 0x4000>; > + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + wdog1: wdog@020bc000 { > + compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; > + reg = <0x020bc000 0x4000>; > + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX6UL_CLK_WDOG1>; > + }; > + > + wdog2: wdog@020c0000 { > + compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; > + reg = <0x020c0000 0x4000>; > + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX6UL_CLK_WDOG2>; > + status = "disabled"; > + }; > + > + clks: ccm@020c4000 { > + compatible = "fsl,imx6ul-ccm"; > + reg = <0x020c4000 0x4000>; > + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; > + #clock-cells = <1>; > + clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; > + clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; > + }; > + > + anatop: anatop@020c8000 { > + compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop", > + "syscon", "simple-bus"; > + reg = <0x020c8000 0x1000>; > + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; > + > + reg_3p0: regulator-3p0@120 { > + compatible = "fsl,anatop-regulator"; > + regulator-name = "vdd3p0"; > + regulator-min-microvolt = <2625000>; > + regulator-max-microvolt = <3400000>; > + anatop-reg-offset = <0x120>; > + anatop-vol-bit-shift = <8>; > + anatop-vol-bit-width = <5>; > + anatop-min-bit-val = <0>; > + anatop-min-voltage = <2625000>; > + anatop-max-voltage = <3400000>; > + anatop-enable-bit = <0>; > + }; > + > + reg_arm: regulator-vddcore@140 { > + compatible = "fsl,anatop-regulator"; > + regulator-name = "cpu"; > + regulator-min-microvolt = <725000>; > + regulator-max-microvolt = <1450000>; > + regulator-always-on; > + anatop-reg-offset = <0x140>; > + anatop-vol-bit-shift = <0>; > + anatop-vol-bit-width = <5>; > + anatop-delay-reg-offset = <0x170>; > + anatop-delay-bit-shift = <24>; > + anatop-delay-bit-width = <2>; > + anatop-min-bit-val = <1>; > + anatop-min-voltage = <725000>; > + anatop-max-voltage = <1450000>; > + }; > + > + reg_soc: regulator-vddsoc@140 { > + compatible = "fsl,anatop-regulator"; > + regulator-name = "vddsoc"; > + regulator-min-microvolt = <725000>; > + regulator-max-microvolt = <1450000>; > + regulator-always-on; > + anatop-reg-offset = <0x140>; > + anatop-vol-bit-shift = <18>; > + anatop-vol-bit-width = <5>; > + anatop-delay-reg-offset = <0x170>; > + anatop-delay-bit-shift = <28>; > + anatop-delay-bit-width = <2>; > + anatop-min-bit-val = <1>; > + anatop-min-voltage = <725000>; > + anatop-max-voltage = <1450000>; > + }; > + }; > + > + usbphy1: usbphy@020c9000 { > + compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; > + reg = <0x020c9000 0x1000>; > + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX6UL_CLK_USBPHY1>; > + phy-3p0-supply = <®_3p0>; > + fsl,anatop = <&anatop>; > + }; > + > + usbphy2: usbphy@020ca000 { > + compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; > + reg = <0x020ca000 0x1000>; > + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX6UL_CLK_USBPHY2>; > + phy-3p0-supply = <®_3p0>; > + fsl,anatop = <&anatop>; > + }; > + > + epit1: epit@020d0000 { > + reg = <0x020d0000 0x4000>; > + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + epit2: epit@020d4000 { > + reg = <0x020d4000 0x4000>; > + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > + src: src@020d8000 { > + compatible = "fsl,imx6ul-src", "fsl,imx51-src"; > + reg = <0x020d8000 0x4000>; > + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; > + #reset-cells = <1>; > + }; > + > + gpc: gpc@020dc000 { > + compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc"; > + reg = <0x020dc000 0x4000>; > + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; > + fsl,mf-mix-wakeup-irq = <0x7c00000 0x3d00 0x0 0x1400240>; I cannot find this property in any bindings doc. Shawn > + }; > + > + iomuxc: iomuxc@020e0000 { > + compatible = "fsl,imx6ul-iomuxc"; > + reg = <0x020e0000 0x4000>; > + }; > + > + gpr: iomuxc-gpr@020e4000 { > + compatible = "fsl,imx6ul-iomuxc-gpr", "syscon"; > + reg = <0x020e4000 0x4000>; > + }; > + > + gpt2: gpt@020e8000 { > + compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt"; > + reg = <0x020e8000 0x4000>; > + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX6UL_CLK_DUMMY>, > + <&clks IMX6UL_CLK_DUMMY>; > + clock-names = "ipg", "per"; > + }; > + > + pwm5: pwm@020f0000 { > + compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; > + reg = <0x020f0000 0x4000>; > + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX6UL_CLK_DUMMY>, > + <&clks IMX6UL_CLK_DUMMY>; > + clock-names = "ipg", "per"; > + #pwm-cells = <2>; > + }; > + > + pwm6: pwm@020f4000 { > + compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; > + reg = <0x020f4000 0x4000>; > + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX6UL_CLK_DUMMY>, > + <&clks IMX6UL_CLK_DUMMY>; > + clock-names = "ipg", "per"; > + #pwm-cells = <2>; > + }; > + > + pwm7: pwm@020f8000 { > + compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; > + reg = <0x020f8000 0x4000>; > + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX6UL_CLK_DUMMY>, > + <&clks IMX6UL_CLK_DUMMY>; > + clock-names = "ipg", "per"; > + #pwm-cells = <2>; > + }; > + > + pwm8: pwm@020fc000 { > + compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; > + reg = <0x020fc000 0x4000>; > + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX6UL_CLK_DUMMY>, > + <&clks IMX6UL_CLK_DUMMY>; > + clock-names = "ipg", "per"; > + #pwm-cells = <2>; > + }; > + }; > + > + aips2: aips-bus@02100000 { > + compatible = "fsl,aips-bus", "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + reg = <0x02100000 0x100000>; > + ranges; > + > + usdhc1: usdhc@02190000 { > + compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; > + reg = <0x02190000 0x4000>; > + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX6UL_CLK_USDHC1>, > + <&clks IMX6UL_CLK_USDHC1>, > + <&clks IMX6UL_CLK_USDHC1>; > + clock-names = "ipg", "ahb", "per"; > + bus-width = <4>; > + status = "disabled"; > + }; > + > + usdhc2: usdhc@02194000 { > + compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; > + reg = <0x02194000 0x4000>; > + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX6UL_CLK_USDHC2>, > + <&clks IMX6UL_CLK_USDHC2>, > + <&clks IMX6UL_CLK_USDHC2>; > + clock-names = "ipg", "ahb", "per"; > + bus-width = <4>; > + status = "disabled"; > + }; > + > + i2c1: i2c@021a0000 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; > + reg = <0x021a0000 0x4000>; > + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX6UL_CLK_I2C1>; > + status = "disabled"; > + }; > + > + i2c2: i2c@021a4000 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; > + reg = <0x021a4000 0x4000>; > + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX6UL_CLK_I2C2>; > + status = "disabled"; > + }; > + > + i2c3: i2c@021a8000 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; > + reg = <0x021a8000 0x4000>; > + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX6UL_CLK_I2C3>; > + status = "disabled"; > + }; > + > + uart2: serial@021e8000 { > + compatible = "fsl,imx6ul-uart", > + "fsl,imx6q-uart", "fsl,imx21-uart"; > + reg = <0x021e8000 0x4000>; > + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX6UL_CLK_UART2_IPG>, > + <&clks IMX6UL_CLK_UART2_SERIAL>; > + clock-names = "ipg", "per"; > + status = "disabled"; > + }; > + > + uart3: serial@021ec000 { > + compatible = "fsl,imx6ul-uart", > + "fsl,imx6q-uart", "fsl,imx21-uart"; > + reg = <0x021ec000 0x4000>; > + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX6UL_CLK_UART3_IPG>, > + <&clks IMX6UL_CLK_UART3_SERIAL>; > + clock-names = "ipg", "per"; > + status = "disabled"; > + }; > + > + uart4: serial@021f0000 { > + compatible = "fsl,imx6ul-uart", > + "fsl,imx6q-uart", "fsl,imx21-uart"; > + reg = <0x021f0000 0x4000>; > + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX6UL_CLK_UART4_IPG>, > + <&clks IMX6UL_CLK_UART4_SERIAL>; > + clock-names = "ipg", "per"; > + status = "disabled"; > + }; > + > + uart5: serial@021f4000 { > + compatible = "fsl,imx6ul-uart", > + "fsl,imx6q-uart", "fsl,imx21-uart"; > + reg = <0x021f4000 0x4000>; > + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX6UL_CLK_UART5_IPG>, > + <&clks IMX6UL_CLK_UART5_SERIAL>; > + clock-names = "ipg", "per"; > + status = "disabled"; > + }; > + > + i2c4: i2c@021f8000 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; > + reg = <0x021f8000 0x4000>; > + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX6UL_CLK_I2C4>; > + status = "disabled"; > + }; > + > + uart6: serial@021fc000 { > + compatible = "fsl,imx6ul-uart", > + "fsl,imx6q-uart", "fsl,imx21-uart"; > + reg = <0x021fc000 0x4000>; > + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clks IMX6UL_CLK_UART6_IPG>, > + <&clks IMX6UL_CLK_UART6_SERIAL>; > + clock-names = "ipg", "per"; > + status = "disabled"; > + }; > + }; > + }; > +}; > -- > 1.9.1 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel > ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 7/8] ARM: imx: imx_v6_v7_defconfig enable imx6ul support [not found] ` <1434555569-8237-1-git-send-email-Frank.Li-KZfg59tc24xl57MIdRCFDg@public.gmane.org> ` (2 preceding siblings ...) 2015-06-17 15:39 ` [PATCH 6/8] ARM: dts: imx: add imx6ul and imx6ul evk board support Frank.Li-KZfg59tc24xl57MIdRCFDg @ 2015-06-17 15:39 ` Frank.Li-KZfg59tc24xl57MIdRCFDg 2015-06-17 15:39 ` [PATCH 8/8] ARM: imx: add low-level debug support for i.mx6ul Frank.Li-KZfg59tc24xl57MIdRCFDg 4 siblings, 0 replies; 16+ messages in thread From: Frank.Li-KZfg59tc24xl57MIdRCFDg @ 2015-06-17 15:39 UTC (permalink / raw) To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, shawn.guo-QSEj5FYQhm4dnm+yROfE0A, shawnguo-DgEjT+Ai2ygdnm+yROfE0A, linus.walleij-QSEj5FYQhm4dnm+yROfE0A, lznuaa-Re5JQEeQqe8AvxtiuMwx3w Cc: linux-gpio-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A, devicetree-u79uwXL29TY76Z2rM5mHXA, Frank Li From: Frank Li <Frank.Li-KZfg59tc24xl57MIdRCFDg@public.gmane.org> default enable imx6ul support Signed-off-by: Frank Li <Frank.Li-KZfg59tc24xl57MIdRCFDg@public.gmane.org> --- arch/arm/configs/imx_v6_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index b47863d..b0fe9d9 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -38,6 +38,7 @@ CONFIG_SOC_IMX53=y CONFIG_SOC_IMX6Q=y CONFIG_SOC_IMX6SL=y CONFIG_SOC_IMX6SX=y +CONFIG_SOC_IMX6UL=y CONFIG_SOC_IMX7D=y CONFIG_SOC_VF610=y CONFIG_SOC_LS1021A=y -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 8/8] ARM: imx: add low-level debug support for i.mx6ul [not found] ` <1434555569-8237-1-git-send-email-Frank.Li-KZfg59tc24xl57MIdRCFDg@public.gmane.org> ` (3 preceding siblings ...) 2015-06-17 15:39 ` [PATCH 7/8] ARM: imx: imx_v6_v7_defconfig enable imx6ul support Frank.Li-KZfg59tc24xl57MIdRCFDg @ 2015-06-17 15:39 ` Frank.Li-KZfg59tc24xl57MIdRCFDg 4 siblings, 0 replies; 16+ messages in thread From: Frank.Li-KZfg59tc24xl57MIdRCFDg @ 2015-06-17 15:39 UTC (permalink / raw) To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, shawn.guo-QSEj5FYQhm4dnm+yROfE0A, shawnguo-DgEjT+Ai2ygdnm+yROfE0A, linus.walleij-QSEj5FYQhm4dnm+yROfE0A, lznuaa-Re5JQEeQqe8AvxtiuMwx3w Cc: linux-gpio-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A, devicetree-u79uwXL29TY76Z2rM5mHXA, Anson Huang, Fugang Duan, Frank Li From: Anson Huang <b20788-KZfg59tc24xl57MIdRCFDg@public.gmane.org> Enable low-level debug support for i.MX6UL by adding the debug port definitions for the SoC. Singed-off-by: Anson Huang <b20788-KZfg59tc24xl57MIdRCFDg@public.gmane.org> Signed-off-by: Fugang Duan <B38611-KZfg59tc24xl57MIdRCFDg@public.gmane.org> Signed-off-by: Frank Li <Frank.Li-KZfg59tc24xl57MIdRCFDg@public.gmane.org> --- arch/arm/Kconfig.debug | 9 +++++++++ arch/arm/include/debug/imx-uart.h | 13 +++++++++++++ 2 files changed, 22 insertions(+) diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index f1b1579..f21daa8 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -411,6 +411,13 @@ choice Say Y here if you want kernel low-level debugging support on i.MX6SX. + config DEBUG_IMX6UL_UART + bool "i.MX6UL Debug UART" + depends on SOC_IMX6UL + help + Say Y here if you want kernel low-level debugging support + on i.MX6UL. + config DEBUG_IMX7D_UART bool "i.MX7D Debug UART" depends on SOC_IMX7D @@ -1269,6 +1276,7 @@ config DEBUG_IMX_UART_PORT DEBUG_IMX6Q_UART || \ DEBUG_IMX6SL_UART || \ DEBUG_IMX6SX_UART || \ + DEBUG_IMX6UL_UART || \ DEBUG_IMX7D_UART default 1 depends on ARCH_MXC @@ -1320,6 +1328,7 @@ config DEBUG_LL_INCLUDE DEBUG_IMX6Q_UART || \ DEBUG_IMX6SL_UART || \ DEBUG_IMX6SX_UART || \ + DEBUG_IMX6UL_UART || \ DEBUG_IMX7D_UART default "debug/ks8695.S" if DEBUG_KS8695_UART default "debug/msm.S" if DEBUG_QCOM_UARTDM diff --git a/arch/arm/include/debug/imx-uart.h b/arch/arm/include/debug/imx-uart.h index 66f736f..bce58e9 100644 --- a/arch/arm/include/debug/imx-uart.h +++ b/arch/arm/include/debug/imx-uart.h @@ -90,6 +90,17 @@ #define IMX6SX_UART_BASE_ADDR(n) IMX6SX_UART##n##_BASE_ADDR #define IMX6SX_UART_BASE(n) IMX6SX_UART_BASE_ADDR(n) +#define IMX6UL_UART1_BASE_ADDR 0x02020000 +#define IMX6UL_UART2_BASE_ADDR 0x021e8000 +#define IMX6UL_UART3_BASE_ADDR 0x021ec000 +#define IMX6UL_UART4_BASE_ADDR 0x021f0000 +#define IMX6UL_UART5_BASE_ADDR 0x021f4000 +#define IMX6UL_UART6_BASE_ADDR 0x021fc000 +#define IMX6UL_UART7_BASE_ADDR 0x02018000 +#define IMX6UL_UART8_BASE_ADDR 0x02024000 +#define IMX6UL_UART_BASE_ADDR(n) IMX6UL_UART##n##_BASE_ADDR +#define IMX6UL_UART_BASE(n) IMX6UL_UART_BASE_ADDR(n) + #define IMX7D_UART1_BASE_ADDR 0x30860000 #define IMX7D_UART2_BASE_ADDR 0x30890000 #define IMX7D_UART3_BASE_ADDR 0x30880000 @@ -124,6 +135,8 @@ #define UART_PADDR IMX_DEBUG_UART_BASE(IMX6SL) #elif defined(CONFIG_DEBUG_IMX6SX_UART) #define UART_PADDR IMX_DEBUG_UART_BASE(IMX6SX) +#elif defined(CONFIG_DEBUG_IMX6UL_UART) +#define UART_PADDR IMX_DEBUG_UART_BASE(IMX6UL) #elif defined(CONFIG_DEBUG_IMX7D_UART) #define UART_PADDR IMX_DEBUG_UART_BASE(IMX7D) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 16+ messages in thread
end of thread, other threads:[~2015-07-09 7:02 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz follow: Atom feed
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2015-06-17 15:39 [PATCH 0/8] add basic support for i.mx6 ul chip Frank.Li-KZfg59tc24xl57MIdRCFDg
2015-06-17 15:39 ` [PATCH 1/8] ARM: imx: add i.mx6ul msl support Frank.Li
2015-07-09 2:17 ` Shawn Guo
2015-06-17 15:39 ` [PATCH 3/8] Document: dt: binding: imx: update document for imx6ul support Frank.Li
2015-07-09 2:36 ` Shawn Guo
2015-06-17 15:39 ` [PATCH 4/8] ARM: pinctrl: imx: add i.mx6ul pinctrl driver Frank.Li
2015-07-09 2:38 ` Shawn Guo
[not found] ` <1434555569-8237-1-git-send-email-Frank.Li-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
2015-06-17 15:39 ` [PATCH 2/8] ARM: imx: add imx6ul clk tree support Frank.Li-KZfg59tc24xl57MIdRCFDg
2015-06-18 5:40 ` Sascha Hauer
2015-06-17 15:39 ` [PATCH 5/8] ARM: dts: add i.mx6ul pin function include file Frank.Li-KZfg59tc24xl57MIdRCFDg
2015-07-09 3:09 ` Shawn Guo
2015-06-17 15:39 ` [PATCH 6/8] ARM: dts: imx: add imx6ul and imx6ul evk board support Frank.Li-KZfg59tc24xl57MIdRCFDg
2015-06-18 5:50 ` Sascha Hauer
2015-07-09 7:02 ` Shawn Guo
2015-06-17 15:39 ` [PATCH 7/8] ARM: imx: imx_v6_v7_defconfig enable imx6ul support Frank.Li-KZfg59tc24xl57MIdRCFDg
2015-06-17 15:39 ` [PATCH 8/8] ARM: imx: add low-level debug support for i.mx6ul Frank.Li-KZfg59tc24xl57MIdRCFDg
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