* [PATCH 1/4] ARM: imx: imx7d-pinfunc: add gpio pad iomuxc settings
@ 2015-06-19 19:59 Adrian Alonso
2015-06-19 19:59 ` [PATCH 2/4] ARM: dts: imx: imx7d add iomuxc lpsr register base address Adrian Alonso
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Adrian Alonso @ 2015-06-19 19:59 UTC (permalink / raw)
To: linux-arm-kernel, shawn.guo, shawnguo, linus.walleij, lznuaa
Cc: devicetree, Frank.Li, nitin.garg, Anson.Huang, linux-gpio,
robh+dt, yibin.gong
* Add iMX7D SoC imx7d-pinfunc gpio pad settings
<mux_reg conf_reg input_reg mux_mode input_val>
* iMX7D GPIO1_IO7 to GPIO1_IO0 encode the pad group id in the most
significant bits of input_val to avoid group id overlap bweeten
iomuxc and iomuxc-lpsr.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
---
arch/arm/boot/dts/imx7d-pinfunc.h | 116 ++++++++++++++++++++++++++++++++++++++
1 file changed, 116 insertions(+)
diff --git a/arch/arm/boot/dts/imx7d-pinfunc.h b/arch/arm/boot/dts/imx7d-pinfunc.h
index a8d8149..ae7cc1a 100644
--- a/arch/arm/boot/dts/imx7d-pinfunc.h
+++ b/arch/arm/boot/dts/imx7d-pinfunc.h
@@ -15,6 +15,122 @@
* <mux_reg conf_reg input_reg mux_mode input_val>
*/
+#define MX7D_PAD_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x9B000000
+#define MX7D_PAD_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x9B000000
+#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x9B000000
+#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x9B000000
+#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x9B000000
+#define MX7D_PAD_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x9C000000
+#define MX7D_PAD_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x9C000000
+#define MX7D_PAD_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x9C000000
+#define MX7D_PAD_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x9C000000
+#define MX7D_PAD_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x9C000000
+#define MX7D_PAD_GPIO1_IO01__OBSERVE0_OUT 0x0004 0x0034 0x0000 0x6 0x9C000000
+#define MX7D_PAD_GPIO1_IO02__GPIO1_IO2 0x0008 0x0038 0x0000 0x0 0x9D000000
+#define MX7D_PAD_GPIO1_IO02__PWM2_OUT 0x0008 0x0038 0x0000 0x1 0x9D000000
+#define MX7D_PAD_GPIO1_IO02__CCM_ENET_REF_CLK1 0x0008 0x0038 0x0564 0x2 0x9D000003
+#define MX7D_PAD_GPIO1_IO02__SAI2_MCLK 0x0008 0x0038 0x0000 0x3 0x9D000000
+#define MX7D_PAD_GPIO1_IO02__CCM_CLKO1 0x0008 0x0038 0x0000 0x5 0x9D000000
+#define MX7D_PAD_GPIO1_IO02__OBSERVE1_OUT 0x0008 0x0038 0x0000 0x6 0x9D000000
+#define MX7D_PAD_GPIO1_IO02__USB_OTG1_ID 0x0008 0x0038 0x0734 0x7 0x9D000003
+#define MX7D_PAD_GPIO1_IO03__GPIO1_IO3 0x000C 0x003C 0x0000 0x0 0x9E000000
+#define MX7D_PAD_GPIO1_IO03__PWM3_OUT 0x000C 0x003C 0x0000 0x1 0x9E000000
+#define MX7D_PAD_GPIO1_IO03__CCM_ENET_REF_CLK2 0x000C 0x003C 0x0570 0x2 0x9E000003
+#define MX7D_PAD_GPIO1_IO03__SAI3_MCLK 0x000C 0x003C 0x0000 0x3 0x9E000000
+#define MX7D_PAD_GPIO1_IO03__CCM_CLKO2 0x000C 0x003C 0x0000 0x5 0x9E000000
+#define MX7D_PAD_GPIO1_IO03__OBSERVE2_OUT 0x000C 0x003C 0x0000 0x6 0x9E000000
+#define MX7D_PAD_GPIO1_IO03__USB_OTG2_ID 0x000C 0x003C 0x0730 0x7 0x9E000003
+#define MX7D_PAD_GPIO1_IO04__GPIO1_IO4 0x0010 0x0040 0x0000 0x0 0x9F000000
+#define MX7D_PAD_GPIO1_IO04__USB_OTG1_OC 0x0010 0x0040 0x072C 0x1 0x9F000001
+#define MX7D_PAD_GPIO1_IO04__FLEXTIMER1_CH4 0x0010 0x0040 0x0594 0x2 0x9F000001
+#define MX7D_PAD_GPIO1_IO04__UART5_CTS_B 0x0010 0x0040 0x0710 0x3 0x9F000004
+#define MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x0010 0x0040 0x05D4 0x4 0x9F000002
+#define MX7D_PAD_GPIO1_IO04__OBSERVE3_OUT 0x0010 0x0040 0x0000 0x6 0x9F000000
+#define MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x0014 0x0044 0x0000 0x0 0xA0000000
+#define MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR 0x0014 0x0044 0x0000 0x1 0xA0000000
+#define MX7D_PAD_GPIO1_IO05__FLEXTIMER1_CH5 0x0014 0x0044 0x0598 0x2 0xA0000001
+#define MX7D_PAD_GPIO1_IO05__UART5_RTS_B 0x0014 0x0044 0x0710 0x3 0xA0000005
+#define MX7D_PAD_GPIO1_IO05__I2C1_SDA 0x0014 0x0044 0x05D8 0x4 0xA0000002
+#define MX7D_PAD_GPIO1_IO05__OBSERVE4_OUT 0x0014 0x0044 0x0000 0x6 0xA0000000
+#define MX7D_PAD_GPIO1_IO06__GPIO1_IO6 0x0018 0x0048 0x0000 0x0 0xA1000000
+#define MX7D_PAD_GPIO1_IO06__USB_OTG2_OC 0x0018 0x0048 0x0728 0x1 0xA1000001
+#define MX7D_PAD_GPIO1_IO06__FLEXTIMER1_CH6 0x0018 0x0048 0x059C 0x2 0xA1000001
+#define MX7D_PAD_GPIO1_IO06__UART5_RX_DATA 0x0018 0x0048 0x0714 0x3 0xA1000004
+#define MX7D_PAD_GPIO1_IO06__I2C2_SCL 0x0018 0x0048 0x05DC 0x4 0xA1000002
+#define MX7D_PAD_GPIO1_IO06__CCM_WAIT 0x0018 0x0048 0x0000 0x5 0xA1000000
+#define MX7D_PAD_GPIO1_IO06__KPP_ROW4 0x0018 0x0048 0x0624 0x6 0xA1000001
+#define MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x001C 0x004C 0x0000 0x0 0xA2000000
+#define MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR 0x001C 0x004C 0x0000 0x1 0xA2000000
+#define MX7D_PAD_GPIO1_IO07__FLEXTIMER1_CH7 0x001C 0x004C 0x05A0 0x2 0xA2000001
+#define MX7D_PAD_GPIO1_IO07__UART5_TX_DATA 0x001C 0x004C 0x0714 0x3 0xA2000005
+#define MX7D_PAD_GPIO1_IO07__I2C2_SDA 0x001C 0x004C 0x05E0 0x4 0xA2000002
+#define MX7D_PAD_GPIO1_IO07__CCM_STOP 0x001C 0x004C 0x0000 0x5 0xA2000000
+#define MX7D_PAD_GPIO1_IO07__KPP_COL4 0x001C 0x004C 0x0604 0x6 0xA2000001
+#define MX7D_PAD_GPIO1_IO08__GPIO1_IO8 0x0014 0x026C 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x0014 0x026C 0x0000 0x1 0x0
+#define MX7D_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0014 0x026C 0x0000 0x2 0x0
+#define MX7D_PAD_GPIO1_IO08__UART3_DCE_RX 0x0014 0x026C 0x0704 0x3 0x0
+#define MX7D_PAD_GPIO1_IO08__UART3_DTE_TX 0x0014 0x026C 0x0000 0x3 0x0
+#define MX7D_PAD_GPIO1_IO08__I2C3_SCL 0x0014 0x026C 0x05E4 0x4 0x0
+#define MX7D_PAD_GPIO1_IO08__KPP_COL5 0x0014 0x026C 0x0608 0x6 0x0
+#define MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x0014 0x026C 0x0000 0x7 0x0
+#define MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x0018 0x0270 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO09__SD1_LCTL 0x0018 0x0270 0x0000 0x1 0x0
+#define MX7D_PAD_GPIO1_IO09__CCM_ENET_REF_CLK3 0x0018 0x0270 0x0000 0x2 0x0
+#define MX7D_PAD_GPIO1_IO09__UART3_DCE_TX 0x0018 0x0270 0x0000 0x3 0x0
+#define MX7D_PAD_GPIO1_IO09__UART3_DTE_RX 0x0018 0x0270 0x0704 0x3 0x1
+#define MX7D_PAD_GPIO1_IO09__I2C3_SDA 0x0018 0x0270 0x05E8 0x4 0x0
+#define MX7D_PAD_GPIO1_IO09__CCM_PMIC_READY 0x0018 0x0270 0x04F4 0x5 0x0
+#define MX7D_PAD_GPIO1_IO09__KPP_ROW5 0x0018 0x0270 0x0628 0x6 0x0
+#define MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x0018 0x0270 0x0000 0x7 0x0
+#define MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x001C 0x0274 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO10__SD2_LCTL 0x001C 0x0274 0x0000 0x1 0x0
+#define MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x001C 0x0274 0x0568 0x2 0x0
+#define MX7D_PAD_GPIO1_IO10__UART3_DCE_RTS 0x001C 0x0274 0x0700 0x3 0x0
+#define MX7D_PAD_GPIO1_IO10__UART3_DTE_CTS 0x001C 0x0274 0x0000 0x3 0x0
+#define MX7D_PAD_GPIO1_IO10__I2C4_SCL 0x001C 0x0274 0x05EC 0x4 0x0
+#define MX7D_PAD_GPIO1_IO10__FLEXTIMER1_PHA 0x001C 0x0274 0x05A4 0x5 0x0
+#define MX7D_PAD_GPIO1_IO10__KPP_COL6 0x001C 0x0274 0x060C 0x6 0x0
+#define MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x001C 0x0274 0x0000 0x7 0x0
+#define MX7D_PAD_GPIO1_IO11__GPIO1_IO11 0x0020 0x0278 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO11__SD3_LCTL 0x0020 0x0278 0x0000 0x1 0x0
+#define MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x0020 0x0278 0x0000 0x2 0x0
+#define MX7D_PAD_GPIO1_IO11__UART3_DCE_CTS 0x0020 0x0278 0x0000 0x3 0x0
+#define MX7D_PAD_GPIO1_IO11__UART3_DTE_RTS 0x0020 0x0278 0x0700 0x3 0x1
+#define MX7D_PAD_GPIO1_IO11__I2C4_SDA 0x0020 0x0278 0x05F0 0x4 0x0
+#define MX7D_PAD_GPIO1_IO11__FLEXTIMER1_PHB 0x0020 0x0278 0x05A8 0x5 0x0
+#define MX7D_PAD_GPIO1_IO11__KPP_ROW6 0x0020 0x0278 0x062C 0x6 0x0
+#define MX7D_PAD_GPIO1_IO11__PWM4_OUT 0x0020 0x0278 0x0000 0x7 0x0
+#define MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x0024 0x027C 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO12__SD2_VSELECT 0x0024 0x027C 0x0000 0x1 0x0
+#define MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x0024 0x027C 0x0564 0x2 0x0
+#define MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x0024 0x027C 0x04DC 0x3 0x0
+#define MX7D_PAD_GPIO1_IO12__CM4_NMI 0x0024 0x027C 0x0000 0x4 0x0
+#define MX7D_PAD_GPIO1_IO12__CCM_EXT_CLK1 0x0024 0x027C 0x04E4 0x5 0x0
+#define MX7D_PAD_GPIO1_IO12__SNVS_VIO_5 0x0024 0x027C 0x0000 0x6 0x0
+#define MX7D_PAD_GPIO1_IO12__USB_OTG1_ID 0x0024 0x027C 0x0734 0x7 0x0
+#define MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x0028 0x0280 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO13__SD3_VSELECT 0x0028 0x0280 0x0000 0x1 0x0
+#define MX7D_PAD_GPIO1_IO13__CCM_ENET_REF_CLK2 0x0028 0x0280 0x0570 0x2 0x0
+#define MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x0028 0x0280 0x0000 0x3 0x0
+#define MX7D_PAD_GPIO1_IO13__CCM_PMIC_READY 0x0028 0x0280 0x04F4 0x4 0x1
+#define MX7D_PAD_GPIO1_IO13__CCM_EXT_CLK2 0x0028 0x0280 0x04E8 0x5 0x0
+#define MX7D_PAD_GPIO1_IO13__SNVS_VIO_5_CTL 0x0028 0x0280 0x0000 0x6 0x0
+#define MX7D_PAD_GPIO1_IO13__USB_OTG2_ID 0x0028 0x0280 0x0730 0x7 0x0
+#define MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x002C 0x0284 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO14__SD3_CD_B 0x002C 0x0284 0x0738 0x1 0x0
+#define MX7D_PAD_GPIO1_IO14__ENET2_MDIO 0x002C 0x0284 0x0574 0x2 0x0
+#define MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x002C 0x0284 0x04E0 0x3 0x0
+#define MX7D_PAD_GPIO1_IO14__WDOG3_WDOG_B 0x002C 0x0284 0x0000 0x4 0x0
+#define MX7D_PAD_GPIO1_IO14__CCM_EXT_CLK3 0x002C 0x0284 0x04EC 0x5 0x0
+#define MX7D_PAD_GPIO1_IO14__SDMA_EXT_EVENT0 0x002C 0x0284 0x06D8 0x6 0x0
+#define MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x0030 0x0288 0x0000 0x0 0x0
+#define MX7D_PAD_GPIO1_IO15__SD3_WP 0x0030 0x0288 0x073C 0x1 0x0
+#define MX7D_PAD_GPIO1_IO15__ENET2_MDC 0x0030 0x0288 0x0000 0x2 0x0
+#define MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x0030 0x0288 0x0000 0x3 0x0
+#define MX7D_PAD_GPIO1_IO15__WDOG4_WDOG_B 0x0030 0x0288 0x0000 0x4 0x0
+#define MX7D_PAD_GPIO1_IO15__CCM_EXT_CLK4 0x0030 0x0288 0x04F0 0x5 0x0
+#define MX7D_PAD_GPIO1_IO15__SDMA_EXT_EVENT1 0x0030 0x0288 0x06DC 0x6 0x0
#define MX7D_PAD_EPDC_DATA00__EPDC_DATA0 0x0034 0x02A4 0x0000 0x0 0x0
#define MX7D_PAD_EPDC_DATA00__SIM1_PORT2_TRXD 0x0034 0x02A4 0x0000 0x1 0x0
#define MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x0034 0x02A4 0x0000 0x2 0x0
--
2.1.4
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 2/4] ARM: dts: imx: imx7d add iomuxc lpsr register base address 2015-06-19 19:59 [PATCH 1/4] ARM: imx: imx7d-pinfunc: add gpio pad iomuxc settings Adrian Alonso @ 2015-06-19 19:59 ` Adrian Alonso 2015-06-19 19:59 ` [PATCH 3/4] ARM: imx: pinctrl-imx: imx7d: add support for iomuxc lpsr Adrian Alonso 2015-06-19 19:59 ` [PATCH 4/4] ARM: imx: pinctrl-imx7d: add iomuxc-lpsr gpio group ids Adrian Alonso 2 siblings, 0 replies; 6+ messages in thread From: Adrian Alonso @ 2015-06-19 19:59 UTC (permalink / raw) To: linux-arm-kernel, shawn.guo, shawnguo, linus.walleij, lznuaa Cc: linux-gpio, devicetree, robh+dt, Anson.Huang, Frank.Li, yibin.gong, nitin.garg * Add iomuxc lpsr register base address to extend pinctrl-imx driver to support the iomux settings for pins that support LPSR operation mode. Signed-off-by: Adrian Alonso <aalonso@freescale.com> --- arch/arm/boot/dts/imx7d.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi index c42cf8d..294a6c6 100644 --- a/arch/arm/boot/dts/imx7d.dtsi +++ b/arch/arm/boot/dts/imx7d.dtsi @@ -253,7 +253,7 @@ iomuxc: iomuxc@30330000 { compatible = "fsl,imx7d-iomuxc"; - reg = <0x30330000 0x10000>; + reg = <0x30330000 0x10000>, <0x302c0000 0x10000>; }; gpr: iomuxc-gpr@30340000 { -- 2.1.4 -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 3/4] ARM: imx: pinctrl-imx: imx7d: add support for iomuxc lpsr 2015-06-19 19:59 [PATCH 1/4] ARM: imx: imx7d-pinfunc: add gpio pad iomuxc settings Adrian Alonso 2015-06-19 19:59 ` [PATCH 2/4] ARM: dts: imx: imx7d add iomuxc lpsr register base address Adrian Alonso @ 2015-06-19 19:59 ` Adrian Alonso 2015-06-19 20:26 ` Zhi Li 2015-07-14 7:57 ` Linus Walleij 2015-06-19 19:59 ` [PATCH 4/4] ARM: imx: pinctrl-imx7d: add iomuxc-lpsr gpio group ids Adrian Alonso 2 siblings, 2 replies; 6+ messages in thread From: Adrian Alonso @ 2015-06-19 19:59 UTC (permalink / raw) To: linux-arm-kernel, shawn.guo, shawnguo, linus.walleij, lznuaa Cc: linux-gpio, devicetree, robh+dt, Anson.Huang, Frank.Li, yibin.gong, nitin.garg * Extend pinctrl-imx driver to support iomux lpsr conntroller, * iMX7D has two iomuxc controllers, iomuxc controller similar as previous iMX SoC generation and iomuxc-lpsr which provides low power state rentetion capabilities on gpios that are part of iomuxc-lpsr (GPIO1_IO7..GPIO1_IO0). * Use IOMUXC_LPSR_SUPPORT and iput_val most significant bits to properly configure iomuxc/iomuxc-lpsr settings. Signed-off-by: Adrian Alonso <aalonso@freescale.com> --- drivers/pinctrl/freescale/pinctrl-imx.c | 75 +++++++++++++++++++++++---------- drivers/pinctrl/freescale/pinctrl-imx.h | 6 ++- 2 files changed, 57 insertions(+), 24 deletions(-) diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c index d7b98ba..2d434ac 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx.c @@ -1,7 +1,7 @@ /* * Core driver for the imx pin controller * - * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Copyright (C) 2012-2015 Freescale Semiconductor, Inc. * Copyright (C) 2012 Linaro Ltd. * * Author: Dong Aisheng <dong.aisheng@linaro.org> @@ -18,6 +18,7 @@ #include <linux/module.h> #include <linux/of.h> #include <linux/of_device.h> +#include <linux/of_address.h> #include <linux/pinctrl/machine.h> #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h> @@ -38,7 +39,6 @@ struct imx_pinctrl { struct device *dev; struct pinctrl_dev *pctl; - void __iomem *base; const struct imx_pinctrl_soc_info *info; }; @@ -212,12 +212,12 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, if (info->flags & SHARE_MUX_CONF_REG) { u32 reg; - reg = readl(ipctl->base + pin_reg->mux_reg); + reg = readl(pin_reg->base + pin_reg->mux_reg); reg &= ~(0x7 << 20); reg |= (pin->mux_mode << 20); - writel(reg, ipctl->base + pin_reg->mux_reg); + writel(reg, pin_reg->base + pin_reg->mux_reg); } else { - writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg); + writel(pin->mux_mode, pin_reg->base + pin_reg->mux_reg); } dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", pin_reg->mux_reg, pin->mux_mode); @@ -245,16 +245,22 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, * The input_reg[i] here is actually some IOMUXC general * purpose register, not regular select input register. */ - val = readl(ipctl->base + pin->input_reg); + val = readl(pin_reg->base + pin->input_reg); val &= ~mask; val |= select << shift; - writel(val, ipctl->base + pin->input_reg); + writel(val, pin_reg->base + pin->input_reg); } else if (pin->input_reg) { /* * Regular select input register can never be at offset * 0, and we only print register value for regular case. */ - writel(pin->input_val, ipctl->base + pin->input_reg); + if (info->flags & IOMUXC_LPSR_SUPPORT && + pin->input_val >> 24) { + writel(pin->input_val, info->base + pin->input_reg); + } else { + writel(pin->input_val, pin_reg->base + pin->input_reg); + } + dev_dbg(ipctl->dev, "==>select_input: offset 0x%x val 0x%x\n", pin->input_reg, pin->input_val); @@ -326,10 +332,10 @@ static int imx_pmx_gpio_request_enable(struct pinctrl_dev *pctldev, return -EINVAL; mux_pin: - reg = readl(ipctl->base + pin_reg->mux_reg); + reg = readl(pin_reg->base + pin_reg->mux_reg); reg &= ~(0x7 << 20); reg |= imx_pin->config; - writel(reg, ipctl->base + pin_reg->mux_reg); + writel(reg, pin_reg->base + pin_reg->mux_reg); return 0; } @@ -354,12 +360,12 @@ static int imx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, return -EINVAL; /* IBE always enabled allows us to read the value "on the wire" */ - reg = readl(ipctl->base + pin_reg->mux_reg); + reg = readl(pin_reg->base + pin_reg->mux_reg); if (input) reg &= ~0x2; else reg |= 0x2; - writel(reg, ipctl->base + pin_reg->mux_reg); + writel(reg, pin_reg->base + pin_reg->mux_reg); return 0; } @@ -386,7 +392,7 @@ static int imx_pinconf_get(struct pinctrl_dev *pctldev, return -EINVAL; } - *config = readl(ipctl->base + pin_reg->conf_reg); + *config = readl(pin_reg->base + pin_reg->conf_reg); if (info->flags & SHARE_MUX_CONF_REG) *config &= 0xffff; @@ -415,12 +421,12 @@ static int imx_pinconf_set(struct pinctrl_dev *pctldev, for (i = 0; i < num_configs; i++) { if (info->flags & SHARE_MUX_CONF_REG) { u32 reg; - reg = readl(ipctl->base + pin_reg->conf_reg); + reg = readl(pin_reg->base + pin_reg->conf_reg); reg &= ~0xffff; reg |= configs[i]; - writel(reg, ipctl->base + pin_reg->conf_reg); + writel(reg, pin_reg->base + pin_reg->conf_reg); } else { - writel(configs[i], ipctl->base + pin_reg->conf_reg); + writel(configs[i], pin_reg->base + pin_reg->conf_reg); } dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n", pin_reg->conf_reg, configs[i]); @@ -442,7 +448,7 @@ static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev, return; } - config = readl(ipctl->base + pin_reg->conf_reg); + config = readl(pin_reg->base + pin_reg->conf_reg); seq_printf(s, "0x%lx", config); } @@ -551,14 +557,27 @@ static int imx_pinctrl_parse_groups(struct device_node *np, } pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4; + + pin->input_reg = be32_to_cpu(*list++); + pin->mux_mode = be32_to_cpu(*list++); + pin->input_val = be32_to_cpu(*list++); + + if (info->flags & IOMUXC_LPSR_SUPPORT) { + if (pin->input_val >> 24) + pin_id = pin->input_val >> 24 & 0xff; + } + pin_reg = &info->pin_regs[pin_id]; pin->pin = pin_id; grp->pin_ids[i] = pin_id; pin_reg->mux_reg = mux_reg; pin_reg->conf_reg = conf_reg; - pin->input_reg = be32_to_cpu(*list++); - pin->mux_mode = be32_to_cpu(*list++); - pin->input_val = be32_to_cpu(*list++); + pin_reg->base = info->base; + + if (info->flags & IOMUXC_LPSR_SUPPORT) { + if (pin->input_val >> 24) + pin_reg->base = info->base_lpsr; + } /* SION bit is in mux register */ config = be32_to_cpu(*list++); @@ -683,6 +702,7 @@ static int imx_pinctrl_probe_dt(struct platform_device *pdev, int imx_pinctrl_probe(struct platform_device *pdev, struct imx_pinctrl_soc_info *info) { + struct device_node *dev_np = pdev->dev.of_node; struct imx_pinctrl *ipctl; struct resource *res; int ret, i; @@ -709,9 +729,18 @@ int imx_pinctrl_probe(struct platform_device *pdev, } res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - ipctl->base = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(ipctl->base)) - return PTR_ERR(ipctl->base); + info->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(info->base)) + return PTR_ERR(info->base); + + if (info->flags & IOMUXC_LPSR_SUPPORT) { + info->base_lpsr = of_iomap(dev_np, 1); + if (IS_ERR(info->base_lpsr)) { + dev_err(&pdev->dev, + "iomuxc-lpsr base address not found\n"); + return PTR_ERR(info->base_lpsr); + } + } imx_pinctrl_desc.name = dev_name(&pdev->dev); imx_pinctrl_desc.pins = info->pins; diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h b/drivers/pinctrl/freescale/pinctrl-imx.h index 49e55d3..b3e00db 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.h +++ b/drivers/pinctrl/freescale/pinctrl-imx.h @@ -1,7 +1,7 @@ /* * IMX pinmux core definitions * - * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Copyright (C) 2012-2015 Freescale Semiconductor, Inc. * Copyright (C) 2012 Linaro Ltd. * * Author: Dong Aisheng <dong.aisheng@linaro.org> @@ -69,6 +69,7 @@ struct imx_pmx_func { struct imx_pin_reg { s16 mux_reg; s16 conf_reg; + void __iomem *base; }; struct imx_pinctrl_soc_info { @@ -81,9 +82,12 @@ struct imx_pinctrl_soc_info { struct imx_pmx_func *functions; unsigned int nfunctions; unsigned int flags; + void __iomem *base; + void __iomem *base_lpsr; }; #define SHARE_MUX_CONF_REG 0x1 +#define IOMUXC_LPSR_SUPPORT 0x2 #define NO_MUX 0x0 #define NO_PAD 0x0 -- 2.1.4 -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 3/4] ARM: imx: pinctrl-imx: imx7d: add support for iomuxc lpsr 2015-06-19 19:59 ` [PATCH 3/4] ARM: imx: pinctrl-imx: imx7d: add support for iomuxc lpsr Adrian Alonso @ 2015-06-19 20:26 ` Zhi Li 2015-07-14 7:57 ` Linus Walleij 1 sibling, 0 replies; 6+ messages in thread From: Zhi Li @ 2015-06-19 20:26 UTC (permalink / raw) To: Adrian Alonso Cc: linux-arm-kernel@lists.infradead.org, Shawn Guo, Shawn Guo, Linus Walleij, linux-gpio, devicetree@vger.kernel.org, Rob Herring, Anson.Huang, Frank.Li@freescale.com, yibin.gong, nitin.garg On Fri, Jun 19, 2015 at 2:59 PM, Adrian Alonso <aalonso@freescale.com> wrote: > * Extend pinctrl-imx driver to support iomux lpsr conntroller, > * iMX7D has two iomuxc controllers, iomuxc controller similar as > previous iMX SoC generation and iomuxc-lpsr which provides > low power state rentetion capabilities on gpios that are part of > iomuxc-lpsr (GPIO1_IO7..GPIO1_IO0). > * Use IOMUXC_LPSR_SUPPORT and iput_val most significant bits to > properly configure iomuxc/iomuxc-lpsr settings. > > Signed-off-by: Adrian Alonso <aalonso@freescale.com> > --- > drivers/pinctrl/freescale/pinctrl-imx.c | 75 +++++++++++++++++++++++---------- > drivers/pinctrl/freescale/pinctrl-imx.h | 6 ++- > 2 files changed, 57 insertions(+), 24 deletions(-) > > diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c > index d7b98ba..2d434ac 100644 > --- a/drivers/pinctrl/freescale/pinctrl-imx.c > +++ b/drivers/pinctrl/freescale/pinctrl-imx.c > @@ -1,7 +1,7 @@ > /* > * Core driver for the imx pin controller > * > - * Copyright (C) 2012 Freescale Semiconductor, Inc. > + * Copyright (C) 2012-2015 Freescale Semiconductor, Inc. > * Copyright (C) 2012 Linaro Ltd. > * > * Author: Dong Aisheng <dong.aisheng@linaro.org> > @@ -18,6 +18,7 @@ > #include <linux/module.h> > #include <linux/of.h> > #include <linux/of_device.h> > +#include <linux/of_address.h> > #include <linux/pinctrl/machine.h> > #include <linux/pinctrl/pinconf.h> > #include <linux/pinctrl/pinctrl.h> > @@ -38,7 +39,6 @@ > struct imx_pinctrl { > struct device *dev; > struct pinctrl_dev *pctl; > - void __iomem *base; > const struct imx_pinctrl_soc_info *info; > }; > > @@ -212,12 +212,12 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, > > if (info->flags & SHARE_MUX_CONF_REG) { > u32 reg; > - reg = readl(ipctl->base + pin_reg->mux_reg); > + reg = readl(pin_reg->base + pin_reg->mux_reg); > reg &= ~(0x7 << 20); > reg |= (pin->mux_mode << 20); > - writel(reg, ipctl->base + pin_reg->mux_reg); > + writel(reg, pin_reg->base + pin_reg->mux_reg); > } else { > - writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg); > + writel(pin->mux_mode, pin_reg->base + pin_reg->mux_reg); > } > dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", > pin_reg->mux_reg, pin->mux_mode); > @@ -245,16 +245,22 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, > * The input_reg[i] here is actually some IOMUXC general > * purpose register, not regular select input register. > */ > - val = readl(ipctl->base + pin->input_reg); > + val = readl(pin_reg->base + pin->input_reg); > val &= ~mask; > val |= select << shift; > - writel(val, ipctl->base + pin->input_reg); > + writel(val, pin_reg->base + pin->input_reg); > } else if (pin->input_reg) { > /* > * Regular select input register can never be at offset > * 0, and we only print register value for regular case. > */ > - writel(pin->input_val, ipctl->base + pin->input_reg); > + if (info->flags & IOMUXC_LPSR_SUPPORT && > + pin->input_val >> 24) { > + writel(pin->input_val, info->base + pin->input_reg); Please add comment here, LPSR select input register shared with normal IOMUX. > + } else { > + writel(pin->input_val, pin_reg->base + pin->input_reg); > + } > + > dev_dbg(ipctl->dev, > "==>select_input: offset 0x%x val 0x%x\n", > pin->input_reg, pin->input_val); > @@ -326,10 +332,10 @@ static int imx_pmx_gpio_request_enable(struct pinctrl_dev *pctldev, > return -EINVAL; > > mux_pin: > - reg = readl(ipctl->base + pin_reg->mux_reg); > + reg = readl(pin_reg->base + pin_reg->mux_reg); > reg &= ~(0x7 << 20); > reg |= imx_pin->config; > - writel(reg, ipctl->base + pin_reg->mux_reg); > + writel(reg, pin_reg->base + pin_reg->mux_reg); > > return 0; > } > @@ -354,12 +360,12 @@ static int imx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, > return -EINVAL; > > /* IBE always enabled allows us to read the value "on the wire" */ > - reg = readl(ipctl->base + pin_reg->mux_reg); > + reg = readl(pin_reg->base + pin_reg->mux_reg); > if (input) > reg &= ~0x2; > else > reg |= 0x2; > - writel(reg, ipctl->base + pin_reg->mux_reg); > + writel(reg, pin_reg->base + pin_reg->mux_reg); > > return 0; > } > @@ -386,7 +392,7 @@ static int imx_pinconf_get(struct pinctrl_dev *pctldev, > return -EINVAL; > } > > - *config = readl(ipctl->base + pin_reg->conf_reg); > + *config = readl(pin_reg->base + pin_reg->conf_reg); > > if (info->flags & SHARE_MUX_CONF_REG) > *config &= 0xffff; > @@ -415,12 +421,12 @@ static int imx_pinconf_set(struct pinctrl_dev *pctldev, > for (i = 0; i < num_configs; i++) { > if (info->flags & SHARE_MUX_CONF_REG) { > u32 reg; > - reg = readl(ipctl->base + pin_reg->conf_reg); > + reg = readl(pin_reg->base + pin_reg->conf_reg); > reg &= ~0xffff; > reg |= configs[i]; > - writel(reg, ipctl->base + pin_reg->conf_reg); > + writel(reg, pin_reg->base + pin_reg->conf_reg); > } else { > - writel(configs[i], ipctl->base + pin_reg->conf_reg); > + writel(configs[i], pin_reg->base + pin_reg->conf_reg); > } > dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n", > pin_reg->conf_reg, configs[i]); > @@ -442,7 +448,7 @@ static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev, > return; > } > > - config = readl(ipctl->base + pin_reg->conf_reg); > + config = readl(pin_reg->base + pin_reg->conf_reg); > seq_printf(s, "0x%lx", config); > } > > @@ -551,14 +557,27 @@ static int imx_pinctrl_parse_groups(struct device_node *np, > } > > pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4; > + > + pin->input_reg = be32_to_cpu(*list++); > + pin->mux_mode = be32_to_cpu(*list++); > + pin->input_val = be32_to_cpu(*list++); > + > + if (info->flags & IOMUXC_LPSR_SUPPORT) { > + if (pin->input_val >> 24) > + pin_id = pin->input_val >> 24 & 0xff; > + } > + It limited normal pin_id is 255 - number of lpsr, which many too small and easy exceed in future chip. I think it'd better at least 4096. or 16bit, 65536. > pin_reg = &info->pin_regs[pin_id]; > pin->pin = pin_id; > grp->pin_ids[i] = pin_id; > pin_reg->mux_reg = mux_reg; > pin_reg->conf_reg = conf_reg; > - pin->input_reg = be32_to_cpu(*list++); > - pin->mux_mode = be32_to_cpu(*list++); > - pin->input_val = be32_to_cpu(*list++); > + pin_reg->base = info->base; > + > + if (info->flags & IOMUXC_LPSR_SUPPORT) { > + if (pin->input_val >> 24) > + pin_reg->base = info->base_lpsr; > + } > > /* SION bit is in mux register */ > config = be32_to_cpu(*list++); > @@ -683,6 +702,7 @@ static int imx_pinctrl_probe_dt(struct platform_device *pdev, > int imx_pinctrl_probe(struct platform_device *pdev, > struct imx_pinctrl_soc_info *info) > { > + struct device_node *dev_np = pdev->dev.of_node; > struct imx_pinctrl *ipctl; > struct resource *res; > int ret, i; > @@ -709,9 +729,18 @@ int imx_pinctrl_probe(struct platform_device *pdev, > } > > res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > - ipctl->base = devm_ioremap_resource(&pdev->dev, res); > - if (IS_ERR(ipctl->base)) > - return PTR_ERR(ipctl->base); > + info->base = devm_ioremap_resource(&pdev->dev, res); > + if (IS_ERR(info->base)) > + return PTR_ERR(info->base); > + > + if (info->flags & IOMUXC_LPSR_SUPPORT) { > + info->base_lpsr = of_iomap(dev_np, 1); > + if (IS_ERR(info->base_lpsr)) { > + dev_err(&pdev->dev, > + "iomuxc-lpsr base address not found\n"); > + return PTR_ERR(info->base_lpsr); > + } > + } > > imx_pinctrl_desc.name = dev_name(&pdev->dev); > imx_pinctrl_desc.pins = info->pins; > diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h b/drivers/pinctrl/freescale/pinctrl-imx.h > index 49e55d3..b3e00db 100644 > --- a/drivers/pinctrl/freescale/pinctrl-imx.h > +++ b/drivers/pinctrl/freescale/pinctrl-imx.h > @@ -1,7 +1,7 @@ > /* > * IMX pinmux core definitions > * > - * Copyright (C) 2012 Freescale Semiconductor, Inc. > + * Copyright (C) 2012-2015 Freescale Semiconductor, Inc. > * Copyright (C) 2012 Linaro Ltd. > * > * Author: Dong Aisheng <dong.aisheng@linaro.org> > @@ -69,6 +69,7 @@ struct imx_pmx_func { > struct imx_pin_reg { > s16 mux_reg; > s16 conf_reg; > + void __iomem *base; > }; > > struct imx_pinctrl_soc_info { > @@ -81,9 +82,12 @@ struct imx_pinctrl_soc_info { > struct imx_pmx_func *functions; > unsigned int nfunctions; > unsigned int flags; > + void __iomem *base; > + void __iomem *base_lpsr; > }; > > #define SHARE_MUX_CONF_REG 0x1 > +#define IOMUXC_LPSR_SUPPORT 0x2 > > #define NO_MUX 0x0 > #define NO_PAD 0x0 > -- > 2.1.4 > -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 3/4] ARM: imx: pinctrl-imx: imx7d: add support for iomuxc lpsr 2015-06-19 19:59 ` [PATCH 3/4] ARM: imx: pinctrl-imx: imx7d: add support for iomuxc lpsr Adrian Alonso 2015-06-19 20:26 ` Zhi Li @ 2015-07-14 7:57 ` Linus Walleij 1 sibling, 0 replies; 6+ messages in thread From: Linus Walleij @ 2015-07-14 7:57 UTC (permalink / raw) To: Adrian Alonso, Shawn Guo Cc: linux-arm-kernel@lists.infradead.org, 李智, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, Rob Herring, Anson.Huang@freescale.com, Frank.Li, yibin.gong, nitin.garg On Fri, Jun 19, 2015 at 9:59 PM, Adrian Alonso <aalonso@freescale.com> wrote: > * Extend pinctrl-imx driver to support iomux lpsr conntroller, > * iMX7D has two iomuxc controllers, iomuxc controller similar as > previous iMX SoC generation and iomuxc-lpsr which provides > low power state rentetion capabilities on gpios that are part of > iomuxc-lpsr (GPIO1_IO7..GPIO1_IO0). > * Use IOMUXC_LPSR_SUPPORT and iput_val most significant bits to > properly configure iomuxc/iomuxc-lpsr settings. > > Signed-off-by: Adrian Alonso <aalonso@freescale.com> I'm waiting for Shawn's ACK on this before I do anything, and you also need to address Zhi Li's comments. (Or there is already such a version higher up in my mailbox, in that case, sorry.) Yours, Linus Walleij ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 4/4] ARM: imx: pinctrl-imx7d: add iomuxc-lpsr gpio group ids 2015-06-19 19:59 [PATCH 1/4] ARM: imx: imx7d-pinfunc: add gpio pad iomuxc settings Adrian Alonso 2015-06-19 19:59 ` [PATCH 2/4] ARM: dts: imx: imx7d add iomuxc lpsr register base address Adrian Alonso 2015-06-19 19:59 ` [PATCH 3/4] ARM: imx: pinctrl-imx: imx7d: add support for iomuxc lpsr Adrian Alonso @ 2015-06-19 19:59 ` Adrian Alonso 2 siblings, 0 replies; 6+ messages in thread From: Adrian Alonso @ 2015-06-19 19:59 UTC (permalink / raw) To: linux-arm-kernel, shawn.guo, shawnguo, linus.walleij, lznuaa Cc: linux-gpio, devicetree, robh+dt, Anson.Huang, Frank.Li, yibin.gong, nitin.garg * Add imx7d SoC iomuxc-lpsr gpio group id's * Add IOMUXC_LPSR_SUPPORT flag for pinctrl-imx driver to support iomuxc-lpsr controller. Signed-off-by: Adrian Alonso <aalonso@freescale.com> --- drivers/pinctrl/freescale/pinctrl-imx7d.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/pinctrl/freescale/pinctrl-imx7d.c b/drivers/pinctrl/freescale/pinctrl-imx7d.c index 1fa7530..cf89275 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx7d.c +++ b/drivers/pinctrl/freescale/pinctrl-imx7d.c @@ -172,6 +172,14 @@ enum imx7d_pads { MX7D_PAD_ENET1_RX_CLK = 152, MX7D_PAD_ENET1_CRS = 153, MX7D_PAD_ENET1_COL = 154, + MX7D_PAD_GPIO1_IO00 = 155, + MX7D_PAD_GPIO1_IO01 = 156, + MX7D_PAD_GPIO1_IO02 = 157, + MX7D_PAD_GPIO1_IO03 = 158, + MX7D_PAD_GPIO1_IO04 = 159, + MX7D_PAD_GPIO1_IO05 = 160, + MX7D_PAD_GPIO1_IO06 = 161, + MX7D_PAD_GPIO1_IO07 = 162, }; /* Pad names for the pinmux subsystem */ @@ -331,11 +339,20 @@ static const struct pinctrl_pin_desc imx7d_pinctrl_pads[] = { IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RX_CLK), IMX_PINCTRL_PIN(MX7D_PAD_ENET1_CRS), IMX_PINCTRL_PIN(MX7D_PAD_ENET1_COL), + IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO00), + IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO01), + IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO02), + IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO03), + IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO04), + IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO05), + IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO06), + IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO07), }; static struct imx_pinctrl_soc_info imx7d_pinctrl_info = { .pins = imx7d_pinctrl_pads, .npins = ARRAY_SIZE(imx7d_pinctrl_pads), + .flags = IOMUXC_LPSR_SUPPORT, }; static struct of_device_id imx7d_pinctrl_of_match[] = { -- 2.1.4 -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in ^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2015-07-14 7:57 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2015-06-19 19:59 [PATCH 1/4] ARM: imx: imx7d-pinfunc: add gpio pad iomuxc settings Adrian Alonso 2015-06-19 19:59 ` [PATCH 2/4] ARM: dts: imx: imx7d add iomuxc lpsr register base address Adrian Alonso 2015-06-19 19:59 ` [PATCH 3/4] ARM: imx: pinctrl-imx: imx7d: add support for iomuxc lpsr Adrian Alonso 2015-06-19 20:26 ` Zhi Li 2015-07-14 7:57 ` Linus Walleij 2015-06-19 19:59 ` [PATCH 4/4] ARM: imx: pinctrl-imx7d: add iomuxc-lpsr gpio group ids Adrian Alonso
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