[PATCH 0/4] Add basic support for Allwinner A83T SOC

linux-gpio.vger.kernel.org archive mirror
 help / color / mirror / Atom feed

* [PATCH 0/4] Add basic support for Allwinner A83T SOC
@ 2015-09-22 15:38 Vishnu Patekar
       [not found] ` <1442936337-3104-1-git-send-email-vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
  0 siblings, 1 reply; 19+ messages in thread
From: Vishnu Patekar @ 2015-09-22 15:38 UTC (permalink / raw)
  To: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, pawel.moll-5wv7dgnIgG8,
	mark.rutland-5wv7dgnIgG8, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
	galak-sgV2jX0FEOL9JmXXK+q4OQ,
	maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
	linux-lFZ/pmaqli7XmaaqVzeoHQ, emilio-0Z03zUJReD5OxF6Tv1QG9Q,
	linus.walleij-QSEj5FYQhm4dnm+yROfE0A
  Cc: jenskuske-Re5JQEeQqe8AvxtiuMwx3w, hdegoede-H+wXaHxf7aLQT0dZR+AlfA,
	wens-jdAy2FN1RRM, devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	linux-sunxi-/JYPxA39Uh5TLH3MbocFFw,
	linux-gpio-u79uwXL29TY76Z2rM5mHXA, Vishnu Patekar

This patch series adds very basic support for Allwinner A83T SOC.
Clock, peripherals, smp support will be added later.

Allwinner A83T is octa-core cortex-a7 based SoC.
It's clock control unit and prcm, pinmux are different from previous sun8i
series.
Its processor cores are arragned in two clusters 4 cores each,
similar to A80.

Patch1 This adds compatibe string for A83T
Patch2	adds PIO controller support R_PIO is yet to be added.
Patch3	adds basic dtsi
Patch4	Adds Alllwinner A83T Homletv2 board dts.

Vishnu Patekar (4):
  ARM: sunxi: Introduce Allwinner for A83T support
  pinctrl: sunxi: add allwinner A83T PIO controller support
  ARM: dts: sun8i: Add Allwinner A83T dtsi
  ARM: dts: sun8i: Add A83T HomletV2 Board by Allwinner

 Documentation/devicetree/bindings/arm/sunxi.txt    |   1 +
 .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt   |   1 +
 arch/arm/boot/dts/Makefile                         |   5 +-
 .../boot/dts/sun8i-a83t-allwinner-homlet-v20.dts   |  69 +++
 arch/arm/boot/dts/sun8i-a83t.dtsi                  | 243 +++++++++
 arch/arm/mach-sunxi/sunxi.c                        |   1 +
 drivers/clk/sunxi/clk-sunxi.c                      |   6 +
 drivers/pinctrl/sunxi/Kconfig                      |   4 +
 drivers/pinctrl/sunxi/Makefile                     |   1 +
 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c         | 603 +++++++++++++++++++++
 10 files changed, 932 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/boot/dts/sun8i-a83t-allwinner-homlet-v20.dts
 create mode 100644 arch/arm/boot/dts/sun8i-a83t.dtsi
 create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c

-- 
1.9.1

^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH 1/4] ARM: sunxi: Introduce Allwinner for A83T support
       [not found] ` <1442936337-3104-1-git-send-email-vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
@ 2015-09-22 15:38   ` Vishnu Patekar
       [not found]     ` <1442936337-3104-2-git-send-email-vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
  2015-09-22 15:38   ` [PATCH 2/4] pinctrl: sunxi: add allwinner A83T PIO controller support Vishnu Patekar
                     ` (2 subsequent siblings)
  3 siblings, 1 reply; 19+ messages in thread
From: Vishnu Patekar @ 2015-09-22 15:38 UTC (permalink / raw)
  To: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, pawel.moll-5wv7dgnIgG8,
	mark.rutland-5wv7dgnIgG8, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
	galak-sgV2jX0FEOL9JmXXK+q4OQ,
	maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
	linux-lFZ/pmaqli7XmaaqVzeoHQ, emilio-0Z03zUJReD5OxF6Tv1QG9Q,
	linus.walleij-QSEj5FYQhm4dnm+yROfE0A
  Cc: jenskuske-Re5JQEeQqe8AvxtiuMwx3w, hdegoede-H+wXaHxf7aLQT0dZR+AlfA,
	wens-jdAy2FN1RRM, devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	linux-sunxi-/JYPxA39Uh5TLH3MbocFFw,
	linux-gpio-u79uwXL29TY76Z2rM5mHXA, Vishnu Patekar

Allwinner A83T is octa-core cortex-a7 based SoC.
It's clock control unit and prcm, pinmux are different from previous sun8i
series.
Its processor cores are arragned in two clusters 4 cores each,
similar to A80.

Signed-off-by: Vishnu Patekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
 arch/arm/mach-sunxi/sunxi.c                     | 1 +
 drivers/clk/sunxi/clk-sunxi.c                   | 6 ++++++
 3 files changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt
index 67da205..cf5ed27 100644
--- a/Documentation/devicetree/bindings/arm/sunxi.txt
+++ b/Documentation/devicetree/bindings/arm/sunxi.txt
@@ -11,4 +11,5 @@ using one of the following compatible strings:
   allwinner,sun8i-a23
   allwinner,sun8i-a33
   allwinner,sun8i-h3
+  allwinner,sun8i-a83t
   allwinner,sun9i-a80
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 65bab28..b04aefa 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -69,6 +69,7 @@ static const char * const sun8i_board_dt_compat[] = {
 	"allwinner,sun8i-a23",
 	"allwinner,sun8i-a33",
 	"allwinner,sun8i-h3",
+	"allwinner,sun8i-a83t",
 	NULL,
 };
 
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 413070d..f216d5d 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -1212,6 +1212,12 @@ CLK_OF_DECLARE(sun6i_a31s_clk_init, "allwinner,sun6i-a31s", sun6i_init_clocks);
 CLK_OF_DECLARE(sun8i_a23_clk_init, "allwinner,sun8i-a23", sun6i_init_clocks);
 CLK_OF_DECLARE(sun8i_a33_clk_init, "allwinner,sun8i-a33", sun6i_init_clocks);
 
+static void __init sun8ia83t_init_clocks(struct device_node *node)
+{
+	sunxi_init_clocks(NULL, 0);
+}
+CLK_OF_DECLARE(sun9i_a83t_clk_init, "allwinner,sun8i-a83t", sun8ia83t_init_clocks);
+
 static void __init sun9i_init_clocks(struct device_node *node)
 {
 	sunxi_init_clocks(NULL, 0);
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH 2/4] pinctrl: sunxi: add allwinner A83T PIO controller support
       [not found] ` <1442936337-3104-1-git-send-email-vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
  2015-09-22 15:38   ` [PATCH 1/4] ARM: sunxi: Introduce Allwinner for A83T support Vishnu Patekar
@ 2015-09-22 15:38   ` Vishnu Patekar
       [not found]     ` <1442936337-3104-3-git-send-email-vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
  2015-10-02 11:10     ` Linus Walleij
  2015-09-22 15:38   ` [PATCH 3/4] ARM: dts: sun8i: Add Allwinner A83T dtsi Vishnu Patekar
  2015-09-22 15:38   ` [PATCH 4/4] ARM: dts: sun8i: Add A83T HomletV2 Board by Allwinner Vishnu Patekar
  3 siblings, 2 replies; 19+ messages in thread
From: Vishnu Patekar @ 2015-09-22 15:38 UTC (permalink / raw)
  To: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, pawel.moll-5wv7dgnIgG8,
	mark.rutland-5wv7dgnIgG8, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
	galak-sgV2jX0FEOL9JmXXK+q4OQ,
	maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
	linux-lFZ/pmaqli7XmaaqVzeoHQ, emilio-0Z03zUJReD5OxF6Tv1QG9Q,
	linus.walleij-QSEj5FYQhm4dnm+yROfE0A
  Cc: jenskuske-Re5JQEeQqe8AvxtiuMwx3w, hdegoede-H+wXaHxf7aLQT0dZR+AlfA,
	wens-jdAy2FN1RRM, devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	linux-sunxi-/JYPxA39Uh5TLH3MbocFFw,
	linux-gpio-u79uwXL29TY76Z2rM5mHXA, Vishnu Patekar

Allwinner A83T soc port controller has 8 ports.
It has 3 IRQ banks namely PB, PG, PH.
Pinmuxing are different for some pins as compared to
sun8i A23 and A33.

Signed-off-by: Vishnu Patekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt   |   1 +
 drivers/pinctrl/sunxi/Kconfig                      |   4 +
 drivers/pinctrl/sunxi/Makefile                     |   1 +
 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c         | 603 +++++++++++++++++++++
 4 files changed, 609 insertions(+)
 create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c

diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index 3c821cd..b321b26 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -17,6 +17,7 @@ Required properties:
   "allwinner,sun8i-a23-pinctrl"
   "allwinner,sun8i-a23-r-pinctrl"
   "allwinner,sun8i-a33-pinctrl"
+  "allwinner,sun8i-a83t-pinctrl"
 
 - reg: Should contain the register physical address and length for the
   pin controller.
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index ae27872..e68fd95 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -42,6 +42,10 @@ config PINCTRL_SUN8I_A33
 	def_bool MACH_SUN8I
 	select PINCTRL_SUNXI_COMMON
 
+config PINCTRL_SUN8I_A83T
+	def_bool MACH_SUN8I
+	select PINCTRL_SUNXI_COMMON
+
 config PINCTRL_SUN8I_A23_R
 	def_bool MACH_SUN8I
 	depends on RESET_CONTROLLER
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index 227a121..e080290 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -12,4 +12,5 @@ obj-$(CONFIG_PINCTRL_SUN7I_A20)		+= pinctrl-sun7i-a20.o
 obj-$(CONFIG_PINCTRL_SUN8I_A23)		+= pinctrl-sun8i-a23.o
 obj-$(CONFIG_PINCTRL_SUN8I_A23_R)	+= pinctrl-sun8i-a23-r.o
 obj-$(CONFIG_PINCTRL_SUN8I_A33)		+= pinctrl-sun8i-a33.o
+obj-$(CONFIG_PINCTRL_SUN8I_A83T)	+= pinctrl-sun8i-a83t.o
 obj-$(CONFIG_PINCTRL_SUN9I_A80)		+= pinctrl-sun9i-a80.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c
new file mode 100644
index 0000000..90b973e
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c
@@ -0,0 +1,603 @@
+/*
+ * Allwinner a83t SoCs pinctrl driver.
+ *
+ * Copyright (C) 2015 Vishnu Patekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
+ *
+ * Based on pinctrl-sun8i-a23.c, which is:
+ * Copyright (C) 2014 Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
+ * Copyright (C) 2014 Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-sunxi.h"
+
+static const struct sunxi_desc_pin sun8i_a83t_pins[] = {
+	/* Hole */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "uart2"),		/* TX */
+		  SUNXI_FUNCTION(0x3, "jtag"),		/* MS0 */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),	/* PB_EINT0 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "uart2"),		/* RX */
+		  SUNXI_FUNCTION(0x3, "jtag"),		/* CK0 */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),	/* PB_EINT1 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "uart2"),		/* RTS */
+		  SUNXI_FUNCTION(0x3, "jtag"),		/* DO0 */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),	/* PB_EINT2 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "uart2"),		/* CTS */
+		  SUNXI_FUNCTION(0x3, "jtag"),		/* DI0 */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),	/* PB_EINT3 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "i2s0"),		/* LRCK */
+		  SUNXI_FUNCTION(0x3, "tdm"),		/* LRCK */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),	/* PB_EINT4 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "i2s0"),		/* BCLK */
+		  SUNXI_FUNCTION(0x3, "tdm"),		/* BCLK */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),	/* PB_EINT5 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "i2s0"),		/* DOUT */
+		  SUNXI_FUNCTION(0x3, "tdm"),		/* DOUT */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),	/* PB_EINT6 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "i2s0"),		/* DIN */
+		  SUNXI_FUNCTION(0x3, "tdm"),		/* DIN */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),	/* PB_EINT7 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "i2s0"),		/* MCLK */
+		  SUNXI_FUNCTION(0x3, "tdm"),		/* MCLK */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),	/* PB_EINT8 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "uart0"),		/* TX */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),	/* PB_EINT9 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "uart0"),		/* RX */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)),	/* PB_EINT10 */
+	/* Hole */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand0"),		/* WE */
+		  SUNXI_FUNCTION(0x3, "spi0")),		/* MOSI */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand0"),		/* ALE */
+		  SUNXI_FUNCTION(0x3, "spi0")),		/* MISO */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand0"),		/* CLE */
+		  SUNXI_FUNCTION(0x3, "spi0")),		/* CLK */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand0"),		/* CE1 */
+		  SUNXI_FUNCTION(0x3, "spi0")),		/* CS */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand0")),	/* CE0 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand0"),		/* RE */
+		  SUNXI_FUNCTION(0x3, "mmc2")),		/* CLK */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand0"),		/* RB0 */
+		  SUNXI_FUNCTION(0x3, "mmc2")),		/* CMD */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand0")),	/* RB1 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQ0 */
+		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D0 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQ1 */
+		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D1 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQ2 */
+		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D2 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQ3 */
+		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D3 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQ4 */
+		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D4 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand0"),		/* DQ5 */
+		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D5 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand"),		/* DQ6 */
+		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D6 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand"),		/* DQ7 */
+		  SUNXI_FUNCTION(0x3, "mmc2")),		/* D7 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand"),		/* DQS */
+		  SUNXI_FUNCTION(0x3, "mmc2")),		/* RST */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand")),		/* CE2 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "nand")),		/* CE3 */
+	/* Hole */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D2 */
+		  SUNXI_FUNCTION(0x4, "gmac")),		/* RGMII / MII RXD3 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D3 */
+		  SUNXI_FUNCTION(0x4, "gmac")),		/* RGMII / MII RXD2 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D4 */
+		  SUNXI_FUNCTION(0x4, "gmac")),		/* RGMII / MII RXD1 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D5 */
+		  SUNXI_FUNCTION(0x4, "gmac")),		/* RGMII / MII RXD0 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D6 */
+		  SUNXI_FUNCTION(0x4, "gmac")),		/* RGMII / MII RXCK */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D7 */
+		  SUNXI_FUNCTION(0x4, "gmac")),		/* RGMII / MII RXDV */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D10 */
+		  SUNXI_FUNCTION(0x4, "gmac")),		/* RGMII / MII RXERR */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D11 */
+		  SUNXI_FUNCTION(0x4, "gmac")),		/* RGMII / MII TXD3 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D12 */
+		  SUNXI_FUNCTION(0x4, "gmac")),		/* RGMII / MII TXD2 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D13 */
+		  SUNXI_FUNCTION(0x4, "gmac")),		/* RGMII / MII TXD1 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D14 */
+		  SUNXI_FUNCTION(0x4, "gmac")),		/* RGMII / MII TXD0 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D15 */
+		  SUNXI_FUNCTION(0x4, "gmac")),	/* RGMII-NULL / MII-CRS */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D18 */
+		  SUNXI_FUNCTION(0x3, "lvds0"),		/* VP0 */
+		  SUNXI_FUNCTION(0x4, "gmac")),		/* GTXCK / ETXCK */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D19 */
+		  SUNXI_FUNCTION(0x3, "lvds0"),		/* VN0 */
+		  SUNXI_FUNCTION(0x4, "gmac")),		/* GTXCTL / ETXEL */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D20 */
+		  SUNXI_FUNCTION(0x3, "lvds0"),		/* VP1 */
+		  SUNXI_FUNCTION(0x4, "gmac")),		/* GNULL / ETXERR */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D21 */
+		  SUNXI_FUNCTION(0x3, "lvds0"),		/* VN1 */
+		  SUNXI_FUNCTION(0x4, "gmac")),		/* GCLKIN / ECOL */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D22 */
+		  SUNXI_FUNCTION(0x3, "lvds0"),		/* VP2 */
+		  SUNXI_FUNCTION(0x4, "gmac")),		/* GMDC */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* D23 */
+		  SUNXI_FUNCTION(0x3, "lvds0"),		/* VN2 */
+		  SUNXI_FUNCTION(0x4, "gmac")),		/* GMDIO */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* CLK */
+		  SUNXI_FUNCTION(0x3, "lvds0")),	/* VPC */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* DE */
+		  SUNXI_FUNCTION(0x3, "lvds0")),	/* VNC */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* HSYNC */
+		  SUNXI_FUNCTION(0x3, "lvds0")),	/* VP3 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "lcd0"),		/* VSYNC */
+		  SUNXI_FUNCTION(0x3, "lvds0")),	/* VN3 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 28),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "pwm")),		/* PWM */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 29),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out")),
+	/* Hole */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "csi"),		/* PCLK */
+		  SUNXI_FUNCTION(0x4, "ccir")),		/* CLK */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "csi"),		/* MCLK */
+		  SUNXI_FUNCTION(0x4, "ccir")),		/* DE */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "csi"),		/* HSYNC */
+		  SUNXI_FUNCTION(0x4, "ccir")),		/* HSYNC */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "csi"),		/* VSYNC */
+		  SUNXI_FUNCTION(0x4, "ccir")),		/* VSYNC */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "csi")),		/* D0 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "csi")),		/* D1 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "csi"),		/* D2 */
+		  SUNXI_FUNCTION(0x4, "ccir")),		/* D0 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "csi"),		/* D3 */
+		  SUNXI_FUNCTION(0x4, "ccir")),		/* D1 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "csi"),		/* D4 */
+		  SUNXI_FUNCTION(0x4, "ccir")),		/* D2 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "csi"),		/* D5 */
+		  SUNXI_FUNCTION(0x4, "ccir")),		/* D3 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "csi"),		/* D6 */
+		  SUNXI_FUNCTION(0x3, "uart4"),		/* TX */
+		  SUNXI_FUNCTION(0x4, "ccir")),		/* D4 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "csi"),		/* D7 */
+		  SUNXI_FUNCTION(0x3, "uart4"),		/* RX */
+		  SUNXI_FUNCTION(0x4, "ccir")),		/* D5 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "csi"),		/* D8 */
+		  SUNXI_FUNCTION(0x3, "uart4"),		/* RTS */
+		  SUNXI_FUNCTION(0x4, "ccir")),		/* D6 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "csi"),		/* D9 */
+		  SUNXI_FUNCTION(0x3, "uart4"),		/* CTS */
+		  SUNXI_FUNCTION(0x4, "ccir")),		/* D7 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "csi"),		/* SCK */
+		  SUNXI_FUNCTION(0x3, "i2c2")),		/* SCK */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "csi"),		/* SDA */
+		  SUNXI_FUNCTION(0x3, "i2c2")),		/* SDA */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out")),
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out")),
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 18),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x3, "owa")),		/* DOUT */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 19),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out")),
+	/* Hole */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "mmc0"),		/* D1 */
+		  SUNXI_FUNCTION(0x3, "jtag")),		/* MS1 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "mmc0"),		/* D0 */
+		  SUNXI_FUNCTION(0x3, "jtag")),		/* DI1 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "mmc0"),		/* CLK */
+		  SUNXI_FUNCTION(0x3, "uart0")),	/* TX */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "mmc0"),		/* CMD */
+		  SUNXI_FUNCTION(0x3, "jtag")),		/* DO1 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "mmc0"),		/* D3 */
+		  SUNXI_FUNCTION(0x3, "uart0")),	/* RX */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "mmc0"),		/* D2 */
+		  SUNXI_FUNCTION(0x3, "jtag")),		/* CK1 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out")),
+	/* Hole */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "mmc1"),		/* CLK */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)),	/* PG_EINT0 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "mmc1"),		/* CMD */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)),	/* PG_EINT1 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "mmc1"),		/* D0 */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)),	/* PG_EINT2 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "mmc1"),		/* D1 */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)),	/* PG_EINT3 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "mmc1"),		/* D2 */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)),	/* PG_EINT4 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "mmc1"),		/* D3 */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)),	/* PG_EINT5 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "uart1"),		/* TX */
+		  SUNXI_FUNCTION(0x3, "spi1"),		/* CS */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)),	/* PG_EINT6 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "uart1"),		/* RX */
+		  SUNXI_FUNCTION(0x3, "spi1"),		/* CLK */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)),	/* PG_EINT7 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "uart1"),		/* RTS */
+		  SUNXI_FUNCTION(0x3, "spi1"),		/* MOSI */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)),	/* PG_EINT8 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "uart1"),		/* CTS */
+		  SUNXI_FUNCTION(0x3, "spi1"),		/* MISO */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)),	/* PG_EINT9 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "i2s1"),		/* BCLK */
+		  SUNXI_FUNCTION(0x3, "uart3"),		/* TX */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)),	/* PG_EINT10 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "i2s1"),		/* LRCK */
+		  SUNXI_FUNCTION(0x3, "uart3"),		/* RX */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)),	/* PG_EINT11 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "i2s1"),		/* DOUT */
+		  SUNXI_FUNCTION(0x3, "uart3"),		/* RTS */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)),	/* PG_EINT12 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "i2s1"),		/* DIN */
+		  SUNXI_FUNCTION(0x3, "uart3"),		/* CTS */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)),	/* PG_EINT13 */
+	/* Hole */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "i2c0"),		/* SCK */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)),	/* PH_EINT0 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "i2c0"),		/* SDA */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)),	/* PH_EINT1 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "i2c1"),		/* SCK */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)),	/* PH_EINT2 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "i2c1"),		/* SDA */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)),	/* PH_EINT3 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "i2c2"),		/* SCK */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)),	/* PH_EINT4 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "i2c2"),		/* SDA */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)),	/* PH_EINT5 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "hdmi"),		/* HSCL */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)),	/* PH_EINT6 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "hdmi"),		/* HSDA */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)),	/* PH_EINT7 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "hdmi"),		/* HCEC */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)),	/* PH_EINT8 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)),	/* PH_EINT9 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)),	/* PH_EINT10 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)),	/* PH_EINT11 */
+};
+
+static const struct sunxi_pinctrl_desc sun8i_a83t_pinctrl_data = {
+	.pins = sun8i_a83t_pins,
+	.npins = ARRAY_SIZE(sun8i_a83t_pins),
+	.irq_banks = 3,
+};
+
+static int sun8i_a83t_pinctrl_probe(struct platform_device *pdev)
+{
+	return sunxi_pinctrl_init(pdev,
+				  &sun8i_a83t_pinctrl_data);
+}
+
+static const struct of_device_id sun8i_a83t_pinctrl_match[] = {
+	{ .compatible = "allwinner,sun8i-a83t-pinctrl", },
+	{}
+};
+MODULE_DEVICE_TABLE(of, sun8i_a83t_pinctrl_match);
+
+static struct platform_driver sun8i_a83t_pinctrl_driver = {
+	.probe	= sun8i_a83t_pinctrl_probe,
+	.driver	= {
+		.name		= "sun8i-a83t-pinctrl",
+		.of_match_table	= sun8i_a83t_pinctrl_match,
+	},
+};
+module_platform_driver(sun8i_a83t_pinctrl_driver);
+
+MODULE_AUTHOR("Vishnu Patekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>");
+MODULE_DESCRIPTION("Allwinner a83t pinctrl driver");
+MODULE_LICENSE("GPL");
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH 3/4] ARM: dts: sun8i: Add Allwinner A83T dtsi
       [not found] ` <1442936337-3104-1-git-send-email-vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
  2015-09-22 15:38   ` [PATCH 1/4] ARM: sunxi: Introduce Allwinner for A83T support Vishnu Patekar
  2015-09-22 15:38   ` [PATCH 2/4] pinctrl: sunxi: add allwinner A83T PIO controller support Vishnu Patekar
@ 2015-09-22 15:38   ` Vishnu Patekar
       [not found]     ` <1442936337-3104-4-git-send-email-vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
  2015-09-22 15:38   ` [PATCH 4/4] ARM: dts: sun8i: Add A83T HomletV2 Board by Allwinner Vishnu Patekar
  3 siblings, 1 reply; 19+ messages in thread
From: Vishnu Patekar @ 2015-09-22 15:38 UTC (permalink / raw)
  To: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, pawel.moll-5wv7dgnIgG8,
	mark.rutland-5wv7dgnIgG8, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
	galak-sgV2jX0FEOL9JmXXK+q4OQ,
	maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
	linux-lFZ/pmaqli7XmaaqVzeoHQ, emilio-0Z03zUJReD5OxF6Tv1QG9Q,
	linus.walleij-QSEj5FYQhm4dnm+yROfE0A
  Cc: jenskuske-Re5JQEeQqe8AvxtiuMwx3w, hdegoede-H+wXaHxf7aLQT0dZR+AlfA,
	wens-jdAy2FN1RRM, devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	linux-sunxi-/JYPxA39Uh5TLH3MbocFFw,
	linux-gpio-u79uwXL29TY76Z2rM5mHXA, Vishnu Patekar

Allwinner A83T is new octa-core cortex-a7 SOC.
This adds the basic dtsi, the clocks differs from
earlier sun8i SOCs.

Signed-off-by: Vishnu Patekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 243 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 243 insertions(+)
 create mode 100644 arch/arm/boot/dts/sun8i-a83t.dtsi

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
new file mode 100644
index 0000000..f6ddd9c
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -0,0 +1,243 @@
+/*
+ * Copyright 2015 Vishnu Patekar
+ *
+ * Vishnu Patekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+
+ */
+
+#include "skeleton.dtsi"
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+	interrupt-parent = <&gic>;
+
+	chosen {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <0>;
+		};
+
+		cpu@1 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <1>;
+		};
+
+		cpu@2 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <2>;
+		};
+
+		cpu@3 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <3>;
+		};
+		cpu@4 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <4>;
+		};
+
+		cpu@5 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <5>;
+		};
+		cpu@6 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <6>;
+		};
+
+		cpu@7 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <7>;
+		};
+	};
+
+	memory {
+		reg = <0x40000000 0x80000000>;
+	};
+
+	timer {
+		compatible = "arm,armv7-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+		clock-frequency = <24000000>;
+		arm,cpu-registers-not-fw-configured;
+	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		osc24M: osc24M_clk {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <24000000>;
+			clock-output-names = "osc24M";
+		};
+
+		osc32k: osc32k_clk {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <32768>;
+			clock-output-names = "osc32k";
+		};
+	};
+
+	soc@01c00000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		pio: pinctrl@01c20800 {
+			compatible = "allwinner,sun8i-a83t-pinctrl";
+			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+			/* compatible gets set in SoC specific dtsi file */
+			reg = <0x01c20800 0x400>;
+			/* interrupts get set in SoC specific dtsi file */
+			clocks = <&osc24M>;
+			gpio-controller;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			#gpio-cells = <3>;
+
+			uart0_pins_a: uart0@0 {
+				allwinner,pins = "PF2", "PF4";
+				allwinner,function = "uart0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			mmc0_pins_a: mmc0@0 {
+				allwinner,pins = "PF0", "PF1", "PF2",
+						 "PF3", "PF4", "PF5";
+				allwinner,function = "mmc0";
+				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			mmc1_pins_a: mmc1@0 {
+				allwinner,pins = "PG0", "PG1", "PG2",
+						 "PG3", "PG4", "PG5";
+				allwinner,function = "mmc1";
+				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			mmc2_8bit_pins: mmc2_8bit {
+				allwinner,pins = "PC5", "PC6", "PC8",
+						 "PC9", "PC10", "PC11",
+						 "PC12", "PC13", "PC14",
+						 "PC15";
+				allwinner,function = "mmc2";
+				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			i2c0_pins_a: i2c0@0 {
+				allwinner,pins = "PH0", "PH1";
+				allwinner,function = "i2c0";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			i2c1_pins_a: i2c1@0 {
+				allwinner,pins = "PH2", "PH3";
+				allwinner,function = "i2c1";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+
+			i2c2_pins_a: i2c2@0 {
+				allwinner,pins = "PH4", "PH5";
+				allwinner,function = "i2c2";
+				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+			};
+		};
+
+		uart0: serial@01c28000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x01c28000 0x400>;
+			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&osc24M>;
+			status = "disabled";
+		};
+
+		gic: interrupt-controller@01c81000 {
+			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+			reg = <0x01c81000 0x1000>,
+			      <0x01c82000 0x1000>,
+			      <0x01c84000 0x2000>,
+			      <0x01c86000 0x2000>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+		};
+
+	};
+};
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 19+ messages in thread

* [PATCH 4/4] ARM: dts: sun8i: Add A83T HomletV2 Board by Allwinner
       [not found] ` <1442936337-3104-1-git-send-email-vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
                     ` (2 preceding siblings ...)
  2015-09-22 15:38   ` [PATCH 3/4] ARM: dts: sun8i: Add Allwinner A83T dtsi Vishnu Patekar
@ 2015-09-22 15:38   ` Vishnu Patekar
  2015-09-22 16:00     ` Maxime Ripard
  3 siblings, 1 reply; 19+ messages in thread
From: Vishnu Patekar @ 2015-09-22 15:38 UTC (permalink / raw)
  To: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, pawel.moll-5wv7dgnIgG8,
	mark.rutland-5wv7dgnIgG8, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
	galak-sgV2jX0FEOL9JmXXK+q4OQ,
	maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
	linux-lFZ/pmaqli7XmaaqVzeoHQ, emilio-0Z03zUJReD5OxF6Tv1QG9Q,
	linus.walleij-QSEj5FYQhm4dnm+yROfE0A
  Cc: jenskuske-Re5JQEeQqe8AvxtiuMwx3w, hdegoede-H+wXaHxf7aLQT0dZR+AlfA,
	wens-jdAy2FN1RRM, devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	linux-sunxi-/JYPxA39Uh5TLH3MbocFFw,
	linux-gpio-u79uwXL29TY76Z2rM5mHXA, Vishnu Patekar

H8Homlet Proto v2.0 Board is A83T Dev Board by Allwinner.
It has UART, ethernet, USB, HDMI, etc ports on it.

It's name is confusing, Its A83T board however,"H8_HOMLET_PROTO_V2"
printed on board.

A83T patches are tested on this board.
It has UART, ethernet, USB, HDMI, etc ports on it.

For FEL mode it needs USB A-A(Male) cable. I used uart0 which
is multiplexed to microsd pins PF2 and PF4.

Signed-off-by: Vishnu Patekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
 arch/arm/boot/dts/Makefile                         |  5 +-
 .../boot/dts/sun8i-a83t-allwinner-homlet-v20.dts   | 69 ++++++++++++++++++++++
 2 files changed, 72 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/boot/dts/sun8i-a83t-allwinner-homlet-v20.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b276174..9585a58 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -634,7 +634,8 @@ dtb-$(CONFIG_MACH_SUN8I) += \
 	sun8i-a33-ga10h-v1.1.dtb \
 	sun8i-a33-ippo-q8h-v1.2.dtb \
 	sun8i-a33-q8-tzx-723q4.dtb \
-	sun8i-a33-sinlinx-sina33.dtb
+	sun8i-a33-sinlinx-sina33.dtb \
+	sun8i-a83t-allwinner-homlet-v20.dtb
 dtb-$(CONFIG_MACH_SUN9I) += \
 	sun9i-a80-optimus.dtb \
 	sun9i-a80-cubieboard4.dtb
@@ -679,7 +680,7 @@ dtb-$(CONFIG_ARCH_UNIPHIER) += \
 	uniphier-ph1-ld6b-ref.dtb \
 	uniphier-ph1-pro4-ref.dtb \
 	uniphier-ph1-sld3-ref.dtb \
-	uniphier-ph1-sld8-ref.dtb 
+	uniphier-ph1-sld8-ref.dtb
 dtb-$(CONFIG_ARCH_VERSATILE) += \
 	versatile-ab.dtb \
 	versatile-pb.dtb
diff --git a/arch/arm/boot/dts/sun8i-a83t-allwinner-homlet-v20.dts b/arch/arm/boot/dts/sun8i-a83t-allwinner-homlet-v20.dts
new file mode 100644
index 0000000..bbc2ab9
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-a83t-allwinner-homlet-v20.dts
@@ -0,0 +1,69 @@
+/*
+ * Copyright 2015 Vishnu Patekar
+ * Vishnu Patekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-a83t.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+	model = "Allwinner A83T H8Homlet Proto Dev Board v2.0";
+	compatible = "allwinner,homletv2", "allwinner,sun8i-a83t";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+		bootargs = "earlyprintk console=ttyS0,115200";
+	};
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins_a>;
+	status = "okay";
+};
-- 
1.9.1

^ permalink raw reply related	[flat|nested] 19+ messages in thread

* Re: [PATCH 1/4] ARM: sunxi: Introduce Allwinner for A83T support
       [not found]     ` <1442936337-3104-2-git-send-email-vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
@ 2015-09-22 15:47       ` Chen-Yu Tsai
       [not found]         ` <CAGb2v665FhnSoWYGJn+Tf79F7pZitYBrEOmAts4nVoUWb-uBqg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
  2015-09-24 10:52         ` Vishnu Patekar
  2015-09-22 15:51       ` Maxime Ripard
  1 sibling, 2 replies; 19+ messages in thread
From: Chen-Yu Tsai @ 2015-09-22 15:47 UTC (permalink / raw)
  To: Vishnu Patekar
  Cc: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
	Maxime Ripard, Russell King - ARM Linux, Emilio Lopez,
	Linus Walleij, Jens Kuske, Hans De Goede, Chen-Yu Tsai,
	devicetree, linux-arm-kernel, linux-kernel, linux-sunxi,
	linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org

On Tue, Sep 22, 2015 at 11:38 PM, Vishnu Patekar
<vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> Allwinner A83T is octa-core cortex-a7 based SoC.
> It's clock control unit and prcm, pinmux are different from previous sun8i
> series.
> Its processor cores are arragned in two clusters 4 cores each,
> similar to A80.
>
> Signed-off-by: Vishnu Patekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
>  Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
>  arch/arm/mach-sunxi/sunxi.c                     | 1 +
>  drivers/clk/sunxi/clk-sunxi.c                   | 6 ++++++
>  3 files changed, 8 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt
> index 67da205..cf5ed27 100644
> --- a/Documentation/devicetree/bindings/arm/sunxi.txt
> +++ b/Documentation/devicetree/bindings/arm/sunxi.txt
> @@ -11,4 +11,5 @@ using one of the following compatible strings:
>    allwinner,sun8i-a23
>    allwinner,sun8i-a33
>    allwinner,sun8i-h3
> +  allwinner,sun8i-a83t

Alphabetic order please.

>    allwinner,sun9i-a80
> diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
> index 65bab28..b04aefa 100644
> --- a/arch/arm/mach-sunxi/sunxi.c
> +++ b/arch/arm/mach-sunxi/sunxi.c
> @@ -69,6 +69,7 @@ static const char * const sun8i_board_dt_compat[] = {
>         "allwinner,sun8i-a23",
>         "allwinner,sun8i-a33",
>         "allwinner,sun8i-h3",
> +       "allwinner,sun8i-a83t",

Same here.

>         NULL,
>  };
>
> diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
> index 413070d..f216d5d 100644
> --- a/drivers/clk/sunxi/clk-sunxi.c
> +++ b/drivers/clk/sunxi/clk-sunxi.c
> @@ -1212,6 +1212,12 @@ CLK_OF_DECLARE(sun6i_a31s_clk_init, "allwinner,sun6i-a31s", sun6i_init_clocks);
>  CLK_OF_DECLARE(sun8i_a23_clk_init, "allwinner,sun8i-a23", sun6i_init_clocks);
>  CLK_OF_DECLARE(sun8i_a33_clk_init, "allwinner,sun8i-a33", sun6i_init_clocks);
>
> +static void __init sun8ia83t_init_clocks(struct device_node *node)
> +{
> +       sunxi_init_clocks(NULL, 0);
> +}
> +CLK_OF_DECLARE(sun9i_a83t_clk_init, "allwinner,sun8i-a83t", sun8ia83t_init_clocks);

sun8i? Missing underscore too.

I think you should add this once you actually have clock support.
Otherwise this call basically does nothing.

> +
>  static void __init sun9i_init_clocks(struct device_node *node)
>  {
>         sunxi_init_clocks(NULL, 0);

On the side, I will send patches to remove sun9i_init_clocks.


Regards
ChenYu

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH 2/4] pinctrl: sunxi: add allwinner A83T PIO controller support
       [not found]     ` <1442936337-3104-3-git-send-email-vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
@ 2015-09-22 15:49       ` Maxime Ripard
  2015-09-22 16:06       ` Chen-Yu Tsai
  1 sibling, 0 replies; 19+ messages in thread
From: Maxime Ripard @ 2015-09-22 15:49 UTC (permalink / raw)
  To: Vishnu Patekar
  Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, pawel.moll-5wv7dgnIgG8,
	mark.rutland-5wv7dgnIgG8, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
	galak-sgV2jX0FEOL9JmXXK+q4OQ, linux-lFZ/pmaqli7XmaaqVzeoHQ,
	emilio-0Z03zUJReD5OxF6Tv1QG9Q,
	linus.walleij-QSEj5FYQhm4dnm+yROfE0A,
	jenskuske-Re5JQEeQqe8AvxtiuMwx3w, hdegoede-H+wXaHxf7aLQT0dZR+AlfA,
	wens-jdAy2FN1RRM, devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	linux-sunxi-/JYPxA39Uh5TLH3MbocFFw,
	linux-gpio-u79uwXL29TY76Z2rM5mHXA

[-- Attachment #1: Type: text/plain, Size: 539 bytes --]

On Tue, Sep 22, 2015 at 11:38:55PM +0800, Vishnu Patekar wrote:
> Allwinner A83T soc port controller has 8 ports.
> It has 3 IRQ banks namely PB, PG, PH.
> Pinmuxing are different for some pins as compared to
> sun8i A23 and A33.
> 
> Signed-off-by: Vishnu Patekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

Acked-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH 1/4] ARM: sunxi: Introduce Allwinner for A83T support
       [not found]     ` <1442936337-3104-2-git-send-email-vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
  2015-09-22 15:47       ` Chen-Yu Tsai
@ 2015-09-22 15:51       ` Maxime Ripard
  2015-09-24 10:55         ` Vishnu Patekar
  1 sibling, 1 reply; 19+ messages in thread
From: Maxime Ripard @ 2015-09-22 15:51 UTC (permalink / raw)
  To: Vishnu Patekar
  Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, pawel.moll-5wv7dgnIgG8,
	mark.rutland-5wv7dgnIgG8, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
	galak-sgV2jX0FEOL9JmXXK+q4OQ, linux-lFZ/pmaqli7XmaaqVzeoHQ,
	emilio-0Z03zUJReD5OxF6Tv1QG9Q,
	linus.walleij-QSEj5FYQhm4dnm+yROfE0A,
	jenskuske-Re5JQEeQqe8AvxtiuMwx3w, hdegoede-H+wXaHxf7aLQT0dZR+AlfA,
	wens-jdAy2FN1RRM, devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	linux-sunxi-/JYPxA39Uh5TLH3MbocFFw,
	linux-gpio-u79uwXL29TY76Z2rM5mHXA

[-- Attachment #1: Type: text/plain, Size: 2447 bytes --]

Hi,

On Tue, Sep 22, 2015 at 11:38:54PM +0800, Vishnu Patekar wrote:
> Allwinner A83T is octa-core cortex-a7 based SoC.
> It's clock control unit and prcm, pinmux are different from previous sun8i
> series.
> Its processor cores are arragned in two clusters 4 cores each,
> similar to A80.
> 
> Signed-off-by: Vishnu Patekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
>  Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
>  arch/arm/mach-sunxi/sunxi.c                     | 1 +
>  drivers/clk/sunxi/clk-sunxi.c                   | 6 ++++++
>  3 files changed, 8 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt
> index 67da205..cf5ed27 100644
> --- a/Documentation/devicetree/bindings/arm/sunxi.txt
> +++ b/Documentation/devicetree/bindings/arm/sunxi.txt
> @@ -11,4 +11,5 @@ using one of the following compatible strings:
>    allwinner,sun8i-a23
>    allwinner,sun8i-a33
>    allwinner,sun8i-h3
> +  allwinner,sun8i-a83t
>    allwinner,sun9i-a80
> diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
> index 65bab28..b04aefa 100644
> --- a/arch/arm/mach-sunxi/sunxi.c
> +++ b/arch/arm/mach-sunxi/sunxi.c
> @@ -69,6 +69,7 @@ static const char * const sun8i_board_dt_compat[] = {
>  	"allwinner,sun8i-a23",
>  	"allwinner,sun8i-a33",
>  	"allwinner,sun8i-h3",
> +	"allwinner,sun8i-a83t",
>  	NULL,
>  };
>  
> diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
> index 413070d..f216d5d 100644
> --- a/drivers/clk/sunxi/clk-sunxi.c
> +++ b/drivers/clk/sunxi/clk-sunxi.c
> @@ -1212,6 +1212,12 @@ CLK_OF_DECLARE(sun6i_a31s_clk_init, "allwinner,sun6i-a31s", sun6i_init_clocks);
>  CLK_OF_DECLARE(sun8i_a23_clk_init, "allwinner,sun8i-a23", sun6i_init_clocks);
>  CLK_OF_DECLARE(sun8i_a33_clk_init, "allwinner,sun8i-a33", sun6i_init_clocks);
>  
> +static void __init sun8ia83t_init_clocks(struct device_node *node)

Having an underscore between sun8i and a83t would be great :)

> +{
> +	sunxi_init_clocks(NULL, 0);
> +}
> +CLK_OF_DECLARE(sun9i_a83t_clk_init, "allwinner,sun8i-a83t", sun8ia83t_init_clocks);

                  ^ Is this a sun9i or sun8i SoC ?

Is the list of protected clocks always going to be empty, or will you
add some new clocks in that list in the future?

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH 1/4] ARM: sunxi: Introduce Allwinner for A83T support
       [not found]         ` <CAGb2v665FhnSoWYGJn+Tf79F7pZitYBrEOmAts4nVoUWb-uBqg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
@ 2015-09-22 15:53           ` Maxime Ripard
  2015-09-22 15:56             ` Chen-Yu Tsai
  0 siblings, 1 reply; 19+ messages in thread
From: Maxime Ripard @ 2015-09-22 15:53 UTC (permalink / raw)
  To: Chen-Yu Tsai
  Cc: Vishnu Patekar, Rob Herring, Pawel Moll, Mark Rutland,
	Ian Campbell, Kumar Gala, Russell King - ARM Linux, Emilio Lopez,
	Linus Walleij, Jens Kuske, Hans De Goede, devicetree,
	linux-arm-kernel, linux-kernel, linux-sunxi,
	linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org

[-- Attachment #1: Type: text/plain, Size: 2724 bytes --]

On Tue, Sep 22, 2015 at 11:47:40PM +0800, Chen-Yu Tsai wrote:
> On Tue, Sep 22, 2015 at 11:38 PM, Vishnu Patekar
> <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> > Allwinner A83T is octa-core cortex-a7 based SoC.
> > It's clock control unit and prcm, pinmux are different from previous sun8i
> > series.
> > Its processor cores are arragned in two clusters 4 cores each,
> > similar to A80.
> >
> > Signed-off-by: Vishnu Patekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> > ---
> >  Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
> >  arch/arm/mach-sunxi/sunxi.c                     | 1 +
> >  drivers/clk/sunxi/clk-sunxi.c                   | 6 ++++++
> >  3 files changed, 8 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt
> > index 67da205..cf5ed27 100644
> > --- a/Documentation/devicetree/bindings/arm/sunxi.txt
> > +++ b/Documentation/devicetree/bindings/arm/sunxi.txt
> > @@ -11,4 +11,5 @@ using one of the following compatible strings:
> >    allwinner,sun8i-a23
> >    allwinner,sun8i-a33
> >    allwinner,sun8i-h3
> > +  allwinner,sun8i-a83t
> 
> Alphabetic order please.
> 
> >    allwinner,sun9i-a80
> > diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
> > index 65bab28..b04aefa 100644
> > --- a/arch/arm/mach-sunxi/sunxi.c
> > +++ b/arch/arm/mach-sunxi/sunxi.c
> > @@ -69,6 +69,7 @@ static const char * const sun8i_board_dt_compat[] = {
> >         "allwinner,sun8i-a23",
> >         "allwinner,sun8i-a33",
> >         "allwinner,sun8i-h3",
> > +       "allwinner,sun8i-a83t",
> 
> Same here.
> 
> >         NULL,
> >  };
> >
> > diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
> > index 413070d..f216d5d 100644
> > --- a/drivers/clk/sunxi/clk-sunxi.c
> > +++ b/drivers/clk/sunxi/clk-sunxi.c
> > @@ -1212,6 +1212,12 @@ CLK_OF_DECLARE(sun6i_a31s_clk_init, "allwinner,sun6i-a31s", sun6i_init_clocks);
> >  CLK_OF_DECLARE(sun8i_a23_clk_init, "allwinner,sun8i-a23", sun6i_init_clocks);
> >  CLK_OF_DECLARE(sun8i_a33_clk_init, "allwinner,sun8i-a33", sun6i_init_clocks);
> >
> > +static void __init sun8ia83t_init_clocks(struct device_node *node)
> > +{
> > +       sunxi_init_clocks(NULL, 0);
> > +}
> > +CLK_OF_DECLARE(sun9i_a83t_clk_init, "allwinner,sun8i-a83t", sun8ia83t_init_clocks);
> 
> sun8i? Missing underscore too.
> 
> I think you should add this once you actually have clock support.
> Otherwise this call basically does nothing.

That's not true, it actually initializes most of the clocks in the
system.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH 3/4] ARM: dts: sun8i: Add Allwinner A83T dtsi
       [not found]     ` <1442936337-3104-4-git-send-email-vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
@ 2015-09-22 15:54       ` Maxime Ripard
  2015-09-22 16:15         ` Chen-Yu Tsai
  0 siblings, 1 reply; 19+ messages in thread
From: Maxime Ripard @ 2015-09-22 15:54 UTC (permalink / raw)
  To: Vishnu Patekar
  Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, pawel.moll-5wv7dgnIgG8,
	mark.rutland-5wv7dgnIgG8, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
	galak-sgV2jX0FEOL9JmXXK+q4OQ, linux-lFZ/pmaqli7XmaaqVzeoHQ,
	emilio-0Z03zUJReD5OxF6Tv1QG9Q,
	linus.walleij-QSEj5FYQhm4dnm+yROfE0A,
	jenskuske-Re5JQEeQqe8AvxtiuMwx3w, hdegoede-H+wXaHxf7aLQT0dZR+AlfA,
	wens-jdAy2FN1RRM, devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	linux-sunxi-/JYPxA39Uh5TLH3MbocFFw,
	linux-gpio-u79uwXL29TY76Z2rM5mHXA

[-- Attachment #1: Type: text/plain, Size: 8112 bytes --]

On Tue, Sep 22, 2015 at 11:38:56PM +0800, Vishnu Patekar wrote:
> Allwinner A83T is new octa-core cortex-a7 SOC.
> This adds the basic dtsi, the clocks differs from
> earlier sun8i SOCs.
> 
> Signed-off-by: Vishnu Patekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
>  arch/arm/boot/dts/sun8i-a83t.dtsi | 243 ++++++++++++++++++++++++++++++++++++++
>  1 file changed, 243 insertions(+)
>  create mode 100644 arch/arm/boot/dts/sun8i-a83t.dtsi
> 
> diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
> new file mode 100644
> index 0000000..f6ddd9c
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
> @@ -0,0 +1,243 @@
> +/*
> + * Copyright 2015 Vishnu Patekar
> + *
> + * Vishnu Patekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *  a) This file is free software; you can redistribute it and/or
> + *     modify it under the terms of the GNU General Public License as
> + *     published by the Free Software Foundation; either version 2 of the
> + *     License, or (at your option) any later version.
> + *
> + *     This file is distributed in the hope that it will be useful,
> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + *     GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + *  b) Permission is hereby granted, free of charge, to any person
> + *     obtaining a copy of this software and associated documentation
> + *     files (the "Software"), to deal in the Software without
> + *     restriction, including without limitation the rights to use,
> + *     copy, modify, merge, publish, distribute, sublicense, and/or
> + *     sell copies of the Software, and to permit persons to whom the
> + *     Software is furnished to do so, subject to the following
> + *     conditions:
> + *
> + *     The above copyright notice and this permission notice shall be
> + *     included in all copies or substantial portions of the Software.
> + *
> + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + *     OTHER DEALINGS IN THE SOFTWARE.
> +
> + */
> +
> +#include "skeleton.dtsi"
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +#include <dt-bindings/pinctrl/sun4i-a10.h>
> +
> +/ {
> +	interrupt-parent = <&gic>;
> +
> +	chosen {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges;
> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu@0 {
> +			compatible = "arm,cortex-a7";
> +			device_type = "cpu";
> +			reg = <0>;
> +		};
> +
> +		cpu@1 {
> +			compatible = "arm,cortex-a7";
> +			device_type = "cpu";
> +			reg = <1>;
> +		};
> +
> +		cpu@2 {
> +			compatible = "arm,cortex-a7";
> +			device_type = "cpu";
> +			reg = <2>;
> +		};
> +
> +		cpu@3 {
> +			compatible = "arm,cortex-a7";
> +			device_type = "cpu";
> +			reg = <3>;
> +		};
> +		cpu@4 {
> +			compatible = "arm,cortex-a7";
> +			device_type = "cpu";
> +			reg = <4>;
> +		};
> +
> +		cpu@5 {
> +			compatible = "arm,cortex-a7";
> +			device_type = "cpu";
> +			reg = <5>;
> +		};
> +		cpu@6 {
> +			compatible = "arm,cortex-a7";
> +			device_type = "cpu";
> +			reg = <6>;
> +		};
> +
> +		cpu@7 {
> +			compatible = "arm,cortex-a7";
> +			device_type = "cpu";
> +			reg = <7>;
> +		};
> +	};
> +
> +	memory {
> +		reg = <0x40000000 0x80000000>;
> +	};
> +
> +	timer {
> +		compatible = "arm,armv7-timer";
> +		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> +		clock-frequency = <24000000>;
> +		arm,cpu-registers-not-fw-configured;
> +	};
> +
> +	clocks {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges;
> +
> +		osc24M: osc24M_clk {
> +			#clock-cells = <0>;
> +			compatible = "fixed-clock";
> +			clock-frequency = <24000000>;
> +			clock-output-names = "osc24M";
> +		};
> +
> +		osc32k: osc32k_clk {
> +			#clock-cells = <0>;
> +			compatible = "fixed-clock";
> +			clock-frequency = <32768>;
> +			clock-output-names = "osc32k";
> +		};
> +	};
> +
> +	soc@01c00000 {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges;
> +
> +		pio: pinctrl@01c20800 {
> +			compatible = "allwinner,sun8i-a83t-pinctrl";
> +			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
> +			<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
> +			<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
> +			/* compatible gets set in SoC specific dtsi file */

Which DTSI?

> +			reg = <0x01c20800 0x400>;
> +			/* interrupts get set in SoC specific dtsi file */

Ditto

> +			clocks = <&osc24M>;
> +			gpio-controller;
> +			interrupt-controller;
> +			#interrupt-cells = <3>;
> +			#gpio-cells = <3>;
> +
> +			uart0_pins_a: uart0@0 {
> +				allwinner,pins = "PF2", "PF4";
> +				allwinner,function = "uart0";
> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> +			};
> +
> +			mmc0_pins_a: mmc0@0 {
> +				allwinner,pins = "PF0", "PF1", "PF2",
> +						 "PF3", "PF4", "PF5";
> +				allwinner,function = "mmc0";
> +				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> +			};
> +
> +			mmc1_pins_a: mmc1@0 {
> +				allwinner,pins = "PG0", "PG1", "PG2",
> +						 "PG3", "PG4", "PG5";
> +				allwinner,function = "mmc1";
> +				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> +			};
> +
> +			mmc2_8bit_pins: mmc2_8bit {
> +				allwinner,pins = "PC5", "PC6", "PC8",
> +						 "PC9", "PC10", "PC11",
> +						 "PC12", "PC13", "PC14",
> +						 "PC15";
> +				allwinner,function = "mmc2";
> +				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> +			};
> +
> +			i2c0_pins_a: i2c0@0 {
> +				allwinner,pins = "PH0", "PH1";
> +				allwinner,function = "i2c0";
> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> +			};
> +
> +			i2c1_pins_a: i2c1@0 {
> +				allwinner,pins = "PH2", "PH3";
> +				allwinner,function = "i2c1";
> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> +			};
> +
> +			i2c2_pins_a: i2c2@0 {
> +				allwinner,pins = "PH4", "PH5";
> +				allwinner,function = "i2c2";
> +				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> +				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> +			};

Please order those by alphabetical order.

> +		};
> +
> +		uart0: serial@01c28000 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x01c28000 0x400>;
> +			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
> +			reg-shift = <2>;
> +			reg-io-width = <4>;
> +			clocks = <&osc24M>;
> +			status = "disabled";
> +		};
> +
> +		gic: interrupt-controller@01c81000 {
> +			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
> +			reg = <0x01c81000 0x1000>,
> +			      <0x01c82000 0x1000>,
> +			      <0x01c84000 0x2000>,
> +			      <0x01c86000 0x2000>;
> +			interrupt-controller;
> +			#interrupt-cells = <3>;
> +			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> +		};
> +
> +	};
> +};
> -- 
> 1.9.1
> 

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH 1/4] ARM: sunxi: Introduce Allwinner for A83T support
  2015-09-22 15:53           ` Maxime Ripard
@ 2015-09-22 15:56             ` Chen-Yu Tsai
  0 siblings, 0 replies; 19+ messages in thread
From: Chen-Yu Tsai @ 2015-09-22 15:56 UTC (permalink / raw)
  To: Maxime Ripard
  Cc: Chen-Yu Tsai, Vishnu Patekar, Rob Herring, Pawel Moll,
	Mark Rutland, Ian Campbell, Kumar Gala, Russell King - ARM Linux,
	Emilio Lopez, Linus Walleij, Jens Kuske, Hans De Goede,
	devicetree, linux-arm-kernel, linux-kernel, linux-sunxi,
	linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org

On Tue, Sep 22, 2015 at 11:53 PM, Maxime Ripard
<maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> wrote:
> On Tue, Sep 22, 2015 at 11:47:40PM +0800, Chen-Yu Tsai wrote:
>> On Tue, Sep 22, 2015 at 11:38 PM, Vishnu Patekar
>> <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
>> > Allwinner A83T is octa-core cortex-a7 based SoC.
>> > It's clock control unit and prcm, pinmux are different from previous sun8i
>> > series.
>> > Its processor cores are arragned in two clusters 4 cores each,
>> > similar to A80.
>> >
>> > Signed-off-by: Vishnu Patekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>> > ---
>> >  Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
>> >  arch/arm/mach-sunxi/sunxi.c                     | 1 +
>> >  drivers/clk/sunxi/clk-sunxi.c                   | 6 ++++++
>> >  3 files changed, 8 insertions(+)
>> >
>> > diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt
>> > index 67da205..cf5ed27 100644
>> > --- a/Documentation/devicetree/bindings/arm/sunxi.txt
>> > +++ b/Documentation/devicetree/bindings/arm/sunxi.txt
>> > @@ -11,4 +11,5 @@ using one of the following compatible strings:
>> >    allwinner,sun8i-a23
>> >    allwinner,sun8i-a33
>> >    allwinner,sun8i-h3
>> > +  allwinner,sun8i-a83t
>>
>> Alphabetic order please.
>>
>> >    allwinner,sun9i-a80
>> > diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
>> > index 65bab28..b04aefa 100644
>> > --- a/arch/arm/mach-sunxi/sunxi.c
>> > +++ b/arch/arm/mach-sunxi/sunxi.c
>> > @@ -69,6 +69,7 @@ static const char * const sun8i_board_dt_compat[] = {
>> >         "allwinner,sun8i-a23",
>> >         "allwinner,sun8i-a33",
>> >         "allwinner,sun8i-h3",
>> > +       "allwinner,sun8i-a83t",
>>
>> Same here.
>>
>> >         NULL,
>> >  };
>> >
>> > diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
>> > index 413070d..f216d5d 100644
>> > --- a/drivers/clk/sunxi/clk-sunxi.c
>> > +++ b/drivers/clk/sunxi/clk-sunxi.c
>> > @@ -1212,6 +1212,12 @@ CLK_OF_DECLARE(sun6i_a31s_clk_init, "allwinner,sun6i-a31s", sun6i_init_clocks);
>> >  CLK_OF_DECLARE(sun8i_a23_clk_init, "allwinner,sun8i-a23", sun6i_init_clocks);
>> >  CLK_OF_DECLARE(sun8i_a33_clk_init, "allwinner,sun8i-a33", sun6i_init_clocks);
>> >
>> > +static void __init sun8ia83t_init_clocks(struct device_node *node)
>> > +{
>> > +       sunxi_init_clocks(NULL, 0);
>> > +}
>> > +CLK_OF_DECLARE(sun9i_a83t_clk_init, "allwinner,sun8i-a83t", sun8ia83t_init_clocks);
>>
>> sun8i? Missing underscore too.
>>
>> I think you should add this once you actually have clock support.
>> Otherwise this call basically does nothing.
>
> That's not true, it actually initializes most of the clocks in the
> system.

Right. Sorry, I think my thoughts strayed to sun9i.

ChenYu

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH 4/4] ARM: dts: sun8i: Add A83T HomletV2 Board by Allwinner
  2015-09-22 15:38   ` [PATCH 4/4] ARM: dts: sun8i: Add A83T HomletV2 Board by Allwinner Vishnu Patekar
@ 2015-09-22 16:00     ` Maxime Ripard
  2015-09-22 16:21       ` Vishnu Patekar
  0 siblings, 1 reply; 19+ messages in thread
From: Maxime Ripard @ 2015-09-22 16:00 UTC (permalink / raw)
  To: Vishnu Patekar
  Cc: robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak, linux,
	emilio, linus.walleij, jenskuske, hdegoede, wens, devicetree,
	linux-arm-kernel, linux-kernel, linux-sunxi, linux-gpio

[-- Attachment #1: Type: text/plain, Size: 5269 bytes --]

On Tue, Sep 22, 2015 at 11:38:57PM +0800, Vishnu Patekar wrote:
> H8Homlet Proto v2.0 Board is A83T Dev Board by Allwinner.
> It has UART, ethernet, USB, HDMI, etc ports on it.
> 
> It's name is confusing, Its A83T board however,"H8_HOMLET_PROTO_V2"
> printed on board.
> 
> A83T patches are tested on this board.
> It has UART, ethernet, USB, HDMI, etc ports on it.
> 
> For FEL mode it needs USB A-A(Male) cable. I used uart0 which
> is multiplexed to microsd pins PF2 and PF4.

Is there no other UART on the device?

> 
> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
> ---
>  arch/arm/boot/dts/Makefile                         |  5 +-
>  .../boot/dts/sun8i-a83t-allwinner-homlet-v20.dts   | 69 ++++++++++++++++++++++
>  2 files changed, 72 insertions(+), 2 deletions(-)
>  create mode 100644 arch/arm/boot/dts/sun8i-a83t-allwinner-homlet-v20.dts
> 
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index b276174..9585a58 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -634,7 +634,8 @@ dtb-$(CONFIG_MACH_SUN8I) += \
>  	sun8i-a33-ga10h-v1.1.dtb \
>  	sun8i-a33-ippo-q8h-v1.2.dtb \
>  	sun8i-a33-q8-tzx-723q4.dtb \
> -	sun8i-a33-sinlinx-sina33.dtb
> +	sun8i-a33-sinlinx-sina33.dtb \
> +	sun8i-a83t-allwinner-homlet-v20.dtb

we probably want to mention the h8 in here too, and the v2 is enough.

>  dtb-$(CONFIG_MACH_SUN9I) += \
>  	sun9i-a80-optimus.dtb \
>  	sun9i-a80-cubieboard4.dtb
> @@ -679,7 +680,7 @@ dtb-$(CONFIG_ARCH_UNIPHIER) += \
>  	uniphier-ph1-ld6b-ref.dtb \
>  	uniphier-ph1-pro4-ref.dtb \
>  	uniphier-ph1-sld3-ref.dtb \
> -	uniphier-ph1-sld8-ref.dtb 
> +	uniphier-ph1-sld8-ref.dtb

Uh ?

>  dtb-$(CONFIG_ARCH_VERSATILE) += \
>  	versatile-ab.dtb \
>  	versatile-pb.dtb
> diff --git a/arch/arm/boot/dts/sun8i-a83t-allwinner-homlet-v20.dts b/arch/arm/boot/dts/sun8i-a83t-allwinner-homlet-v20.dts
> new file mode 100644
> index 0000000..bbc2ab9
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun8i-a83t-allwinner-homlet-v20.dts
> @@ -0,0 +1,69 @@
> +/*
> + * Copyright 2015 Vishnu Patekar
> + * Vishnu Patekar <vishnupatekar0510@gmail.com>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *  a) This file is free software; you can redistribute it and/or
> + *     modify it under the terms of the GNU General Public License as
> + *     published by the Free Software Foundation; either version 2 of the
> + *     License, or (at your option) any later version.
> + *
> + *     This file is distributed in the hope that it will be useful,
> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + *     GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + *  b) Permission is hereby granted, free of charge, to any person
> + *     obtaining a copy of this software and associated documentation
> + *     files (the "Software"), to deal in the Software without
> + *     restriction, including without limitation the rights to use,
> + *     copy, modify, merge, publish, distribute, sublicense, and/or
> + *     sell copies of the Software, and to permit persons to whom the
> + *     Software is furnished to do so, subject to the following
> + *     conditions:
> + *
> + *     The above copyright notice and this permission notice shall be
> + *     included in all copies or substantial portions of the Software.
> + *
> + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + *     OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +/dts-v1/;
> +#include "sun8i-a83t.dtsi"
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/pinctrl/sun4i-a10.h>

Do you need those headers?

> +
> +/ {
> +	model = "Allwinner A83T H8Homlet Proto Dev Board v2.0";
> +	compatible = "allwinner,homletv2", "allwinner,sun8i-a83t";

                                ^ Please add a dash here

> +
> +	aliases {
> +		serial0 = &uart0;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +		bootargs = "earlyprintk console=ttyS0,115200";

console is useless here, and please remove earlyprintk. It will make
your kernel crash if the image is configured for another SoC.

> +	};
> +};
> +
> +&uart0 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&uart0_pins_a>;
> +	status = "okay";
> +};
> -- 
> 1.9.1
> 

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 819 bytes --]

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH 2/4] pinctrl: sunxi: add allwinner A83T PIO controller support
       [not found]     ` <1442936337-3104-3-git-send-email-vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
  2015-09-22 15:49       ` Maxime Ripard
@ 2015-09-22 16:06       ` Chen-Yu Tsai
  2015-09-24 10:15         ` Maxime Ripard
  1 sibling, 1 reply; 19+ messages in thread
From: Chen-Yu Tsai @ 2015-09-22 16:06 UTC (permalink / raw)
  To: Vishnu Patekar
  Cc: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
	Maxime Ripard, Russell King - ARM Linux, Emilio Lopez,
	Linus Walleij, Jens Kuske, Hans De Goede, Chen-Yu Tsai,
	devicetree, linux-arm-kernel, linux-kernel, linux-sunxi,
	linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org

On Tue, Sep 22, 2015 at 11:38 PM, Vishnu Patekar
<vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> Allwinner A83T soc port controller has 8 ports.
> It has 3 IRQ banks namely PB, PG, PH.
> Pinmuxing are different for some pins as compared to
> sun8i A23 and A33.
>
> Signed-off-by: Vishnu Patekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
>  .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt   |   1 +
>  drivers/pinctrl/sunxi/Kconfig                      |   4 +
>  drivers/pinctrl/sunxi/Makefile                     |   1 +
>  drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c         | 603 +++++++++++++++++++++
>  4 files changed, 609 insertions(+)
>  create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> index 3c821cd..b321b26 100644
> --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> @@ -17,6 +17,7 @@ Required properties:
>    "allwinner,sun8i-a23-pinctrl"
>    "allwinner,sun8i-a23-r-pinctrl"
>    "allwinner,sun8i-a33-pinctrl"
> +  "allwinner,sun8i-a83t-pinctrl"
>
>  - reg: Should contain the register physical address and length for the
>    pin controller.
> diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
> index ae27872..e68fd95 100644
> --- a/drivers/pinctrl/sunxi/Kconfig
> +++ b/drivers/pinctrl/sunxi/Kconfig
> @@ -42,6 +42,10 @@ config PINCTRL_SUN8I_A33
>         def_bool MACH_SUN8I
>         select PINCTRL_SUNXI_COMMON
>
> +config PINCTRL_SUN8I_A83T
> +       def_bool MACH_SUN8I
> +       select PINCTRL_SUNXI_COMMON
> +
>  config PINCTRL_SUN8I_A23_R
>         def_bool MACH_SUN8I
>         depends on RESET_CONTROLLER
> diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
> index 227a121..e080290 100644
> --- a/drivers/pinctrl/sunxi/Makefile
> +++ b/drivers/pinctrl/sunxi/Makefile
> @@ -12,4 +12,5 @@ obj-$(CONFIG_PINCTRL_SUN7I_A20)               += pinctrl-sun7i-a20.o
>  obj-$(CONFIG_PINCTRL_SUN8I_A23)                += pinctrl-sun8i-a23.o
>  obj-$(CONFIG_PINCTRL_SUN8I_A23_R)      += pinctrl-sun8i-a23-r.o
>  obj-$(CONFIG_PINCTRL_SUN8I_A33)                += pinctrl-sun8i-a33.o
> +obj-$(CONFIG_PINCTRL_SUN8I_A83T)       += pinctrl-sun8i-a83t.o
>  obj-$(CONFIG_PINCTRL_SUN9I_A80)                += pinctrl-sun9i-a80.o
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c
> new file mode 100644
> index 0000000..90b973e
> --- /dev/null
> +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t.c
> @@ -0,0 +1,603 @@
> +/*
> + * Allwinner a83t SoCs pinctrl driver.

                A83T (uppercase)?

> + *
> + * Copyright (C) 2015 Vishnu Patekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> + *
> + * Based on pinctrl-sun8i-a23.c, which is:
> + * Copyright (C) 2014 Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
> + * Copyright (C) 2014 Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/pinctrl/pinctrl.h>
> +
> +#include "pinctrl-sunxi.h"
> +
> +static const struct sunxi_desc_pin sun8i_a83t_pins[] = {
> +       /* Hole */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "uart2"),         /* TX */
> +                 SUNXI_FUNCTION(0x3, "jtag"),          /* MS0 */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),  /* PB_EINT0 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "uart2"),         /* RX */
> +                 SUNXI_FUNCTION(0x3, "jtag"),          /* CK0 */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),  /* PB_EINT1 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "uart2"),         /* RTS */
> +                 SUNXI_FUNCTION(0x3, "jtag"),          /* DO0 */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),  /* PB_EINT2 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "uart2"),         /* CTS */
> +                 SUNXI_FUNCTION(0x3, "jtag"),          /* DI0 */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),  /* PB_EINT3 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "i2s0"),          /* LRCK */
> +                 SUNXI_FUNCTION(0x3, "tdm"),           /* LRCK */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),  /* PB_EINT4 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "i2s0"),          /* BCLK */
> +                 SUNXI_FUNCTION(0x3, "tdm"),           /* BCLK */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),  /* PB_EINT5 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "i2s0"),          /* DOUT */
> +                 SUNXI_FUNCTION(0x3, "tdm"),           /* DOUT */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),  /* PB_EINT6 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "i2s0"),          /* DIN */
> +                 SUNXI_FUNCTION(0x3, "tdm"),           /* DIN */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),  /* PB_EINT7 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "i2s0"),          /* MCLK */
> +                 SUNXI_FUNCTION(0x3, "tdm"),           /* MCLK */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),  /* PB_EINT8 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "uart0"),         /* TX */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),  /* PB_EINT9 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "uart0"),         /* RX */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PB_EINT10 */
> +       /* Hole */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "nand0"),         /* WE */
> +                 SUNXI_FUNCTION(0x3, "spi0")),         /* MOSI */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "nand0"),         /* ALE */
> +                 SUNXI_FUNCTION(0x3, "spi0")),         /* MISO */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "nand0"),         /* CLE */
> +                 SUNXI_FUNCTION(0x3, "spi0")),         /* CLK */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "nand0"),         /* CE1 */
> +                 SUNXI_FUNCTION(0x3, "spi0")),         /* CS */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "nand0")),        /* CE0 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "nand0"),         /* RE */
> +                 SUNXI_FUNCTION(0x3, "mmc2")),         /* CLK */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "nand0"),         /* RB0 */
> +                 SUNXI_FUNCTION(0x3, "mmc2")),         /* CMD */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "nand0")),        /* RB1 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "nand0"),         /* DQ0 */
> +                 SUNXI_FUNCTION(0x3, "mmc2")),         /* D0 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "nand0"),         /* DQ1 */
> +                 SUNXI_FUNCTION(0x3, "mmc2")),         /* D1 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "nand0"),         /* DQ2 */
> +                 SUNXI_FUNCTION(0x3, "mmc2")),         /* D2 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "nand0"),         /* DQ3 */
> +                 SUNXI_FUNCTION(0x3, "mmc2")),         /* D3 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "nand0"),         /* DQ4 */
> +                 SUNXI_FUNCTION(0x3, "mmc2")),         /* D4 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "nand0"),         /* DQ5 */
> +                 SUNXI_FUNCTION(0x3, "mmc2")),         /* D5 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "nand"),          /* DQ6 */
> +                 SUNXI_FUNCTION(0x3, "mmc2")),         /* D6 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "nand"),          /* DQ7 */
> +                 SUNXI_FUNCTION(0x3, "mmc2")),         /* D7 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "nand"),          /* DQS */
> +                 SUNXI_FUNCTION(0x3, "mmc2")),         /* RST */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "nand")),         /* CE2 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "nand")),         /* CE3 */
> +       /* Hole */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "lcd0"),          /* D2 */
> +                 SUNXI_FUNCTION(0x4, "gmac")),         /* RGMII / MII RXD3 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "lcd0"),          /* D3 */
> +                 SUNXI_FUNCTION(0x4, "gmac")),         /* RGMII / MII RXD2 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "lcd0"),          /* D4 */
> +                 SUNXI_FUNCTION(0x4, "gmac")),         /* RGMII / MII RXD1 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "lcd0"),          /* D5 */
> +                 SUNXI_FUNCTION(0x4, "gmac")),         /* RGMII / MII RXD0 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "lcd0"),          /* D6 */
> +                 SUNXI_FUNCTION(0x4, "gmac")),         /* RGMII / MII RXCK */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "lcd0"),          /* D7 */
> +                 SUNXI_FUNCTION(0x4, "gmac")),         /* RGMII / MII RXDV */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "lcd0"),          /* D10 */
> +                 SUNXI_FUNCTION(0x4, "gmac")),         /* RGMII / MII RXERR */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "lcd0"),          /* D11 */
> +                 SUNXI_FUNCTION(0x4, "gmac")),         /* RGMII / MII TXD3 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "lcd0"),          /* D12 */
> +                 SUNXI_FUNCTION(0x4, "gmac")),         /* RGMII / MII TXD2 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "lcd0"),          /* D13 */
> +                 SUNXI_FUNCTION(0x4, "gmac")),         /* RGMII / MII TXD1 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "lcd0"),          /* D14 */
> +                 SUNXI_FUNCTION(0x4, "gmac")),         /* RGMII / MII TXD0 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "lcd0"),          /* D15 */
> +                 SUNXI_FUNCTION(0x4, "gmac")), /* RGMII-NULL / MII-CRS */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "lcd0"),          /* D18 */
> +                 SUNXI_FUNCTION(0x3, "lvds0"),         /* VP0 */
> +                 SUNXI_FUNCTION(0x4, "gmac")),         /* GTXCK / ETXCK */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "lcd0"),          /* D19 */
> +                 SUNXI_FUNCTION(0x3, "lvds0"),         /* VN0 */
> +                 SUNXI_FUNCTION(0x4, "gmac")),         /* GTXCTL / ETXEL */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "lcd0"),          /* D20 */
> +                 SUNXI_FUNCTION(0x3, "lvds0"),         /* VP1 */
> +                 SUNXI_FUNCTION(0x4, "gmac")),         /* GNULL / ETXERR */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "lcd0"),          /* D21 */
> +                 SUNXI_FUNCTION(0x3, "lvds0"),         /* VN1 */
> +                 SUNXI_FUNCTION(0x4, "gmac")),         /* GCLKIN / ECOL */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "lcd0"),          /* D22 */
> +                 SUNXI_FUNCTION(0x3, "lvds0"),         /* VP2 */
> +                 SUNXI_FUNCTION(0x4, "gmac")),         /* GMDC */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "lcd0"),          /* D23 */
> +                 SUNXI_FUNCTION(0x3, "lvds0"),         /* VN2 */
> +                 SUNXI_FUNCTION(0x4, "gmac")),         /* GMDIO */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "lcd0"),          /* CLK */
> +                 SUNXI_FUNCTION(0x3, "lvds0")),        /* VPC */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "lcd0"),          /* DE */
> +                 SUNXI_FUNCTION(0x3, "lvds0")),        /* VNC */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "lcd0"),          /* HSYNC */
> +                 SUNXI_FUNCTION(0x3, "lvds0")),        /* VP3 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "lcd0"),          /* VSYNC */
> +                 SUNXI_FUNCTION(0x3, "lvds0")),        /* VN3 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 28),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "pwm")),          /* PWM */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 29),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out")),
> +       /* Hole */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "csi"),           /* PCLK */
> +                 SUNXI_FUNCTION(0x4, "ccir")),         /* CLK */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "csi"),           /* MCLK */
> +                 SUNXI_FUNCTION(0x4, "ccir")),         /* DE */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "csi"),           /* HSYNC */
> +                 SUNXI_FUNCTION(0x4, "ccir")),         /* HSYNC */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "csi"),           /* VSYNC */
> +                 SUNXI_FUNCTION(0x4, "ccir")),         /* VSYNC */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "csi")),          /* D0 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "csi")),          /* D1 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "csi"),           /* D2 */
> +                 SUNXI_FUNCTION(0x4, "ccir")),         /* D0 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "csi"),           /* D3 */
> +                 SUNXI_FUNCTION(0x4, "ccir")),         /* D1 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "csi"),           /* D4 */
> +                 SUNXI_FUNCTION(0x4, "ccir")),         /* D2 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "csi"),           /* D5 */
> +                 SUNXI_FUNCTION(0x4, "ccir")),         /* D3 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "csi"),           /* D6 */
> +                 SUNXI_FUNCTION(0x3, "uart4"),         /* TX */
> +                 SUNXI_FUNCTION(0x4, "ccir")),         /* D4 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "csi"),           /* D7 */
> +                 SUNXI_FUNCTION(0x3, "uart4"),         /* RX */
> +                 SUNXI_FUNCTION(0x4, "ccir")),         /* D5 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "csi"),           /* D8 */
> +                 SUNXI_FUNCTION(0x3, "uart4"),         /* RTS */
> +                 SUNXI_FUNCTION(0x4, "ccir")),         /* D6 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "csi"),           /* D9 */
> +                 SUNXI_FUNCTION(0x3, "uart4"),         /* CTS */
> +                 SUNXI_FUNCTION(0x4, "ccir")),         /* D7 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "csi"),           /* SCK */
> +                 SUNXI_FUNCTION(0x3, "i2c2")),         /* SCK */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "csi"),           /* SDA */
> +                 SUNXI_FUNCTION(0x3, "i2c2")),         /* SDA */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out")),
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out")),
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 18),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x3, "owa")),          /* DOUT */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 19),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out")),
> +       /* Hole */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "mmc0"),          /* D1 */
> +                 SUNXI_FUNCTION(0x3, "jtag")),         /* MS1 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "mmc0"),          /* D0 */
> +                 SUNXI_FUNCTION(0x3, "jtag")),         /* DI1 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "mmc0"),          /* CLK */
> +                 SUNXI_FUNCTION(0x3, "uart0")),        /* TX */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "mmc0"),          /* CMD */
> +                 SUNXI_FUNCTION(0x3, "jtag")),         /* DO1 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "mmc0"),          /* D3 */
> +                 SUNXI_FUNCTION(0x3, "uart0")),        /* RX */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "mmc0"),          /* D2 */
> +                 SUNXI_FUNCTION(0x3, "jtag")),         /* CK1 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out")),
> +       /* Hole */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "mmc1"),          /* CLK */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)),  /* PG_EINT0 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "mmc1"),          /* CMD */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)),  /* PG_EINT1 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "mmc1"),          /* D0 */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)),  /* PG_EINT2 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "mmc1"),          /* D1 */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)),  /* PG_EINT3 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "mmc1"),          /* D2 */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)),  /* PG_EINT4 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "mmc1"),          /* D3 */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)),  /* PG_EINT5 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "uart1"),         /* TX */
> +                 SUNXI_FUNCTION(0x3, "spi1"),          /* CS */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)),  /* PG_EINT6 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "uart1"),         /* RX */
> +                 SUNXI_FUNCTION(0x3, "spi1"),          /* CLK */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)),  /* PG_EINT7 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "uart1"),         /* RTS */
> +                 SUNXI_FUNCTION(0x3, "spi1"),          /* MOSI */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)),  /* PG_EINT8 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "uart1"),         /* CTS */
> +                 SUNXI_FUNCTION(0x3, "spi1"),          /* MISO */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)),  /* PG_EINT9 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "i2s1"),          /* BCLK */
> +                 SUNXI_FUNCTION(0x3, "uart3"),         /* TX */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)), /* PG_EINT10 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "i2s1"),          /* LRCK */
> +                 SUNXI_FUNCTION(0x3, "uart3"),         /* RX */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)), /* PG_EINT11 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "i2s1"),          /* DOUT */
> +                 SUNXI_FUNCTION(0x3, "uart3"),         /* RTS */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)), /* PG_EINT12 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "i2s1"),          /* DIN */
> +                 SUNXI_FUNCTION(0x3, "uart3"),         /* CTS */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)), /* PG_EINT13 */
> +       /* Hole */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "i2c0"),          /* SCK */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)),  /* PH_EINT0 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "i2c0"),          /* SDA */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)),  /* PH_EINT1 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "i2c1"),          /* SCK */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)),  /* PH_EINT2 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "i2c1"),          /* SDA */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)),  /* PH_EINT3 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "i2c2"),          /* SCK */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)),  /* PH_EINT4 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "i2c2"),          /* SDA */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)),  /* PH_EINT5 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "hdmi"),          /* HSCL */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)),  /* PH_EINT6 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "hdmi"),          /* HSDA */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)),  /* PH_EINT7 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION(0x2, "hdmi"),          /* HCEC */
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)),  /* PH_EINT8 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)),  /* PH_EINT9 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PH_EINT10 */
> +       SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
> +                 SUNXI_FUNCTION(0x0, "gpio_in"),
> +                 SUNXI_FUNCTION(0x1, "gpio_out"),
> +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)),  /* PH_EINT11 */
> +};
> +
> +static const struct sunxi_pinctrl_desc sun8i_a83t_pinctrl_data = {
> +       .pins = sun8i_a83t_pins,
> +       .npins = ARRAY_SIZE(sun8i_a83t_pins),
> +       .irq_banks = 3,

Do you know if there's a hole at where PA_EINT interrupt registers
should be? AFAIK we aren't handling that properly, but that is outside
the scope of this patch.

> +};
> +
> +static int sun8i_a83t_pinctrl_probe(struct platform_device *pdev)
> +{
> +       return sunxi_pinctrl_init(pdev,
> +                                 &sun8i_a83t_pinctrl_data);

Small nit. I know this is in all the other drivers,
but is the line break really necesary?

> +}
> +
> +static const struct of_device_id sun8i_a83t_pinctrl_match[] = {
> +       { .compatible = "allwinner,sun8i-a83t-pinctrl", },
> +       {}
> +};
> +MODULE_DEVICE_TABLE(of, sun8i_a83t_pinctrl_match);
> +
> +static struct platform_driver sun8i_a83t_pinctrl_driver = {
> +       .probe  = sun8i_a83t_pinctrl_probe,
> +       .driver = {
> +               .name           = "sun8i-a83t-pinctrl",
> +               .of_match_table = sun8i_a83t_pinctrl_match,
> +       },
> +};
> +module_platform_driver(sun8i_a83t_pinctrl_driver);
> +
> +MODULE_AUTHOR("Vishnu Patekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>");
> +MODULE_DESCRIPTION("Allwinner a83t pinctrl driver");

                                 A83T (uppercase)?

Thanks!

Regards
ChenYu

> +MODULE_LICENSE("GPL");
> --
> 1.9.1
>

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH 3/4] ARM: dts: sun8i: Add Allwinner A83T dtsi
  2015-09-22 15:54       ` Maxime Ripard
@ 2015-09-22 16:15         ` Chen-Yu Tsai
  0 siblings, 0 replies; 19+ messages in thread
From: Chen-Yu Tsai @ 2015-09-22 16:15 UTC (permalink / raw)
  To: Vishnu Patekar
  Cc: Maxime Ripard, Rob Herring, Pawel Moll, Mark Rutland,
	Ian Campbell, Kumar Gala, Russell King - ARM Linux, Emilio Lopez,
	Linus Walleij, Jens Kuske, Hans De Goede, Chen-Yu Tsai,
	devicetree, linux-arm-kernel, linux-kernel, linux-sunxi,
	linux-gpio@vger.kernel.org

On Tue, Sep 22, 2015 at 11:54 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> On Tue, Sep 22, 2015 at 11:38:56PM +0800, Vishnu Patekar wrote:
>> Allwinner A83T is new octa-core cortex-a7 SOC.
>> This adds the basic dtsi, the clocks differs from
>> earlier sun8i SOCs.
>>
>> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
>> ---
>>  arch/arm/boot/dts/sun8i-a83t.dtsi | 243 ++++++++++++++++++++++++++++++++++++++
>>  1 file changed, 243 insertions(+)
>>  create mode 100644 arch/arm/boot/dts/sun8i-a83t.dtsi
>>
>> diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
>> new file mode 100644
>> index 0000000..f6ddd9c
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
>> @@ -0,0 +1,243 @@
>> +/*
>> + * Copyright 2015 Vishnu Patekar
>> + *
>> + * Vishnu Patekar <vishnupatekar0510@gmail.com>
>> + *
>> + * This file is dual-licensed: you can use it either under the terms
>> + * of the GPL or the X11 license, at your option. Note that this dual
>> + * licensing only applies to this file, and not this project as a
>> + * whole.
>> + *
>> + *  a) This file is free software; you can redistribute it and/or
>> + *     modify it under the terms of the GNU General Public License as
>> + *     published by the Free Software Foundation; either version 2 of the
>> + *     License, or (at your option) any later version.
>> + *
>> + *     This file is distributed in the hope that it will be useful,
>> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + *     GNU General Public License for more details.
>> + *
>> + * Or, alternatively,
>> + *
>> + *  b) Permission is hereby granted, free of charge, to any person
>> + *     obtaining a copy of this software and associated documentation
>> + *     files (the "Software"), to deal in the Software without
>> + *     restriction, including without limitation the rights to use,
>> + *     copy, modify, merge, publish, distribute, sublicense, and/or
>> + *     sell copies of the Software, and to permit persons to whom the
>> + *     Software is furnished to do so, subject to the following
>> + *     conditions:
>> + *
>> + *     The above copyright notice and this permission notice shall be
>> + *     included in all copies or substantial portions of the Software.
>> + *
>> + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + *     OTHER DEALINGS IN THE SOFTWARE.
>> +
>> + */
>> +
>> +#include "skeleton.dtsi"
>> +
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +
>> +#include <dt-bindings/pinctrl/sun4i-a10.h>
>> +
>> +/ {
>> +     interrupt-parent = <&gic>;
>> +
>> +     chosen {
>> +             #address-cells = <1>;
>> +             #size-cells = <1>;
>> +             ranges;
>> +     };
>> +
>> +     cpus {
>> +             #address-cells = <1>;
>> +             #size-cells = <0>;
>> +
>> +             cpu@0 {
>> +                     compatible = "arm,cortex-a7";
>> +                     device_type = "cpu";
>> +                     reg = <0>;
>> +             };
>> +
>> +             cpu@1 {
>> +                     compatible = "arm,cortex-a7";
>> +                     device_type = "cpu";
>> +                     reg = <1>;
>> +             };
>> +
>> +             cpu@2 {
>> +                     compatible = "arm,cortex-a7";
>> +                     device_type = "cpu";
>> +                     reg = <2>;
>> +             };
>> +
>> +             cpu@3 {
>> +                     compatible = "arm,cortex-a7";
>> +                     device_type = "cpu";
>> +                     reg = <3>;
>> +             };
>> +             cpu@4 {
>> +                     compatible = "arm,cortex-a7";
>> +                     device_type = "cpu";
>> +                     reg = <4>;

These don't look right. See Documentation/devicetree/bindings/arm/cpus.txt
Cluster 1 would be 0x100 ~ 0x103.

>> +             };
>> +
>> +             cpu@5 {
>> +                     compatible = "arm,cortex-a7";
>> +                     device_type = "cpu";
>> +                     reg = <5>;
>> +             };
>> +             cpu@6 {
>> +                     compatible = "arm,cortex-a7";
>> +                     device_type = "cpu";
>> +                     reg = <6>;
>> +             };
>> +
>> +             cpu@7 {
>> +                     compatible = "arm,cortex-a7";
>> +                     device_type = "cpu";
>> +                     reg = <7>;
>> +             };
>> +     };
>> +
>> +     memory {
>> +             reg = <0x40000000 0x80000000>;
>> +     };
>> +
>> +     timer {
>> +             compatible = "arm,armv7-timer";
>> +             interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> +                          <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> +                          <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> +                          <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
>> +             clock-frequency = <24000000>;
>> +             arm,cpu-registers-not-fw-configured;
>> +     };
>> +
>> +     clocks {
>> +             #address-cells = <1>;
>> +             #size-cells = <1>;
>> +             ranges;
>> +
>> +             osc24M: osc24M_clk {
>> +                     #clock-cells = <0>;
>> +                     compatible = "fixed-clock";
>> +                     clock-frequency = <24000000>;
>> +                     clock-output-names = "osc24M";
>> +             };
>> +
>> +             osc32k: osc32k_clk {
>> +                     #clock-cells = <0>;
>> +                     compatible = "fixed-clock";
>> +                     clock-frequency = <32768>;
>> +                     clock-output-names = "osc32k";
>> +             };
>> +     };
>> +
>> +     soc@01c00000 {
>> +             compatible = "simple-bus";
>> +             #address-cells = <1>;
>> +             #size-cells = <1>;
>> +             ranges;
>> +
>> +             pio: pinctrl@01c20800 {
>> +                     compatible = "allwinner,sun8i-a83t-pinctrl";
>> +                     interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
>> +                     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
>> +                     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
>> +                     /* compatible gets set in SoC specific dtsi file */
>
> Which DTSI?
>
>> +                     reg = <0x01c20800 0x400>;
>> +                     /* interrupts get set in SoC specific dtsi file */
>
> Ditto
>
>> +                     clocks = <&osc24M>;
>> +                     gpio-controller;
>> +                     interrupt-controller;
>> +                     #interrupt-cells = <3>;
>> +                     #gpio-cells = <3>;
>> +
>> +                     uart0_pins_a: uart0@0 {
>> +                             allwinner,pins = "PF2", "PF4";
>> +                             allwinner,function = "uart0";
>> +                             allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> +                             allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> +                     };

Could you use PB9 & PB10 for uart0 pins, and not the PF ones?

http://linux-sunxi.org/User:Simos/H8HomletProtoV20_A83T shows
they are available on the headers, and I tested them before.

Thanks!
ChenYu

>> +
>> +                     mmc0_pins_a: mmc0@0 {
>> +                             allwinner,pins = "PF0", "PF1", "PF2",
>> +                                              "PF3", "PF4", "PF5";
>> +                             allwinner,function = "mmc0";
>> +                             allwinner,drive = <SUN4I_PINCTRL_30_MA>;
>> +                             allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> +                     };
>> +
>> +                     mmc1_pins_a: mmc1@0 {
>> +                             allwinner,pins = "PG0", "PG1", "PG2",
>> +                                              "PG3", "PG4", "PG5";
>> +                             allwinner,function = "mmc1";
>> +                             allwinner,drive = <SUN4I_PINCTRL_30_MA>;
>> +                             allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> +                     };
>> +
>> +                     mmc2_8bit_pins: mmc2_8bit {
>> +                             allwinner,pins = "PC5", "PC6", "PC8",
>> +                                              "PC9", "PC10", "PC11",
>> +                                              "PC12", "PC13", "PC14",
>> +                                              "PC15";

Would we also want PC16 (SDC2_RST)?

>> +                             allwinner,function = "mmc2";
>> +                             allwinner,drive = <SUN4I_PINCTRL_30_MA>;
>> +                             allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> +                     };
>> +
>> +                     i2c0_pins_a: i2c0@0 {
>> +                             allwinner,pins = "PH0", "PH1";
>> +                             allwinner,function = "i2c0";
>> +                             allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> +                             allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> +                     };
>> +
>> +                     i2c1_pins_a: i2c1@0 {
>> +                             allwinner,pins = "PH2", "PH3";
>> +                             allwinner,function = "i2c1";
>> +                             allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> +                             allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> +                     };
>> +
>> +                     i2c2_pins_a: i2c2@0 {
>> +                             allwinner,pins = "PH4", "PH5";
>> +                             allwinner,function = "i2c2";
>> +                             allwinner,drive = <SUN4I_PINCTRL_10_MA>;
>> +                             allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
>> +                     };
>
> Please order those by alphabetical order.
>
>> +             };
>> +
>> +             uart0: serial@01c28000 {
>> +                     compatible = "snps,dw-apb-uart";
>> +                     reg = <0x01c28000 0x400>;
>> +                     interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
>> +                     reg-shift = <2>;
>> +                     reg-io-width = <4>;
>> +                     clocks = <&osc24M>;
>> +                     status = "disabled";
>> +             };
>> +
>> +             gic: interrupt-controller@01c81000 {
>> +                     compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
>> +                     reg = <0x01c81000 0x1000>,
>> +                           <0x01c82000 0x1000>,
>> +                           <0x01c84000 0x2000>,
>> +                           <0x01c86000 0x2000>;
>> +                     interrupt-controller;
>> +                     #interrupt-cells = <3>;
>> +                     interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>> +             };
>> +
>> +     };
>> +};
>> --
>> 1.9.1
>>
>
> Thanks!
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux, Kernel and Android engineering
> http://free-electrons.com

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH 4/4] ARM: dts: sun8i: Add A83T HomletV2 Board by Allwinner
  2015-09-22 16:00     ` Maxime Ripard
@ 2015-09-22 16:21       ` Vishnu Patekar
  0 siblings, 0 replies; 19+ messages in thread
From: Vishnu Patekar @ 2015-09-22 16:21 UTC (permalink / raw)
  To: Maxime Ripard
  Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
	pawel.moll-5wv7dgnIgG8@public.gmane.org,
	mark.rutland-5wv7dgnIgG8@public.gmane.org,
	ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org,
	Kumar Gala, linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org,
	emilio-0Z03zUJReD5OxF6Tv1QG9Q, Linus Walleij, Jens Kuske,
	Hans de Goede, Chen-Yu Tsai,
	devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org,
	linux-gpio-u79uwXL29TY76Z2rM5mHXA

Hello,


On Wed, Sep 23, 2015 at 12:00 AM, Maxime Ripard
<maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> wrote:
>
> On Tue, Sep 22, 2015 at 11:38:57PM +0800, Vishnu Patekar wrote:
> > H8Homlet Proto v2.0 Board is A83T Dev Board by Allwinner.
> > It has UART, ethernet, USB, HDMI, etc ports on it.
> >
> > It's name is confusing, Its A83T board however,"H8_HOMLET_PROTO_V2"
> > printed on board.
> >
> > A83T patches are tested on this board.
> > It has UART, ethernet, USB, HDMI, etc ports on it.
> >
> > For FEL mode it needs USB A-A(Male) cable. I used uart0 which
> > is multiplexed to microsd pins PF2 and PF4.
>
> Is there no other UART on the device?
There is other UART port. I've not yet verify it.
Well, to put this device into FEL mode we need to press '2' on UART0.
So, I had to use uart0 multiplexed with uart0.

I doubt whether we can use other uart connector to put device into FEL mode.
>
> >
> > Signed-off-by: Vishnu Patekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> > ---
> >  arch/arm/boot/dts/Makefile                         |  5 +-
> >  .../boot/dts/sun8i-a83t-allwinner-homlet-v20.dts   | 69 ++++++++++++++++++++++
> >  2 files changed, 72 insertions(+), 2 deletions(-)
> >  create mode 100644 arch/arm/boot/dts/sun8i-a83t-allwinner-homlet-v20.dts
> >
> > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> > index b276174..9585a58 100644
> > --- a/arch/arm/boot/dts/Makefile
> > +++ b/arch/arm/boot/dts/Makefile
> > @@ -634,7 +634,8 @@ dtb-$(CONFIG_MACH_SUN8I) += \
> >       sun8i-a33-ga10h-v1.1.dtb \
> >       sun8i-a33-ippo-q8h-v1.2.dtb \
> >       sun8i-a33-q8-tzx-723q4.dtb \
> > -     sun8i-a33-sinlinx-sina33.dtb
> > +     sun8i-a33-sinlinx-sina33.dtb \
> > +     sun8i-a83t-allwinner-homlet-v20.dtb
>
> we probably want to mention the h8 in here too, and the v2 is enough.
>
> >  dtb-$(CONFIG_MACH_SUN9I) += \
> >       sun9i-a80-optimus.dtb \
> >       sun9i-a80-cubieboard4.dtb
> > @@ -679,7 +680,7 @@ dtb-$(CONFIG_ARCH_UNIPHIER) += \
> >       uniphier-ph1-ld6b-ref.dtb \
> >       uniphier-ph1-pro4-ref.dtb \
> >       uniphier-ph1-sld3-ref.dtb \
> > -     uniphier-ph1-sld8-ref.dtb
> > +     uniphier-ph1-sld8-ref.dtb
>
> Uh ?
I just fixed a white space error here, sorry, forgot to mention in commit log.
>
> >  dtb-$(CONFIG_ARCH_VERSATILE) += \
> >       versatile-ab.dtb \
> >       versatile-pb.dtb
> > diff --git a/arch/arm/boot/dts/sun8i-a83t-allwinner-homlet-v20.dts b/arch/arm/boot/dts/sun8i-a83t-allwinner-homlet-v20.dts
> > new file mode 100644
> > index 0000000..bbc2ab9
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/sun8i-a83t-allwinner-homlet-v20.dts
> > @@ -0,0 +1,69 @@
> > +/*
> > + * Copyright 2015 Vishnu Patekar
> > + * Vishnu Patekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> > + *
> > + * This file is dual-licensed: you can use it either under the terms
> > + * of the GPL or the X11 license, at your option. Note that this dual
> > + * licensing only applies to this file, and not this project as a
> > + * whole.
> > + *
> > + *  a) This file is free software; you can redistribute it and/or
> > + *     modify it under the terms of the GNU General Public License as
> > + *     published by the Free Software Foundation; either version 2 of the
> > + *     License, or (at your option) any later version.
> > + *
> > + *     This file is distributed in the hope that it will be useful,
> > + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + *     GNU General Public License for more details.
> > + *
> > + * Or, alternatively,
> > + *
> > + *  b) Permission is hereby granted, free of charge, to any person
> > + *     obtaining a copy of this software and associated documentation
> > + *     files (the "Software"), to deal in the Software without
> > + *     restriction, including without limitation the rights to use,
> > + *     copy, modify, merge, publish, distribute, sublicense, and/or
> > + *     sell copies of the Software, and to permit persons to whom the
> > + *     Software is furnished to do so, subject to the following
> > + *     conditions:
> > + *
> > + *     The above copyright notice and this permission notice shall be
> > + *     included in all copies or substantial portions of the Software.
> > + *
> > + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> > + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> > + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> > + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> > + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> > + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> > + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > + *     OTHER DEALINGS IN THE SOFTWARE.
> > + */
> > +
> > +/dts-v1/;
> > +#include "sun8i-a83t.dtsi"
> > +
> > +#include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/input/input.h>
> > +#include <dt-bindings/pinctrl/sun4i-a10.h>
>
> Do you need those headers?
I'll verify.
>
> > +
> > +/ {
> > +     model = "Allwinner A83T H8Homlet Proto Dev Board v2.0";
> > +     compatible = "allwinner,homletv2", "allwinner,sun8i-a83t";
>
>                                 ^ Please add a dash here
>
> > +
> > +     aliases {
> > +             serial0 = &uart0;
> > +     };
> > +
> > +     chosen {
> > +             stdout-path = "serial0:115200n8";
> > +             bootargs = "earlyprintk console=ttyS0,115200";
>
> console is useless here, and please remove earlyprintk. It will make
> your kernel crash if the image is configured for another SoC.
>
Okie.
> > +     };
> > +};
> > +
> > +&uart0 {
> > +     pinctrl-names = "default";
> > +     pinctrl-0 = <&uart0_pins_a>;
> > +     status = "okay";
> > +};
> > --
> > 1.9.1
> >
>
> Thanks!
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux, Kernel and Android engineering
> http://free-electrons.com

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH 2/4] pinctrl: sunxi: add allwinner A83T PIO controller support
  2015-09-22 16:06       ` Chen-Yu Tsai
@ 2015-09-24 10:15         ` Maxime Ripard
  0 siblings, 0 replies; 19+ messages in thread
From: Maxime Ripard @ 2015-09-24 10:15 UTC (permalink / raw)
  To: Chen-Yu Tsai
  Cc: Vishnu Patekar, Rob Herring, Pawel Moll, Mark Rutland,
	Ian Campbell, Kumar Gala, Russell King - ARM Linux, Emilio Lopez,
	Linus Walleij, Jens Kuske, Hans De Goede, devicetree,
	linux-arm-kernel, linux-kernel, linux-sunxi,
	linux-gpio@vger.kernel.org

[-- Attachment #1: Type: text/plain, Size: 647 bytes --]

On Wed, Sep 23, 2015 at 12:06:56AM +0800, Chen-Yu Tsai wrote:
> > +static const struct sunxi_pinctrl_desc sun8i_a83t_pinctrl_data = {
> > +       .pins = sun8i_a83t_pins,
> > +       .npins = ARRAY_SIZE(sun8i_a83t_pins),
> > +       .irq_banks = 3,
> 
> Do you know if there's a hole at where PA_EINT interrupt registers
> should be? AFAIK we aren't handling that properly, but that is outside
> the scope of this patch.

Judging from the A83t datasheet, PB seems to be the first IRQ bank, so
it should be fine.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 819 bytes --]

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH 1/4] ARM: sunxi: Introduce Allwinner for A83T support
  2015-09-22 15:47       ` Chen-Yu Tsai
       [not found]         ` <CAGb2v665FhnSoWYGJn+Tf79F7pZitYBrEOmAts4nVoUWb-uBqg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
@ 2015-09-24 10:52         ` Vishnu Patekar
  1 sibling, 0 replies; 19+ messages in thread
From: Vishnu Patekar @ 2015-09-24 10:52 UTC (permalink / raw)
  To: Chen-Yu Tsai
  Cc: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
	Maxime Ripard, Russell King - ARM Linux, Emilio Lopez,
	Linus Walleij, Jens Kuske, Hans De Goede, devicetree,
	linux-arm-kernel, linux-kernel, linux-sunxi,
	linux-gpio@vger.kernel.org

Hello,

On Tue, Sep 22, 2015 at 11:47 PM, Chen-Yu Tsai <wens@csie.org> wrote:
> On Tue, Sep 22, 2015 at 11:38 PM, Vishnu Patekar
> <vishnupatekar0510@gmail.com> wrote:
>> Allwinner A83T is octa-core cortex-a7 based SoC.
>> It's clock control unit and prcm, pinmux are different from previous sun8i
>> series.
>> Its processor cores are arragned in two clusters 4 cores each,
>> similar to A80.
>>
>> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
>> ---
>>  Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
>>  arch/arm/mach-sunxi/sunxi.c                     | 1 +
>>  drivers/clk/sunxi/clk-sunxi.c                   | 6 ++++++
>>  3 files changed, 8 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt
>> index 67da205..cf5ed27 100644
>> --- a/Documentation/devicetree/bindings/arm/sunxi.txt
>> +++ b/Documentation/devicetree/bindings/arm/sunxi.txt
>> @@ -11,4 +11,5 @@ using one of the following compatible strings:
>>    allwinner,sun8i-a23
>>    allwinner,sun8i-a33
>>    allwinner,sun8i-h3
>> +  allwinner,sun8i-a83t
>
> Alphabetic order please.
Okie, I'll correct.
>
>>    allwinner,sun9i-a80
>> diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
>> index 65bab28..b04aefa 100644
>> --- a/arch/arm/mach-sunxi/sunxi.c
>> +++ b/arch/arm/mach-sunxi/sunxi.c
>> @@ -69,6 +69,7 @@ static const char * const sun8i_board_dt_compat[] = {
>>         "allwinner,sun8i-a23",
>>         "allwinner,sun8i-a33",
>>         "allwinner,sun8i-h3",
>> +       "allwinner,sun8i-a83t",
>
> Same here.
>
>>         NULL,
>>  };
>>
>> diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
>> index 413070d..f216d5d 100644
>> --- a/drivers/clk/sunxi/clk-sunxi.c
>> +++ b/drivers/clk/sunxi/clk-sunxi.c
>> @@ -1212,6 +1212,12 @@ CLK_OF_DECLARE(sun6i_a31s_clk_init, "allwinner,sun6i-a31s", sun6i_init_clocks);
>>  CLK_OF_DECLARE(sun8i_a23_clk_init, "allwinner,sun8i-a23", sun6i_init_clocks);
>>  CLK_OF_DECLARE(sun8i_a33_clk_init, "allwinner,sun8i-a33", sun6i_init_clocks);
>>
>> +static void __init sun8ia83t_init_clocks(struct device_node *node)
>> +{
>> +       sunxi_init_clocks(NULL, 0);
>> +}
>> +CLK_OF_DECLARE(sun9i_a83t_clk_init, "allwinner,sun8i-a83t", sun8ia83t_init_clocks);
>
> sun8i? Missing underscore too.
Sorry, yes, sun8i. will add _.
>
> I think you should add this once you actually have clock support.
> Otherwise this call basically does nothing.
>
>> +
>>  static void __init sun9i_init_clocks(struct device_node *node)
>>  {
>>         sunxi_init_clocks(NULL, 0);
>
> On the side, I will send patches to remove sun9i_init_clocks.
>
>
> Regards
> ChenYu
Thanks for review.

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH 1/4] ARM: sunxi: Introduce Allwinner for A83T support
  2015-09-22 15:51       ` Maxime Ripard
@ 2015-09-24 10:55         ` Vishnu Patekar
  0 siblings, 0 replies; 19+ messages in thread
From: Vishnu Patekar @ 2015-09-24 10:55 UTC (permalink / raw)
  To: Maxime Ripard
  Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
	pawel.moll-5wv7dgnIgG8@public.gmane.org,
	mark.rutland-5wv7dgnIgG8@public.gmane.org,
	ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org,
	Kumar Gala, linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org,
	emilio-0Z03zUJReD5OxF6Tv1QG9Q, Linus Walleij, Jens Kuske,
	Hans de Goede, Chen-Yu Tsai,
	devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org,
	linux-gpio-u79uwXL29TY76Z2rM5mHXA

Hello,

On Tue, Sep 22, 2015 at 11:51 PM, Maxime Ripard
<maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> wrote:
> Hi,
>
> On Tue, Sep 22, 2015 at 11:38:54PM +0800, Vishnu Patekar wrote:
>> Allwinner A83T is octa-core cortex-a7 based SoC.
>> It's clock control unit and prcm, pinmux are different from previous sun8i
>> series.
>> Its processor cores are arragned in two clusters 4 cores each,
>> similar to A80.
>>
>> Signed-off-by: Vishnu Patekar <vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>> ---
>>  Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
>>  arch/arm/mach-sunxi/sunxi.c                     | 1 +
>>  drivers/clk/sunxi/clk-sunxi.c                   | 6 ++++++
>>  3 files changed, 8 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt
>> index 67da205..cf5ed27 100644
>> --- a/Documentation/devicetree/bindings/arm/sunxi.txt
>> +++ b/Documentation/devicetree/bindings/arm/sunxi.txt
>> @@ -11,4 +11,5 @@ using one of the following compatible strings:
>>    allwinner,sun8i-a23
>>    allwinner,sun8i-a33
>>    allwinner,sun8i-h3
>> +  allwinner,sun8i-a83t
>>    allwinner,sun9i-a80
>> diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
>> index 65bab28..b04aefa 100644
>> --- a/arch/arm/mach-sunxi/sunxi.c
>> +++ b/arch/arm/mach-sunxi/sunxi.c
>> @@ -69,6 +69,7 @@ static const char * const sun8i_board_dt_compat[] = {
>>       "allwinner,sun8i-a23",
>>       "allwinner,sun8i-a33",
>>       "allwinner,sun8i-h3",
>> +     "allwinner,sun8i-a83t",
>>       NULL,
>>  };
>>
>> diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
>> index 413070d..f216d5d 100644
>> --- a/drivers/clk/sunxi/clk-sunxi.c
>> +++ b/drivers/clk/sunxi/clk-sunxi.c
>> @@ -1212,6 +1212,12 @@ CLK_OF_DECLARE(sun6i_a31s_clk_init, "allwinner,sun6i-a31s", sun6i_init_clocks);
>>  CLK_OF_DECLARE(sun8i_a23_clk_init, "allwinner,sun8i-a23", sun6i_init_clocks);
>>  CLK_OF_DECLARE(sun8i_a33_clk_init, "allwinner,sun8i-a33", sun6i_init_clocks);
>>
>> +static void __init sun8ia83t_init_clocks(struct device_node *node)
>
> Having an underscore between sun8i and a83t would be great :)
>
>> +{
>> +     sunxi_init_clocks(NULL, 0);
>> +}
>> +CLK_OF_DECLARE(sun9i_a83t_clk_init, "allwinner,sun8i-a83t", sun8ia83t_init_clocks);
>
>                   ^ Is this a sun9i or sun8i SoC ?
It's sun8i, sorry.
>
> Is the list of protected clocks always going to be empty, or will you
> add some new clocks in that list in the future?
Yes, I'll add new clocks as time permits.
>
> Thanks!
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux, Kernel and Android engineering
> http://free-electrons.com
Thanks for review.

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH 2/4] pinctrl: sunxi: add allwinner A83T PIO controller support
  2015-09-22 15:38   ` [PATCH 2/4] pinctrl: sunxi: add allwinner A83T PIO controller support Vishnu Patekar
       [not found]     ` <1442936337-3104-3-git-send-email-vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
@ 2015-10-02 11:10     ` Linus Walleij
  1 sibling, 0 replies; 19+ messages in thread
From: Linus Walleij @ 2015-10-02 11:10 UTC (permalink / raw)
  To: Vishnu Patekar
  Cc: Rob Herring, Paweł Moll, Mark Rutland,
	ijc+devicetree@hellion.org.uk, Kumar Gala, Maxime Ripard,
	Russell King - ARM Linux, Emilio Lopez, Jens Kuske, Hans de Goede,
	Chen-Yu Tsai, devicetree@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-sunxi,
	linux-gpio@vger.kernel.org

On Tue, Sep 22, 2015 at 8:38 AM, Vishnu Patekar
<vishnupatekar0510@gmail.com> wrote:

> Allwinner A83T soc port controller has 8 ports.
> It has 3 IRQ banks namely PB, PG, PH.
> Pinmuxing are different for some pins as compared to
> sun8i A23 and A33.
>
> Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>

Patch applied with Maxime's ACK.

Yours,
Linus Walleij

^ permalink raw reply	[flat|nested] 19+ messages in thread

end of thread, other threads:[~2015-10-02 11:10 UTC | newest]

Thread overview: 19+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2015-09-22 15:38 [PATCH 0/4] Add basic support for Allwinner A83T SOC Vishnu Patekar
     [not found] ` <1442936337-3104-1-git-send-email-vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2015-09-22 15:38   ` [PATCH 1/4] ARM: sunxi: Introduce Allwinner for A83T support Vishnu Patekar
     [not found]     ` <1442936337-3104-2-git-send-email-vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2015-09-22 15:47       ` Chen-Yu Tsai
     [not found]         ` <CAGb2v665FhnSoWYGJn+Tf79F7pZitYBrEOmAts4nVoUWb-uBqg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2015-09-22 15:53           ` Maxime Ripard
2015-09-22 15:56             ` Chen-Yu Tsai
2015-09-24 10:52         ` Vishnu Patekar
2015-09-22 15:51       ` Maxime Ripard
2015-09-24 10:55         ` Vishnu Patekar
2015-09-22 15:38   ` [PATCH 2/4] pinctrl: sunxi: add allwinner A83T PIO controller support Vishnu Patekar
     [not found]     ` <1442936337-3104-3-git-send-email-vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2015-09-22 15:49       ` Maxime Ripard
2015-09-22 16:06       ` Chen-Yu Tsai
2015-09-24 10:15         ` Maxime Ripard
2015-10-02 11:10     ` Linus Walleij
2015-09-22 15:38   ` [PATCH 3/4] ARM: dts: sun8i: Add Allwinner A83T dtsi Vishnu Patekar
     [not found]     ` <1442936337-3104-4-git-send-email-vishnupatekar0510-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2015-09-22 15:54       ` Maxime Ripard
2015-09-22 16:15         ` Chen-Yu Tsai
2015-09-22 15:38   ` [PATCH 4/4] ARM: dts: sun8i: Add A83T HomletV2 Board by Allwinner Vishnu Patekar
2015-09-22 16:00     ` Maxime Ripard
2015-09-22 16:21       ` Vishnu Patekar

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).