* [PATCH v4] Fix sun7i pin assignment for IRQ's
@ 2016-02-21 23:17 Henry Paulissen
[not found] ` <1456096638-21961-1-git-send-email-henry-oxlTVf6CAJF4HdFT58BDcQ@public.gmane.org>
2016-02-25 9:26 ` Linus Walleij
0 siblings, 2 replies; 3+ messages in thread
From: Henry Paulissen @ 2016-02-21 23:17 UTC (permalink / raw)
To: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
Cc: Linus Walleij, Maxime Ripard, Chen-Yu Tsai, Patrice Chotard,
Fabian Frederick, Lee Jones, Hongzhou Yang,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
After testing IRQ pins we found some bugs in the pinctrl declaration.
Signed-off-by: Henry Paulissen <henry-oxlTVf6CAJF4HdFT58BDcQ@public.gmane.org>
---
Changes in v2:
After some more testing we found irq on PI pins.
they where on mux6 so this is included in my patch.
Also included is a warning for PI17, this pin was not working
on apritzel his bPI and he thinks it might be correlated to
GIC and IRQ 29.
Changes in v3:
Changed name from nickname to realname in email and SoB.
Changes in v4:
Added closing parenthesis for the C pins
---
drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c | 33 ++++++++++++++-----------------
1 file changed, 15 insertions(+), 18 deletions(-)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
index cf1ce0c..ca7b9a3 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
@@ -343,26 +343,22 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */
- SUNXI_FUNCTION(0x3, "spi2"), /* CS0 */
- SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */
+ SUNXI_FUNCTION(0x3, "spi2")), /* CS0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 20),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NCE5 */
- SUNXI_FUNCTION(0x3, "spi2"), /* CLK */
- SUNXI_FUNCTION_IRQ(0x6, 13)), /* EINT13 */
+ SUNXI_FUNCTION(0x3, "spi2")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 21),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NCE6 */
- SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */
- SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */
+ SUNXI_FUNCTION(0x3, "spi2")), /* MOSI */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 22),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NCE7 */
- SUNXI_FUNCTION(0x3, "spi2"), /* MISO */
- SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */
+ SUNXI_FUNCTION(0x3, "spi2")), /* MISO */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 23),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
@@ -960,65 +956,66 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */
SUNXI_FUNCTION(0x3, "uart5"), /* TX */
- SUNXI_FUNCTION_IRQ(0x5, 22)), /* EINT22 */
+ SUNXI_FUNCTION_IRQ(0x6, 22)), /* EINT22 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
SUNXI_FUNCTION(0x3, "uart5"), /* RX */
- SUNXI_FUNCTION_IRQ(0x5, 23)), /* EINT23 */
+ SUNXI_FUNCTION_IRQ(0x6, 23)), /* EINT23 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */
SUNXI_FUNCTION(0x3, "uart6"), /* TX */
SUNXI_FUNCTION(0x4, "clk_out_a"), /* CLK_OUT_A */
- SUNXI_FUNCTION_IRQ(0x5, 24)), /* EINT24 */
+ SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* MISO */
SUNXI_FUNCTION(0x3, "uart6"), /* RX */
SUNXI_FUNCTION(0x4, "clk_out_b"), /* CLK_OUT_B */
- SUNXI_FUNCTION_IRQ(0x5, 25)), /* EINT25 */
+ SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* CS1 */
SUNXI_FUNCTION(0x3, "ps2"), /* SCK1 */
SUNXI_FUNCTION(0x4, "timer4"), /* TCLKIN0 */
- SUNXI_FUNCTION_IRQ(0x5, 26)), /* EINT26 */
+ SUNXI_FUNCTION_IRQ(0x6, 26)), /* EINT26 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
SUNXI_FUNCTION(0x3, "ps2"), /* SDA1 */
SUNXI_FUNCTION(0x4, "timer5"), /* TCLKIN1 */
- SUNXI_FUNCTION_IRQ(0x5, 27)), /* EINT27 */
+ SUNXI_FUNCTION_IRQ(0x6, 27)), /* EINT27 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
SUNXI_FUNCTION(0x3, "uart2"), /* RTS */
- SUNXI_FUNCTION_IRQ(0x5, 28)), /* EINT28 */
+ SUNXI_FUNCTION_IRQ(0x6, 28)), /* EINT28 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
SUNXI_FUNCTION(0x3, "uart2"), /* CTS */
- SUNXI_FUNCTION_IRQ(0x5, 29)), /* EINT29 */
+ SUNXI_FUNCTION_IRQ(0x6, 29)), /* EINT29 */
+ /* EINT29 might not work - more testing needed */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
SUNXI_FUNCTION(0x3, "uart2"), /* TX */
- SUNXI_FUNCTION_IRQ(0x5, 30)), /* EINT30 */
+ SUNXI_FUNCTION_IRQ(0x6, 30)), /* EINT30 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 19),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
SUNXI_FUNCTION(0x3, "uart2"), /* RX */
- SUNXI_FUNCTION_IRQ(0x5, 31)), /* EINT31 */
+ SUNXI_FUNCTION_IRQ(0x6, 31)), /* EINT31 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 20),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
--
2.5.0
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH v4] Fix sun7i pin assignment for IRQ's
[not found] ` <1456096638-21961-1-git-send-email-henry-oxlTVf6CAJF4HdFT58BDcQ@public.gmane.org>
@ 2016-02-21 23:46 ` Chen-Yu Tsai
0 siblings, 0 replies; 3+ messages in thread
From: Chen-Yu Tsai @ 2016-02-21 23:46 UTC (permalink / raw)
To: Henry Paulissen
Cc: linux-sunxi, Linus Walleij, Maxime Ripard, Chen-Yu Tsai,
Patrice Chotard, Fabian Frederick, Lee Jones, Hongzhou Yang,
linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel, linux-kernel
On Sun, Feb 21, 2016 at 3:17 PM, Henry Paulissen <draakje197-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> After testing IRQ pins we found some bugs in the pinctrl declaration.
>
> Signed-off-by: Henry Paulissen <henry-oxlTVf6CAJF4HdFT58BDcQ@public.gmane.org>
Acked-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v4] Fix sun7i pin assignment for IRQ's
2016-02-21 23:17 [PATCH v4] Fix sun7i pin assignment for IRQ's Henry Paulissen
[not found] ` <1456096638-21961-1-git-send-email-henry-oxlTVf6CAJF4HdFT58BDcQ@public.gmane.org>
@ 2016-02-25 9:26 ` Linus Walleij
1 sibling, 0 replies; 3+ messages in thread
From: Linus Walleij @ 2016-02-25 9:26 UTC (permalink / raw)
To: Henry Paulissen
Cc: linux-sunxi, Maxime Ripard, Chen-Yu Tsai, Patrice Chotard,
Fabian Frederick, Lee Jones, Hongzhou Yang,
linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
On Mon, Feb 22, 2016 at 12:17 AM, Henry Paulissen <draakje197@gmail.com> wrote:
> After testing IRQ pins we found some bugs in the pinctrl declaration.
>
> Signed-off-by: Henry Paulissen <henry@nitronetworks.nl>
This v4 patch applied with Chen-Yu's ACK.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 3+ messages in thread
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2016-02-21 23:17 [PATCH v4] Fix sun7i pin assignment for IRQ's Henry Paulissen
[not found] ` <1456096638-21961-1-git-send-email-henry-oxlTVf6CAJF4HdFT58BDcQ@public.gmane.org>
2016-02-21 23:46 ` Chen-Yu Tsai
2016-02-25 9:26 ` Linus Walleij
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