Re: [PATCH v2 1/1] gpio: merrifield: Introduce GPIO driver to support Merrifield

[Andy Shevchenko <andriy.shevchenko@linux.intel.com>]

On Mon, 2016-07-11 at 11:06 +0200, Linus Walleij wrote:
> On Fri, Jul 8, 2016 at 1:08 PM, Andy Shevchenko
> <andriy.shevchenko@linux.intel.com> wrote:
> 
> > Intel Merrifield platform has a special GPIO controller to drive
> > pads when they
> > are muxed in corresponding mode.
> > 
> > Intel Merrifield GPIO IP is slightly different here and there in
> > comparison to
> > the older Intel MID platforms. These differences include in
> > particular the
> > shaked register offsets, specific support of level triggered
> > interrupts and
> > wake capable sources, as well as a pinctrl which is a separate IP.
> > 
> > Instead of uglifying existing driver I decide to provide a new one
> > slightly
> > based on gpio-intel-mid.c. So, anyone can easily compare what
> > changes are
> > happened to be here.
> > 
> > Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> 
> That is a nice driver.
> 
> I'm especially fond of the way you carefully handle the edge vs
> level IRQs, good job.

Thanks!

> 
> > +static const struct mrfld_gpio_pinrange mrfld_gpio_ranges[] = {
> > +       GPIO_PINRANGE(0, 11, 146),
> > +       GPIO_PINRANGE(12, 13, 144),
> > +       GPIO_PINRANGE(14, 15, 35),
> > +       GPIO_PINRANGE(16, 16, 164),
> > +       GPIO_PINRANGE(17, 18, 105),
> > +       GPIO_PINRANGE(19, 22, 101),
> > +       GPIO_PINRANGE(23, 30, 107),
> > +       GPIO_PINRANGE(32, 43, 67),
> > +       GPIO_PINRANGE(44, 63, 195),
> > +       GPIO_PINRANGE(64, 67, 140),
> > +       GPIO_PINRANGE(68, 69, 165),
> > +       GPIO_PINRANGE(70, 71, 65),
> > +       GPIO_PINRANGE(72, 76, 228),
> > +       GPIO_PINRANGE(77, 86, 37),
> > +       GPIO_PINRANGE(87, 87, 48),
> > +       GPIO_PINRANGE(88, 88, 47),
> > +       GPIO_PINRANGE(89, 96, 49),
> > +       GPIO_PINRANGE(97, 97, 34),
> > +       GPIO_PINRANGE(102, 119, 83),
> > +       GPIO_PINRANGE(120, 123, 79),
> > +       GPIO_PINRANGE(124, 135, 115),
> > +       GPIO_PINRANGE(137, 142, 158),
> > +       GPIO_PINRANGE(154, 163, 24),
> > +       GPIO_PINRANGE(164, 176, 215),
> > +       GPIO_PINRANGE(177, 189, 127),
> > +       GPIO_PINRANGE(190, 191, 178),
> > +};
> 
> In device tree we put this into the hardware description (the device
> tree),
> and I'm expecting ACPI to come up with something similar, but I guess
> that
> for a pure PCI device you have no choice but to do it this way.
> 
> And you also do it the elegant way by associating with the gpiochip
> rather than the other way around from the pin controller side.

Unfortunately this all Intel MID era is scary SFI, we have no other
choice for most of the drivers for it.

But for ACPI we would really try hard to do our best and provide
information in some tables/properties.

-- 

Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy
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