From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Linus Walleij <linus.walleij@linaro.org>
Cc: "linux-gpio@vger.kernel.org" <linux-gpio@vger.kernel.org>,
Mika Westerberg <mika.westerberg@linux.intel.com>,
Jarkko Nikula <jarkko.nikula@linux.intel.com>
Subject: Re: [PATCH v1 1/1] pinctrl: intel: Set pin direction properly
Date: Wed, 11 Jan 2017 16:21:26 +0200 [thread overview]
Message-ID: <1484144486.2133.62.camel@linux.intel.com> (raw)
In-Reply-To: <CACRpkdY8fUR6-WE9TE9V3AxsWWjKs-gwQbUG5Afoe9fmYUnkmQ@mail.gmail.com>
On Wed, 2017-01-11 at 13:50 +0100, Linus Walleij wrote:
> On Mon, Jan 2, 2017 at 1:07 PM, Andy Shevchenko
> <andriy.shevchenko@linux.intel.com> wrote:
>
> > There are two bits in the PADCFG0 register to configure direction,
> > one per
> > TX/RX buffers.
> >
> > For now we wrongly assume that the GPIO is always requested before
> > it is being
> > used, which is not true when the GPIO is used through irqchip. In
> > this case the
> > GPIO is never requested and we never enable RX buffer for it.
> >
> > Fix this by setting both bits accordingly.
> >
> > Reported-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
> > Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
>
> I applied this patch for fixes on top of Mika's pad offset
> fix.
>
> Hope this is right... There is some noise in the thread but
> AFAICT there are more fixes coming.
Yes, it's self-sufficient and needed independently of the rest.
Thanks!
--
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy
prev parent reply other threads:[~2017-01-11 14:21 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-02 12:07 [PATCH v1 1/1] pinctrl: intel: Set pin direction properly Andy Shevchenko
2017-01-09 14:29 ` Jarkko Nikula
2017-01-09 14:45 ` Andy Shevchenko
2017-01-09 15:12 ` Jarkko Nikula
2017-01-09 15:41 ` Andy Shevchenko
2017-01-11 12:50 ` Linus Walleij
2017-01-11 14:21 ` Andy Shevchenko [this message]
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