From: Yoshihiro Kaneko <ykaneko0929@gmail.com>
To: linux-gpio@vger.kernel.org
Cc: Linus Walleij <linus.walleij@linaro.org>,
Laurent Pinchart <laurent.pinchart@ideasonboard.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Simon Horman <horms@verge.net.au>,
Magnus Damm <magnus.damm@gmail.com>,
linux-renesas-soc@vger.kernel.org
Subject: [PATCH 1/9] pinctrl: sh-pfc: r8a7795: Fix MOD_SEL1 bit[25:24] to 0x3 when using STP_ISEN_1_D
Date: Fri, 28 Jul 2017 20:41:13 +0900 [thread overview]
Message-ID: <1501242081-3805-2-git-send-email-ykaneko0929@gmail.com> (raw)
In-Reply-To: <1501242081-3805-1-git-send-email-ykaneko0929@gmail.com>
From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
This patch fixes the implementation incorrect of MOD_SEL1 bit[25:24]
value when STP_ISEN_1_D pin function is selected for IPSR17 bit[27:24].
This is a correction to the incorrect implementation of MOD_SEL register
pin assignment for R8A7795 SoC specification of R-Car Gen3 Hardware
User's Manual Rev.0.51E or later.
Fixes: 0b0ffc96dbe3 ("pinctrl: sh-pfc: Initial R8A7795 PFC support)
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
---
drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
index 1656295..73507bf 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
@@ -1460,7 +1460,7 @@ enum {
PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI_1),
PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
- PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_2),
+ PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU_1),
--
1.9.1
next prev parent reply other threads:[~2017-07-28 11:41 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-07-28 11:41 [PATCH 0/9] pinctrl: sh-pfc: r8a7795: Fix pin assignment definitions Yoshihiro Kaneko
2017-07-28 11:41 ` Yoshihiro Kaneko [this message]
2017-08-16 11:55 ` [PATCH 1/9] pinctrl: sh-pfc: r8a7795: Fix MOD_SEL1 bit[25:24] to 0x3 when using STP_ISEN_1_D Geert Uytterhoeven
2017-07-28 11:41 ` [PATCH 2/9] pinctrl: sh-pfc: r8a7795: Fix MOD_SEL2 bit26 to 0x0 when using SCK5_A Yoshihiro Kaneko
2017-08-16 11:59 ` Geert Uytterhoeven
2017-07-28 11:41 ` [PATCH 3/9] pinctrl: sh-pfc: r8a7795: Fix SCIF_CLK_{A,B} pin's MOD_SEL assignment to MOD_SEL1 bit10 Yoshihiro Kaneko
2017-08-16 12:01 ` Geert Uytterhoeven
2017-07-28 11:41 ` [PATCH 4/9] pinctrl: sh-pfc: r8a7795: Fix FMCLK{_C,_D} and FMIN{_C,_D} pin function definitions Yoshihiro Kaneko
2017-08-16 12:04 ` Geert Uytterhoeven
2017-07-28 11:41 ` [PATCH 5/9] pinctrl: sh-pfc: r8a7795: Fix NFDATA{0..13} and NF{ALE,CLE,WE_N,RE_N} " Yoshihiro Kaneko
2017-08-16 12:06 ` Geert Uytterhoeven
2017-07-28 11:41 ` [PATCH 6/9] pinctrl: sh-pfc: r8a7795: Fix MOD_SEL register pin assignment for TCLK{1,2}_{A,B} pins group Yoshihiro Kaneko
2017-08-16 12:13 ` Geert Uytterhoeven
2017-07-28 11:41 ` [PATCH 7/9] pinctrl: sh-pfc: r8a7795: Fix to delete FSCLKST pin and IPSR7 bit[15:12] register definitions Yoshihiro Kaneko
2017-08-16 12:19 ` Geert Uytterhoeven
2017-07-28 11:41 ` [PATCH 8/9] pinctrl: sh-pfc: r8a7795: Rename CS1# pin function definitions Yoshihiro Kaneko
2017-08-16 12:20 ` Geert Uytterhoeven
2017-07-28 11:41 ` [PATCH 9/9] pinctrl: sh-pfc: r8a7795: Fix to reserved MOD_SEL2 bit22 Yoshihiro Kaneko
2017-08-16 12:23 ` Geert Uytterhoeven
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