From: Srinivas Neeli <srinivas.neeli@xilinx.com>
To: <linus.walleij@linaro.org>, <bgolaszewski@baylibre.com>,
<michal.simek@xilinx.com>, <shubhrajyoti.datta@xilinx.com>,
<sgoud@xilinx.com>, <hancock@sedsystems.ca>,
<vilhelm.gray@gmail.com>, <syednwaris@gmail.com>
Cc: <linux-gpio@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <git@xilinx.com>,
Srinivas Neeli <srinivas.neeli@xilinx.com>
Subject: [PATCH V4 2/5] gpio: gpio-xilinx: Reduce spinlock array to array
Date: Wed, 6 Jan 2021 17:56:37 +0530 [thread overview]
Message-ID: <1609936000-28378-3-git-send-email-srinivas.neeli@xilinx.com> (raw)
In-Reply-To: <1609936000-28378-1-git-send-email-srinivas.neeli@xilinx.com>
Changed spinlock array to single. It is preparation for irq support which
is shared between two channels that's why spinlock should be only one.
Signed-off-by: Srinivas Neeli <srinivas.neeli@xilinx.com>
---
Changes in V4:
-None.
Changes in V3:
-Created new patch for spinlock changes.
---
drivers/gpio/gpio-xilinx.c | 25 ++++++++++++-------------
1 file changed, 12 insertions(+), 13 deletions(-)
diff --git a/drivers/gpio/gpio-xilinx.c b/drivers/gpio/gpio-xilinx.c
index d010a63d5d15..f88db56543c2 100644
--- a/drivers/gpio/gpio-xilinx.c
+++ b/drivers/gpio/gpio-xilinx.c
@@ -47,7 +47,7 @@ struct xgpio_instance {
unsigned int gpio_width[2];
u32 gpio_state[2];
u32 gpio_dir[2];
- spinlock_t gpio_lock[2];
+ spinlock_t gpio_lock; /* For serializing operations */
struct clk *clk;
};
@@ -113,7 +113,7 @@ static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
int index = xgpio_index(chip, gpio);
int offset = xgpio_offset(chip, gpio);
- spin_lock_irqsave(&chip->gpio_lock[index], flags);
+ spin_lock_irqsave(&chip->gpio_lock, flags);
/* Write to GPIO signal and set its direction to output */
if (val)
@@ -124,7 +124,7 @@ static void xgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET +
xgpio_regoffset(chip, gpio), chip->gpio_state[index]);
- spin_unlock_irqrestore(&chip->gpio_lock[index], flags);
+ spin_unlock_irqrestore(&chip->gpio_lock, flags);
}
/**
@@ -144,7 +144,7 @@ static void xgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
int index = xgpio_index(chip, 0);
int offset, i;
- spin_lock_irqsave(&chip->gpio_lock[index], flags);
+ spin_lock_irqsave(&chip->gpio_lock, flags);
/* Write to GPIO signals */
for (i = 0; i < gc->ngpio; i++) {
@@ -155,9 +155,9 @@ static void xgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET +
index * XGPIO_CHANNEL_OFFSET,
chip->gpio_state[index]);
- spin_unlock_irqrestore(&chip->gpio_lock[index], flags);
+ spin_unlock_irqrestore(&chip->gpio_lock, flags);
index = xgpio_index(chip, i);
- spin_lock_irqsave(&chip->gpio_lock[index], flags);
+ spin_lock_irqsave(&chip->gpio_lock, flags);
}
if (__test_and_clear_bit(i, mask)) {
offset = xgpio_offset(chip, i);
@@ -171,7 +171,7 @@ static void xgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
xgpio_writereg(chip->regs + XGPIO_DATA_OFFSET +
index * XGPIO_CHANNEL_OFFSET, chip->gpio_state[index]);
- spin_unlock_irqrestore(&chip->gpio_lock[index], flags);
+ spin_unlock_irqrestore(&chip->gpio_lock, flags);
}
/**
@@ -190,14 +190,14 @@ static int xgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
int index = xgpio_index(chip, gpio);
int offset = xgpio_offset(chip, gpio);
- spin_lock_irqsave(&chip->gpio_lock[index], flags);
+ spin_lock_irqsave(&chip->gpio_lock, flags);
/* Set the GPIO bit in shadow register and set direction as input */
chip->gpio_dir[index] |= BIT(offset);
xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET +
xgpio_regoffset(chip, gpio), chip->gpio_dir[index]);
- spin_unlock_irqrestore(&chip->gpio_lock[index], flags);
+ spin_unlock_irqrestore(&chip->gpio_lock, flags);
return 0;
}
@@ -221,7 +221,7 @@ static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
int index = xgpio_index(chip, gpio);
int offset = xgpio_offset(chip, gpio);
- spin_lock_irqsave(&chip->gpio_lock[index], flags);
+ spin_lock_irqsave(&chip->gpio_lock, flags);
/* Write state of GPIO signal */
if (val)
@@ -236,7 +236,7 @@ static int xgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
xgpio_writereg(chip->regs + XGPIO_TRI_OFFSET +
xgpio_regoffset(chip, gpio), chip->gpio_dir[index]);
- spin_unlock_irqrestore(&chip->gpio_lock[index], flags);
+ spin_unlock_irqrestore(&chip->gpio_lock, flags);
return 0;
}
@@ -312,7 +312,7 @@ static int xgpio_probe(struct platform_device *pdev)
if (of_property_read_u32(np, "xlnx,gpio-width", &chip->gpio_width[0]))
chip->gpio_width[0] = 32;
- spin_lock_init(&chip->gpio_lock[0]);
+ spin_lock_init(&chip->gpio_lock);
if (of_property_read_u32(np, "xlnx,is-dual", &is_dual))
is_dual = 0;
@@ -336,7 +336,6 @@ static int xgpio_probe(struct platform_device *pdev)
&chip->gpio_width[1]))
chip->gpio_width[1] = 32;
- spin_lock_init(&chip->gpio_lock[1]);
}
chip->gc.base = -1;
--
2.7.4
next prev parent reply other threads:[~2021-01-06 12:28 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-06 12:26 [PATCH V4 0/5] gpio-xilinx: Update on xilinx gpio driver Srinivas Neeli
2021-01-06 12:26 ` [PATCH V4 1/5] gpio: gpio-xilinx: Simplify with dev_err_probe() Srinivas Neeli
2021-01-07 9:13 ` Linus Walleij
2021-01-06 12:26 ` Srinivas Neeli [this message]
2021-01-07 9:14 ` [PATCH V4 2/5] gpio: gpio-xilinx: Reduce spinlock array to array Linus Walleij
2021-01-06 12:26 ` [PATCH V4 3/5] gpio: gpio-xilinx: Add interrupt support Srinivas Neeli
2021-01-07 9:26 ` Linus Walleij
2021-01-06 12:26 ` [PATCH V4 4/5] gpio: gpio-xilinx: Add support for suspend and resume Srinivas Neeli
2021-01-07 9:46 ` Linus Walleij
2021-01-08 11:41 ` Srinivas Neeli
2021-01-09 0:25 ` Linus Walleij
2021-01-06 12:26 ` [PATCH V4 5/5] gpio: gpio-xilinx: Add check if width exceeds 32 Srinivas Neeli
2021-01-07 10:17 ` Linus Walleij
2021-01-07 10:29 ` Michal Simek
2021-01-07 10:47 ` Linus Walleij
2021-01-07 10:52 ` Michal Simek
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