Re: [v2, 04/12] pinctrl: mediatek: moore: check if pin_desc is valid before use

Re: [v2, 04/12] pinctrl: mediatek: moore: check if pin_desc is valid before use

[sean.wang]

From: Sean Wang <sean.wang@mediatek.com>

>Certain SoC are missing the middle part gpios in consecutive pins, it's better to check if mtk_pin_desc is a valid pin for the extensibility
>
>Signed-off-by: Sam Shih <sam.shih@mediatek.com>
>


>---
>v2: applied the comment suggested by reviewers:
>    - for the pins not ballout, we can fill .name in struct mtk_pin_desc
>      as NULL and return -ENOTSUPP in gpio/pinconf ops.

Thanks for take the suggestion and the improvement.
Acked-by: Sean Wang <sean.wang@mediatek.com>

>
>---
> drivers/pinctrl/mediatek/pinctrl-moore.c | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
>diff --git a/drivers/pinctrl/mediatek/pinctrl-moore.c b/drivers/pinctrl/mediatek/pinctrl-moore.c
>index 3a4a23c40a71..ad3b67163973 100644
>--- a/drivers/pinctrl/mediatek/pinctrl-moore.c
>+++ b/drivers/pinctrl/mediatek/pinctrl-moore.c
>@@ -60,6 +60,8 @@ static int mtk_pinmux_set_mux(struct pinctrl_dev *pctldev,
>		int pin = grp->pins[i];
>
>		desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
>+		if (!desc->name)
>+			return -ENOTSUPP;
>
>		mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
>				 pin_modes[i]);
>@@ -76,6 +78,8 @@ static int mtk_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
>	const struct mtk_pin_desc *desc;
>
>	desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
>+	if (!desc->name)
>+		return -ENOTSUPP;

<snip>

Re: [v2,06/12] pinctrl: mediatek: add support for MT7986 SoC

[sean.wang]

From: Sean Wang <sean.wang@mediatek.com>

>This commit includes pinctrl driver for Mediatek MT7986
>
>The difference of pinctrl between mt7986a and mt7986b
>is that pin-41 to pin-65 do not exist on mt7986b
>
>Signed-off-by: Sam Shih <sam.shih@mediatek.com>
>
>---
>v2: applied the comment suggested by reviewers:
>    - for the pins not ballout, we can fill .name in struct mtk_pin_desc
>      as NULL and return -ENOTSUPP in gpio/pinconf ops.
>
>---
> drivers/pinctrl/mediatek/Kconfig          |    7 +
> drivers/pinctrl/mediatek/Makefile         |    1 +
> drivers/pinctrl/mediatek/pinctrl-mt7986.c | 1217 +++++++++++++++++++++
> 3 files changed, 1225 insertions(+)
> create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7986.c
>
>diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
>index 7040a7a7bd5d..66db4ac5d169 100644
>--- a/drivers/pinctrl/mediatek/Kconfig
>+++ b/drivers/pinctrl/mediatek/Kconfig
>@@ -119,6 +119,13 @@ config PINCTRL_MT7622
>	default ARM64 && ARCH_MEDIATEK
>	select PINCTRL_MTK_MOORE
>
>+config PINCTRL_MT7986
>+	bool "Mediatek MT7986 pin control"
>+	depends on OF
>+	depends on ARM64 || COMPILE_TEST
>+	default ARM64 && ARCH_MEDIATEK
>+	select PINCTRL_MTK_MOORE
>+
> config PINCTRL_MT8167
>	bool "Mediatek MT8167 pin control"
>	depends on OF
>diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile
>index 1bb7f9c65bc2..1e3931d924e7 100644
>--- a/drivers/pinctrl/mediatek/Makefile
>+++ b/drivers/pinctrl/mediatek/Makefile
>@@ -17,6 +17,7 @@ obj-$(CONFIG_PINCTRL_MT6797)	+= pinctrl-mt6797.o
> obj-$(CONFIG_PINCTRL_MT7622)	+= pinctrl-mt7622.o
> obj-$(CONFIG_PINCTRL_MT7623)	+= pinctrl-mt7623.o
> obj-$(CONFIG_PINCTRL_MT7629)	+= pinctrl-mt7629.o
>+obj-$(CONFIG_PINCTRL_MT7986)	+= pinctrl-mt7986.o
> obj-$(CONFIG_PINCTRL_MT8167)	+= pinctrl-mt8167.o
> obj-$(CONFIG_PINCTRL_MT8173)	+= pinctrl-mt8173.o
> obj-$(CONFIG_PINCTRL_MT8183)	+= pinctrl-mt8183.o
>diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7986.c b/drivers/pinctrl/mediatek/pinctrl-mt7986.c
>new file mode 100644
>index 000000000000..808ae4e03eb2
>--- /dev/null
>+++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c
>@@ -0,0 +1,1217 @@
>+// SPDX-License-Identifier: GPL-2.0
>+/*
>+ * The MT7986 driver based on Linux generic pinctrl binding.
>+ *
>+ * Copyright (C) 2021 MediaTek Inc.
>+ * Author: Sam Shih <sam.shih@mediatek.com>
>+ */
>+
>+#include "pinctrl-moore.h"
>+
>+#define MT7986_PIN(_number, _name) MTK_PIN(_number, _name, 0, _number, DRV_GRP4)
>+#define MT7986_NOT_BALLOUT_PIN(_number) { .number = _number }

I preferred explict set .name to NULL to indicate the pin is not ball out.

>+
>+#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,	\
>+			   _x_bits)														\
>+	PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit,		\
>+			   _x_bits, 32, 0)
>+
>+/**
>+ * enum - Locking variants of the iocfg bases
>+ *
>+ * MT7986 have multiple bases to program pin configuration listed as the below:
>+ * iocfg_rt:0x11c30000, iocfg_rb:0x11c40000, iocfg_lt:0x11e20000,
>+ * iocfg_lb:0x11e30000, iocfg_tr:0x11f00000, iocfg_tl:0x11f10000,
>+ * _i_based could be used to indicate what base the pin should be mapped into.
>+ *
>+ * Each iocfg register base control different group of pads on the SoC
>+ *
>+ *
>+ *  chip carrier
>+ *
>+ *      A  B  C  D  E  F  G  H
>+ *    +------------------------+
>+ *  8 | o  o  o  o  o  o  o  o |
>+ *  7 | o  o  o  o  o  o  o  o |
>+ *  6 | o  o  o  o  o  o  o  o |
>+ *  5 | o  o  o  o  o  o  o  o |
>+ *  4 | o  o  o  o  o  o  o  o |
>+ *  3 | o  o  o  o  o  o  o  o |
>+ *  2 | o  o  o  o  o  o  o  o |
>+ *  1 | o  o  o  o  o  o  o  o |
>+ *    +------------------------+
>+ *
>+ *  inside Chip carrier
>+ *
>+ *      A  B  C  D  E  F  G  H
>+ *    +------------------------+
>+ *  8 |                        |
>+ *  7 |        TL  TR          |
>+ *  6 |      +---------+       |
>+ *  5 |   LT |         | RT    |
>+ *  4 |      |         |       |
>+ *  3 |   LB |         | RB    |
>+ *  2 |      +---------+       |
>+ *  1 |                        |
>+ *    +------------------------+
>+ *
>+ */
>+
>+enum {
>+	GPIO_BASE,
>+	IOCFG_RT_BASE,
>+	IOCFG_RB_BASE,
>+	IOCFG_LT_BASE,
>+	IOCFG_LB_BASE,
>+	IOCFG_TR_BASE,
>+	IOCFG_TL_BASE,
>+};
>+
>+static const char *const mt7986_pinctrl_register_base_names[] = {
>+	"gpio_base", "iocfg_rt_base", "iocfg_rb_base", "iocfg_lt_base",
>+	"iocfg_lb_base", "iocfg_tr_base", "iocfg_tl_base",
>+};
>+
>+static const struct mtk_pin_field_calc mt7986_pin_mode_range[] = {
>+	PIN_FIELD(0, 40, 0x300, 0x10, 0, 4),
>+	PIN_FIELD(41, 65, 0x350, 0x10, 4, 4),
>+	PIN_FIELD(66, 68, 0x380, 0x10, 8, 4),
>+	PIN_FIELD(69, 100, 0x380, 0x10, 20, 4),
>+};
>+
>+static const struct mtk_pin_field_calc mt7986_pin_dir_range[] = {
>+	PIN_FIELD(0, 40, 0x0, 0x10, 0, 1),
>+	PIN_FIELD(41, 65, 0x10, 0x10, 9, 1),
>+	PIN_FIELD(66, 68, 0x20, 0x10, 2, 1),
>+	PIN_FIELD(69, 100, 0x20, 0x10, 5, 1),
>+};
>+
>+static const struct mtk_pin_field_calc mt7986_pin_di_range[] = {
>+	PIN_FIELD(0, 40, 0x200, 0x10, 0, 1),
>+	PIN_FIELD(41, 65, 0x210, 0x10, 9, 1),
>+	PIN_FIELD(66, 68, 0x220, 0x10, 2, 1),
>+	PIN_FIELD(69, 100, 0x220, 0x10, 5, 1),
>+};
>+
>+static const struct mtk_pin_field_calc mt7986_pin_do_range[] = {
>+	PIN_FIELD(0, 40, 0x100, 0x10, 0, 1),
>+	PIN_FIELD(41, 65, 0x110, 0x10, 9, 1),
>+	PIN_FIELD(66, 68, 0x120, 0x10, 2, 1),
>+	PIN_FIELD(69, 100, 0x120, 0x10, 5, 1),
>+};
>+
>+static const struct mtk_pin_field_calc mt7986_pin_ies_range[] = {
>+	PIN_FIELD_BASE(0, 0, IOCFG_RB_BASE, 0x40, 0x10, 17, 1),
>+	PIN_FIELD_BASE(1, 1, IOCFG_LT_BASE, 0x20, 0x10, 10, 1),
>+	PIN_FIELD_BASE(2, 2, IOCFG_LT_BASE, 0x20, 0x10, 11, 1),
>+	PIN_FIELD_BASE(3, 3, IOCFG_LB_BASE, 0x20, 0x10, 0, 1),
>+	PIN_FIELD_BASE(4, 4, IOCFG_LB_BASE, 0x20, 0x10, 1, 1),
>+	PIN_FIELD_BASE(5, 5, IOCFG_RB_BASE, 0x40, 0x10, 0, 1),
>+	PIN_FIELD_BASE(6, 6, IOCFG_RB_BASE, 0x40, 0x10, 1, 1),
>+	PIN_FIELD_BASE(7, 7, IOCFG_LT_BASE, 0x20, 0x10, 0, 1),
>+	PIN_FIELD_BASE(8, 8, IOCFG_LT_BASE, 0x20, 0x10, 1, 1),
>+	PIN_FIELD_BASE(9, 9, IOCFG_LT_BASE, 0x20, 0x10, 2, 1),
>+	PIN_FIELD_BASE(10, 10, IOCFG_LT_BASE, 0x20, 0x10, 3, 1),
>+	PIN_FIELD_BASE(11, 11, IOCFG_RB_BASE, 0x40, 0x10, 8, 1),
>+	PIN_FIELD_BASE(12, 12, IOCFG_RB_BASE, 0x40, 0x10, 9, 1),
>+	PIN_FIELD_BASE(13, 13, IOCFG_RB_BASE, 0x40, 0x10, 10, 1),
>+	PIN_FIELD_BASE(14, 14, IOCFG_RB_BASE, 0x40, 0x10, 11, 1),
>+	PIN_FIELD_BASE(15, 15, IOCFG_RB_BASE, 0x40, 0x10, 2, 1),
>+	PIN_FIELD_BASE(16, 16, IOCFG_RB_BASE, 0x40, 0x10, 3, 1),
>+	PIN_FIELD_BASE(17, 17, IOCFG_RB_BASE, 0x40, 0x10, 4, 1),
>+	PIN_FIELD_BASE(18, 18, IOCFG_RB_BASE, 0x40, 0x10, 5, 1),
>+	PIN_FIELD_BASE(19, 19, IOCFG_RB_BASE, 0x40, 0x10, 6, 1),
>+	PIN_FIELD_BASE(20, 20, IOCFG_RB_BASE, 0x40, 0x10, 7, 1),

Actually, we can merge the consecutive entries into one to reduce the table size
For example, we can merge those entries pin 15 ~ 20 into one, from

PIN_FIELD_BASE(15, 15, IOCFG_RB_BASE, 0x40, 0x10, 2, 1),
PIN_FIELD_BASE(16, 16, IOCFG_RB_BASE, 0x40, 0x10, 3, 1),
PIN_FIELD_BASE(17, 17, IOCFG_RB_BASE, 0x40, 0x10, 4, 1),
PIN_FIELD_BASE(18, 18, IOCFG_RB_BASE, 0x40, 0x10, 5, 1),
PIN_FIELD_BASE(19, 19, IOCFG_RB_BASE, 0x40, 0x10, 6, 1),
PIN_FIELD_BASE(20, 20, IOCFG_RB_BASE, 0x40, 0x10, 7, 1),

to

PIN_FIELD_BASE(15, 20, IOCFG_RB_BASE, 0x40, 0x10, 2, 1).

Also please consider merging all the similar occurrences elsewhere to optimize them.

>+	PIN_FIELD_BASE(21, 21, IOCFG_RT_BASE, 0x30, 0x10, 12, 1),
>+	PIN_FIELD_BASE(22, 22, IOCFG_RT_BASE, 0x30, 0x10, 13, 1),
>+	PIN_FIELD_BASE(23, 23, IOCFG_RT_BASE, 0x30, 0x10, 14, 1),
>+	PIN_FIELD_BASE(24, 24, IOCFG_RT_BASE, 0x30, 0x10, 18, 1),
>+	PIN_FIELD_BASE(25, 25, IOCFG_RT_BASE, 0x30, 0x10, 17, 1),
>+	PIN_FIELD_BASE(26, 26, IOCFG_RT_BASE, 0x30, 0x10, 15, 1),
>+	PIN_FIELD_BASE(27, 27, IOCFG_RT_BASE, 0x30, 0x10, 16, 1),

<snip>

[v2,00/12] Add basic SoC support for mediatek mt7986

[Sam Shih]

This patch adds basic SoC support for Mediatek's new 4-core SoC,
MT7986, which is mainly for wifi-router application.

---
v2: updated mt7986 clock releated IDs, dt-binding, and driver
    updated mt7986 clock releated dt-binding and driver
    updated device tree of mt7986a and mt7986b

Sam Shih (12):
  dt-bindings: clock: mediatek: document clk bindings for mediatek
    mt7986 SoC
  clk: mediatek: add mt7986 clock IDs
  clk: mediatek: add mt7986 clock support
  pinctrl: mediatek: moore: check if pin_desc is valid before use
  dt-bindings: pinctrl: update bindings for MT7986 SoC
  pinctrl: mediatek: add support for MT7986 SoC
  dt-bindings: arm64: dts: mediatek: Add mt7986 series
  dt-bindings: rng: mediatek: add mt7986 to mtk rng binding
  dt-bindings: serial: Add compatible for Mediatek MT7986
  dt-bindings: watchdog: Add compatible for Mediatek MT7986
  arm64: dts: mediatek: add mt7986a support
  arm64: dts: mediatek: add mt7986b support

 .../devicetree/bindings/arm/mediatek.yaml     |    8 +
 .../arm/mediatek/mediatek,apmixedsys.txt      |    1 +
 .../bindings/arm/mediatek/mediatek,ethsys.txt |    1 +
 .../arm/mediatek/mediatek,infracfg.txt        |    1 +
 .../arm/mediatek/mediatek,sgmiisys.txt        |    2 +
 .../arm/mediatek/mediatek,topckgen.txt        |    1 +
 .../bindings/pinctrl/pinctrl-mt7622.txt       |  170 +++
 .../devicetree/bindings/rng/mtk-rng.yaml      |    1 +
 .../devicetree/bindings/serial/mtk-uart.txt   |    1 +
 .../devicetree/bindings/watchdog/mtk-wdt.txt  |    1 +
 arch/arm64/boot/dts/mediatek/Makefile         |    2 +
 arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts  |   49 +
 arch/arm64/boot/dts/mediatek/mt7986a.dtsi     |  227 +++
 arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts  |   21 +
 arch/arm64/boot/dts/mediatek/mt7986b.dtsi     |  236 ++++
 drivers/clk/mediatek/Kconfig                  |   17 +
 drivers/clk/mediatek/Makefile                 |    4 +
 drivers/clk/mediatek/clk-mt7986-apmixed.c     |   78 ++
 drivers/clk/mediatek/clk-mt7986-eth.c         |  132 ++
 drivers/clk/mediatek/clk-mt7986-infracfg.c    |  198 +++
 drivers/clk/mediatek/clk-mt7986-topckgen.c    |  319 +++++
 drivers/pinctrl/mediatek/Kconfig              |    7 +
 drivers/pinctrl/mediatek/Makefile             |    1 +
 drivers/pinctrl/mediatek/pinctrl-moore.c      |   18 +
 drivers/pinctrl/mediatek/pinctrl-mt7986.c     | 1217 +++++++++++++++++
 include/dt-bindings/clock/mt7986-clk.h        |  169 +++
 26 files changed, 2882 insertions(+)
 create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
 create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a.dtsi
 create mode 100644 arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
 create mode 100644 arch/arm64/boot/dts/mediatek/mt7986b.dtsi
 create mode 100644 drivers/clk/mediatek/clk-mt7986-apmixed.c
 create mode 100644 drivers/clk/mediatek/clk-mt7986-eth.c
 create mode 100644 drivers/clk/mediatek/clk-mt7986-infracfg.c
 create mode 100644 drivers/clk/mediatek/clk-mt7986-topckgen.c
 create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7986.c
 create mode 100644 include/dt-bindings/clock/mt7986-clk.h

-- 
2.29.2

[v2,04/12] pinctrl: mediatek: moore: check if pin_desc is valid before use

[Sam Shih]

Certain SoC are missing the middle part gpios in consecutive pins,
it's better to check if mtk_pin_desc is a valid pin for the extensibility

Signed-off-by: Sam Shih <sam.shih@mediatek.com>

---
v2: applied the comment suggested by reviewers:
    - for the pins not ballout, we can fill .name in struct mtk_pin_desc
      as NULL and return -ENOTSUPP in gpio/pinconf ops.

---
 drivers/pinctrl/mediatek/pinctrl-moore.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/drivers/pinctrl/mediatek/pinctrl-moore.c b/drivers/pinctrl/mediatek/pinctrl-moore.c
index 3a4a23c40a71..ad3b67163973 100644
--- a/drivers/pinctrl/mediatek/pinctrl-moore.c
+++ b/drivers/pinctrl/mediatek/pinctrl-moore.c
@@ -60,6 +60,8 @@ static int mtk_pinmux_set_mux(struct pinctrl_dev *pctldev,
 		int pin = grp->pins[i];
 
 		desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
+		if (!desc->name)
+			return -ENOTSUPP;
 
 		mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
 				 pin_modes[i]);
@@ -76,6 +78,8 @@ static int mtk_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
 	const struct mtk_pin_desc *desc;
 
 	desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
+	if (!desc->name)
+		return -ENOTSUPP;
 
 	return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
 				hw->soc->gpio_m);
@@ -89,6 +93,8 @@ static int mtk_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
 	const struct mtk_pin_desc *desc;
 
 	desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
+	if (!desc->name)
+		return -ENOTSUPP;
 
 	/* hardware would take 0 as input direction */
 	return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !input);
@@ -103,6 +109,8 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctldev,
 	const struct mtk_pin_desc *desc;
 
 	desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
+	if (!desc->name)
+		return -ENOTSUPP;
 
 	switch (param) {
 	case PIN_CONFIG_BIAS_DISABLE:
@@ -218,6 +226,8 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
 	int cfg, err = 0;
 
 	desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
+	if (!desc->name)
+		return -ENOTSUPP;
 
 	for (cfg = 0; cfg < num_configs; cfg++) {
 		param = pinconf_to_config_param(configs[cfg]);
@@ -435,6 +445,8 @@ static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio)
 	int value, err;
 
 	desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
+	if (!desc->name)
+		return -ENOTSUPP;
 
 	err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value);
 	if (err)
@@ -449,6 +461,10 @@ static void mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
 	const struct mtk_pin_desc *desc;
 
 	desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
+	if (!desc->name) {
+		dev_err(hw->dev, "Failed to set gpio %d\n", gpio);
+		return;
+	}
 
 	mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, !!value);
 }
@@ -490,6 +506,8 @@ static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
 	u32 debounce;
 
 	desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
+	if (!desc->name)
+		return -ENOTSUPP;
 
 	if (!hw->eint ||
 	    pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE ||
-- 
2.29.2