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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2bf239fdf0asm123199395ad.26.2026.06.02.00.29.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 02 Jun 2026 00:29:58 -0700 (PDT) Message-ID: <18235340-cd42-4d88-bfdb-19aecdd63d68@oss.qualcomm.com> Date: Tue, 2 Jun 2026 15:29:53 +0800 Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/4] soc: qcom: rpmh: Allow non-child devices to issue write commands To: Dmitry Baryshkov Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , David Collins , Subbaraman Narayanamurthy , Kamal Wadhwa , Maulik Shah , kernel@oss.qualcomm.com, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org References: <20260528-pinctrl-level-shifter-v2-0-3a6a025392bf@oss.qualcomm.com> <20260528-pinctrl-level-shifter-v2-1-3a6a025392bf@oss.qualcomm.com> <4ac5hjmr6divqs4myhcw5sveuboj265sw2jwslbivrfwh5e7ce@6d7ajvgikkgt> Content-Language: en-US From: Fenglin Wu In-Reply-To: <4ac5hjmr6divqs4myhcw5sveuboj265sw2jwslbivrfwh5e7ce@6d7ajvgikkgt> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjAyMDA2OCBTYWx0ZWRfX3rpBHwaFsUT8 xPzPmULHnvNWey4FZsbY3ZufzFVXvKbFRJ68+sLOitp5V+Dq9X8zqD+oObN9Qot9CIlcHAKhplG Ygr1m+5yKlbhqwNUned3piBFT0iYLRo0aB/plFkNOXRlkbiVAZrNo0quOIqK0IKp3xaTAx6wsBF J2QhSGvirJcRFUnCdUSqu/ezHwnxT/eomWNehkGa/upuMaaFq59RwOKKQiNXYMEvsubDknmR+EA SJXTXDH+kGfAYtB+IrlTBn2azp+xmN4nC2QJndfXYWb2l4bKwgdcjZEBvZNtNXuEFXZyTDLNHJC Pxdo9nEHtEwsqykci0sJwG8L6y6R37gZPnKlPMTRWXD48BtgGZY6Qkfgv1K6WLEZJWhUAFq1JQ0 qpr62YXkcLrfdCXBfbFBnrCMTdnJy8luUOn/xiI1htoX+McXBLhdCeQGGQR0ZpqAz8mj2IJMp17 +v0XUFjrM8OzNVvjlYw== X-Proofpoint-ORIG-GUID: tEjAzuJ2AXB_xD97TUsknT3dtVWzeyaN X-Proofpoint-GUID: tEjAzuJ2AXB_xD97TUsknT3dtVWzeyaN X-Authority-Analysis: v=2.4 cv=Rrv16imK c=1 sm=1 tr=0 ts=6a1e8677 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=1fo9jZtHFcPKizIzv_QA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-01_07,2026-05-28_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 lowpriorityscore=0 clxscore=1015 spamscore=0 suspectscore=0 impostorscore=0 phishscore=0 priorityscore=1501 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606020068 On 6/1/2026 9:37 PM, Dmitry Baryshkov wrote: > On Thu, May 28, 2026 at 06:05:35PM -0700, Fenglin Wu wrote: >> Currently, the RPMH driver only allows child devices of the RPMH >> controller to issue commands, as it assumes dev->parent points to the >> RSC device. >> >> There is a possibility that certain devices which are not children of >> the RPMH controller want to send commands for special control at the >> RPMH side. For example, in PMH0101 PMICs, there are bidirectional >> level shifter (LS) peripherals, and each LS works with a pair of PMIC >> GPIOs. The control of the LS, which is combined with the GPIO >> configuration, is handled by RPMH firmware for sharing the resource >> between different subsystems. From a hardware point of view, the LS >> functionality is tied to a pair of PMIC GPIOs, so its control is more >> suitable to be added in the pinctrl-spmi-gpio driver by adding the >> level-shifter function. However, the pinctrl-spmi-gpio device is a >> child device of the SPMI controller, not the RPMH controller. > This replicates the story of the PMIC regulators. There are two drivers, > one SPMI and one RPMh. Why don't we add a separate, RPMh-based GPIO > driver targeting only those paired GPIOs (and we don't even need to > represent them as a pair, it might be just one pin). Thanks for the suggestion. I agree that adding a separate, RPMh-based GPIO driver would be more straightforward from RPMh control perspective. It makes the new device as a child of the RSC device then it can naturally use the APIs for RPMh commands. The main challenge here is, we need to make the level-shifter mutually exclusive with other GPIO functions when the GPIO pairs are used in level-shifter function, which means we need to write SPMI commands to disable the associated GPIO modules. I am not sure if AOP already handles this; as far as I know, AOP only manages the BIDIR_LVL_SHIFTER module registers. Let me double check on this internally, if the GPIO modules could be controlled along with BIDIR_LVL_SHIFTER module registers at AOP side, and get back. Also, I would still insist on the pin group configuration, as the level-shifter would only work between 2 pins. Do you see any concerns if we represent the level-shifter as following even after move to a new driver? pmh0101-ls1-en { groups = "gpio11, gpio12"; function = "level-shifter"; qcom,1p2v-1p8v-ls-en = <1>; }; pmh0101-ls1-dis { groups = "gpio11, gpio12"; function = "level-shifter"; qcom,1p2v-1p8v-ls-en = <0>; };