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[86.58.12.163]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-439fe2273e8sm25569590f8f.33.2026.03.14.02.11.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 Mar 2026 02:11:58 -0700 (PDT) From: Jernej =?UTF-8?B?xaBrcmFiZWM=?= To: Icenowy Zheng , wens@kernel.org Cc: Andre Przywara , Linus Walleij , Samuel Holland , Bartosz Golaszewski , linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [RFC PATCH] pinctrl: sunxi: convert to GPIO_GENERIC Date: Sat, 14 Mar 2026 10:11:57 +0100 Message-ID: <1948361.tdWV9SEqCh@jernej-laptop> In-Reply-To: References: <20260313000652.11470-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Dne sobota, 14. marec 2026 ob 09:38:11 Srednjeevropski standardni =C4=8Das = je Chen-Yu Tsai napisal(a): > On Sat, Mar 14, 2026 at 1:14=E2=80=AFPM Icenowy Zheng wr= ote: > > > > =E5=9C=A8 2026-03-13=E4=BA=94=E7=9A=84 01:06 +0100=EF=BC=8CAndre Przywa= ra=E5=86=99=E9=81=93=EF=BC=9A > > > Allwinner SoCs combine pinmuxing and GPIO control in one device/MMIO > > > register frame. So far we were instantiating one GPIO chip per > > > pinctrl > > > device, which covers multiple banks of up to 32 GPIO pins per bank. > > > The > > > GPIO numbers were set to match the absolute pin numbers, even across > > > the > > > typically two instances of the pinctrl device. > > > > > > Convert the GPIO part of the sunxi pinctrl over to use the > > > gpio_generic > > > framework. This alone allows to remove some sunxi specific code, > > > which > > > is replaced with the existing generic code. This will become even > > > more > > > useful with the upcoming A733 support, which adds set and clear > > > registers for the output. > > > As a side effect this also changes the GPIO device and number > > > allocation: Each bank is now represented by its own gpio_chip, with > > > only > > > as many pins as there are actually implemented. The numbering is left > > > up > > > > Ah, is this a userspace API break? >=20 > Unfortunately, yes. This means the easily computable numbers that one can > use with the (deprecated) sysfs interface is gone, and also the pins are > now split amongst multiple gpiochip instances. I don't mind this at all for new SoCs, e.g. A733, but not really for already supported SoCs. >=20 > However if someone wanted the old "one gpiochip for one PIO instance with > evenly spaced banks" scheme, I suppose we could put together something > with the GPIO aggregator driver? It won't have same base pin number thoug= h. IIUC, this can be instantiated only via sysfs or configfs? Best regards, Jernej