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AJvYcCWgsRS/8TtnbG69xcXQB9vOxsfjDy21tW8LapzY314wE6eeWpSxfErtuJ/BkcwWiZsNITEvi4k7QFUY@vger.kernel.org X-Gm-Message-State: AOJu0YzIJGw88NQaS2z4LwC1ck0ABI3p6HuO/VI7vRx/1g/e885vFxcV 62DvLhnY3HmFMQdg4sZpAsQVqN9DjE2Yiikwi2P8YrwntZfgdl7ndX/weRz3TJY= X-Google-Smtp-Source: AGHT+IGmTYY7T/VcCziMPqVOTqADhj4JCoKKFv7vqIAcFy6bMnH/1xpzOaWZCQUfdpOfXaJpahrrrg== X-Received: by 2002:a05:6402:278f:b0:5c3:1089:ff23 with SMTP id 4fb4d7f45d1cf-5c91d6a03femr1195309a12.35.1728460851772; Wed, 09 Oct 2024 01:00:51 -0700 (PDT) Received: from [192.168.50.4] ([82.78.167.23]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5c8e05eb7f0sm5164321a12.72.2024.10.09.01.00.48 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 09 Oct 2024 01:00:50 -0700 (PDT) Message-ID: <1c3c8c5c-8f84-47c7-a9d0-963f95cba147@tuxon.dev> Date: Wed, 9 Oct 2024 11:00:48 +0300 Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/5] pinctrl: renesas: rzg2l: Remove RZG2L_TINT_IRQ_START_INDEX Content-Language: en-US To: Fabrizio Castro , Linus Walleij , Geert Uytterhoeven Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Chris Paterson , Biju Das , Lad Prabhakar References: <20240930145244.356565-1-fabrizio.castro.jz@renesas.com> <20240930145244.356565-2-fabrizio.castro.jz@renesas.com> From: claudiu beznea In-Reply-To: <20240930145244.356565-2-fabrizio.castro.jz@renesas.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 30.09.2024 17:52, Fabrizio Castro wrote: > The RZ/V2H(P) has 16 IRQ interrupts, while every other platforms > has 8, and this affects the start index of TINT interrupts > (1 + 16 = 17, rather than 1 + 8 = 9). > Macro RZG2L_TINT_IRQ_START_INDEX cannot work anymore, replace > it with a new member within struct rzg2l_hwcfg. > > Signed-off-by: Fabrizio Castro Tested-by: Claudiu Beznea > --- > v1->v2: > * No change > > drivers/pinctrl/renesas/pinctrl-rzg2l.c | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > > diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c > index 5a403915fed2..0aba75dce229 100644 > --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c > +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c > @@ -168,7 +168,6 @@ > #define RZG2L_PIN_ID_TO_PIN(id) ((id) % RZG2L_PINS_PER_PORT) > > #define RZG2L_TINT_MAX_INTERRUPT 32 > -#define RZG2L_TINT_IRQ_START_INDEX 9 > #define RZG2L_PACK_HWIRQ(t, i) (((t) << 16) | (i)) > > /* Custom pinconf parameters */ > @@ -251,6 +250,7 @@ enum rzg2l_iolh_index { > * @func_base: base number for port function (see register PFC) > * @oen_max_pin: the maximum pin number supporting output enable > * @oen_max_port: the maximum port number supporting output enable > + * @tint_start_index: the start index for the TINT interrupts > */ > struct rzg2l_hwcfg { > const struct rzg2l_register_offsets regs; > @@ -262,6 +262,7 @@ struct rzg2l_hwcfg { > u8 func_base; > u8 oen_max_pin; > u8 oen_max_port; > + unsigned int tint_start_index; Maybe you can use u16 (even u8 is enough at the moment) and add it a bit above (if u16 or even if unsigned int) to avoid any padding, if any. > }; > > struct rzg2l_dedicated_configs { > @@ -2379,7 +2380,7 @@ static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc, > > rzg2l_gpio_irq_endisable(pctrl, child, true); > pctrl->hwirq[irq] = child; > - irq += RZG2L_TINT_IRQ_START_INDEX; > + irq += pctrl->data->hwcfg->tint_start_index; > > /* All these interrupts are level high in the CPU */ > *parent_type = IRQ_TYPE_LEVEL_HIGH; > @@ -3035,6 +3036,7 @@ static const struct rzg2l_hwcfg rzg2l_hwcfg = { > }, > .iolh_groupb_oi = { 100, 66, 50, 33, }, > .oen_max_pin = 0, > + .tint_start_index = 9, > }; > > static const struct rzg2l_hwcfg rzg3s_hwcfg = { > @@ -3067,12 +3069,14 @@ static const struct rzg2l_hwcfg rzg3s_hwcfg = { > .func_base = 1, > .oen_max_pin = 1, /* Pin 1 of P0 and P7 is the maximum OEN pin. */ > .oen_max_port = 7, /* P7_1 is the maximum OEN port. */ > + .tint_start_index = 9, > }; > > static const struct rzg2l_hwcfg rzv2h_hwcfg = { > .regs = { > .pwpr = 0x3c04, > }, > + .tint_start_index = 17, > }; > > static struct rzg2l_pinctrl_data r9a07g043_data = {