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Thu, 14 May 2026 16:24:24 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ThreadId: A0acSZ0bucxw Date: Thu, 14 May 2026 22:23:25 +0200 From: "MINETTE Alexandre" To: "Konrad Dybcio" , "Bjorn Andersson" , "Konrad Dybcio" , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" , "MyungJoo Ham" , "Chanwoo Choi" , "Guru Das Srinagesh" , "Linus Walleij" , "Rob Clark" , "Joerg Roedel" , "Will Deacon" , "Robin Murphy" , "Kees Cook" , "Tony Luck" , "Guilherme G. Piccoli" Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, iommu@lists.linux.dev, phone-devel@vger.kernel.org Message-Id: <1eb77056-0716-49d3-b45f-d51ee5b70618@app.fastmail.com> In-Reply-To: References: <20260427-mainline-send-v1-sending-v2-0-dcaa9178007b@alex-min.fr> <20260427-mainline-send-v1-sending-v2-8-dcaa9178007b@alex-min.fr> <97969bf9-8eb2-4498-90bd-9973fb2bd638@oss.qualcomm.com> Subject: Re: [PATCH v2 8/8] ARM: dts: qcom: Add Samsung Galaxy S4 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Ah yes, I see. I tried GSBI for both the MUIC/extcon bus and the LED bus, but it does not work on my GT-I9505: USB does not enumerate with the MUIC on GSBI2, and the LED on GSBI3 times out when setting brightness (-110, = with no visble changes). So I think these should stay as i2c-gpio like downstream. --=20 MINETTE Alexandre contact@alex-min.fr Lun 04 mai 2026, =C3=A0 09:41, Konrad Dybcio a =C3=A9crit=E2=80=AF: > On 5/4/26 9:40 AM, Konrad Dybcio wrote: >> On 5/1/26 9:41 AM, MINETTE Alexandre wrote: >>> Thanks a lot for the suggestion, I checked the downstream board files >>> and it does not look like these buses are wired for GSBI. >>> >>> There, the MAX77693 bus is instantiated as a dedicated i2c-gpio bus = on >>> GPIO 22/23, and the AN30259A LED bus as a dedicated i2c-gpio bus on >>> GPIO 6/7. The native APQ8064 GSBI2/GSBI3 I2C pins are different >>> (GPIO 24/25 and GPIO 8/9), so these two buses do not seem to be wired >>> to the GSBI controllers on jflte. >>=20 >> What I meant is that the pins that the i2c-gpio nodes reference >> are actually wired (inside the SoC) to the GSBI I2C controllers. >>=20 >> You'll notice that in drivers/pinctrl/qcom/pinctrl-apq8064.c, >> there are bits like: >>=20 >> PINGROUP(6, gsbi3, NA, NA, NA, NA, NA, NA, NA, NA, NA), >>=20 >> which mean "function 0 is GPIO [implicitly in the macro], function >> 1 is mux to the GSBI controller" > > Unless you meant "these are indeed GSBI pins, but within that GSBIn > pingroup, those specific ones aren't assigned to SDA/SCL when > proto=3D=3DI2C, to which I'm afraid I won't be able to find docs for (= too > old) > > Konrad