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[77.252.46.238]) by smtp.gmail.com with ESMTPSA id b18-20020a05640202d200b0051dfa2e30b2sm5498533edx.9.2023.09.04.00.45.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 04 Sep 2023 00:45:56 -0700 (PDT) Message-ID: <1f0bf00f-07db-4017-a30b-618d90ce0457@linaro.org> Date: Mon, 4 Sep 2023 09:45:55 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.15.0 Subject: Re: [PATCH 2/2] pinctrl: qcom: lpass-lpi: allow slew rate bit in main pin config register Content-Language: en-US To: Konrad Dybcio , Andy Gross , Bjorn Andersson , Linus Walleij , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org References: <20230901090224.27770-1-krzysztof.kozlowski@linaro.org> <20230901090224.27770-3-krzysztof.kozlowski@linaro.org> <08a10dc1-bb8e-48b1-8d86-5ee513835196@linaro.org> From: Krzysztof Kozlowski In-Reply-To: <08a10dc1-bb8e-48b1-8d86-5ee513835196@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org On 01/09/2023 14:28, Konrad Dybcio wrote: > On 1.09.2023 11:02, Krzysztof Kozlowski wrote: >> Existing Qualcomm SoCs have the LPASS pin controller slew rate control >> in separate register, however this will change with upcoming Qualcomm >> SoCs. The slew rate will be part of the main register for pin >> configuration, thus second device IO address space is not needed. >> >> Prepare for supporting new SoCs by adding flag customizing the driver >> behavior for slew rate. >> >> Signed-off-by: Krzysztof Kozlowski >> --- >> drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 20 ++++++++++++++------ >> drivers/pinctrl/qcom/pinctrl-lpass-lpi.h | 7 +++++++ >> 2 files changed, 21 insertions(+), 6 deletions(-) >> >> diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c >> index e2df2193a802..40eb58a3a8cd 100644 >> --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c >> +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c >> @@ -190,6 +190,7 @@ static int lpi_config_set_slew_rate(struct lpi_pinctrl *pctrl, >> const struct lpi_pingroup *g, >> unsigned int group, unsigned int slew) >> { >> + void __iomem *reg; > Aaalmost reverse-Christmas-tree! I can fix it. > >> unsigned long sval; >> int slew_offset; >> >> @@ -203,12 +204,17 @@ static int lpi_config_set_slew_rate(struct lpi_pinctrl *pctrl, >> if (slew_offset == LPI_NO_SLEW) >> return 0; >> >> + if (pctrl->data->flags & LPI_FLAG_SLEW_RATE_SAME_REG) >> + reg = pctrl->tlmm_base + LPI_TLMM_REG_OFFSET * group + LPI_GPIO_CFG_REG; >> + else >> + reg = pctrl->slew_base + LPI_SLEW_RATE_CTL_REG; > Perhaps lpi_gpio_read/write could be used here? > > I guess both ways work though I was thinking about this, but decided not to in favor of duplicating "tlmm_base + offset * group ....". It would not make the code easier to read. Best regards, Krzysztof