* [PATCH 1/2] pinctrl: qcom: lpass-lpi: split slew rate set to separate function
2023-09-01 9:02 [PATCH 0/2] pinctrl: qcom: lpass-lpi: allow slew rate bit in main pin config register Krzysztof Kozlowski
@ 2023-09-01 9:02 ` Krzysztof Kozlowski
2023-09-01 9:02 ` [PATCH 2/2] pinctrl: qcom: lpass-lpi: allow slew rate bit in main pin config register Krzysztof Kozlowski
1 sibling, 0 replies; 5+ messages in thread
From: Krzysztof Kozlowski @ 2023-09-01 9:02 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Linus Walleij,
linux-arm-msm, linux-gpio, linux-kernel
Cc: Krzysztof Kozlowski
Setting slew rate for each pin will grow with upcoming Qualcomm SoCs,
so split the code responsible for this into separate function for easier
readability and maintenance.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 53 +++++++++++++++---------
1 file changed, 33 insertions(+), 20 deletions(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
index 0b2839d27fd6..e2df2193a802 100644
--- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
+++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
@@ -186,6 +186,35 @@ static int lpi_config_get(struct pinctrl_dev *pctldev,
return 0;
}
+static int lpi_config_set_slew_rate(struct lpi_pinctrl *pctrl,
+ const struct lpi_pingroup *g,
+ unsigned int group, unsigned int slew)
+{
+ unsigned long sval;
+ int slew_offset;
+
+ if (slew > LPI_SLEW_RATE_MAX) {
+ dev_err(pctrl->dev, "invalid slew rate %u for pin: %d\n",
+ slew, group);
+ return -EINVAL;
+ }
+
+ slew_offset = g->slew_offset;
+ if (slew_offset == LPI_NO_SLEW)
+ return 0;
+
+ mutex_lock(&pctrl->lock);
+
+ sval = ioread32(pctrl->slew_base + LPI_SLEW_RATE_CTL_REG);
+ sval &= ~(LPI_SLEW_RATE_MASK << slew_offset);
+ sval |= slew << slew_offset;
+ iowrite32(sval, pctrl->slew_base + LPI_SLEW_RATE_CTL_REG);
+
+ mutex_unlock(&pctrl->lock);
+
+ return 0;
+}
+
static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group,
unsigned long *configs, unsigned int nconfs)
{
@@ -193,8 +222,7 @@ static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group,
unsigned int param, arg, pullup = LPI_GPIO_BIAS_DISABLE, strength = 2;
bool value, output_enabled = false;
const struct lpi_pingroup *g;
- unsigned long sval;
- int i, slew_offset;
+ int i, ret;
u32 val;
g = &pctrl->data->groups[group];
@@ -226,24 +254,9 @@ static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group,
strength = arg;
break;
case PIN_CONFIG_SLEW_RATE:
- if (arg > LPI_SLEW_RATE_MAX) {
- dev_err(pctldev->dev, "invalid slew rate %u for pin: %d\n",
- arg, group);
- return -EINVAL;
- }
-
- slew_offset = g->slew_offset;
- if (slew_offset == LPI_NO_SLEW)
- break;
-
- mutex_lock(&pctrl->lock);
-
- sval = ioread32(pctrl->slew_base + LPI_SLEW_RATE_CTL_REG);
- sval &= ~(LPI_SLEW_RATE_MASK << slew_offset);
- sval |= arg << slew_offset;
- iowrite32(sval, pctrl->slew_base + LPI_SLEW_RATE_CTL_REG);
-
- mutex_unlock(&pctrl->lock);
+ ret = lpi_config_set_slew_rate(pctrl, g, group, arg);
+ if (ret)
+ return ret;
break;
default:
return -EINVAL;
--
2.34.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 2/2] pinctrl: qcom: lpass-lpi: allow slew rate bit in main pin config register
2023-09-01 9:02 [PATCH 0/2] pinctrl: qcom: lpass-lpi: allow slew rate bit in main pin config register Krzysztof Kozlowski
2023-09-01 9:02 ` [PATCH 1/2] pinctrl: qcom: lpass-lpi: split slew rate set to separate function Krzysztof Kozlowski
@ 2023-09-01 9:02 ` Krzysztof Kozlowski
2023-09-01 12:28 ` Konrad Dybcio
1 sibling, 1 reply; 5+ messages in thread
From: Krzysztof Kozlowski @ 2023-09-01 9:02 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Linus Walleij,
linux-arm-msm, linux-gpio, linux-kernel
Cc: Krzysztof Kozlowski
Existing Qualcomm SoCs have the LPASS pin controller slew rate control
in separate register, however this will change with upcoming Qualcomm
SoCs. The slew rate will be part of the main register for pin
configuration, thus second device IO address space is not needed.
Prepare for supporting new SoCs by adding flag customizing the driver
behavior for slew rate.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 20 ++++++++++++++------
drivers/pinctrl/qcom/pinctrl-lpass-lpi.h | 7 +++++++
2 files changed, 21 insertions(+), 6 deletions(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
index e2df2193a802..40eb58a3a8cd 100644
--- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
+++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
@@ -190,6 +190,7 @@ static int lpi_config_set_slew_rate(struct lpi_pinctrl *pctrl,
const struct lpi_pingroup *g,
unsigned int group, unsigned int slew)
{
+ void __iomem *reg;
unsigned long sval;
int slew_offset;
@@ -203,12 +204,17 @@ static int lpi_config_set_slew_rate(struct lpi_pinctrl *pctrl,
if (slew_offset == LPI_NO_SLEW)
return 0;
+ if (pctrl->data->flags & LPI_FLAG_SLEW_RATE_SAME_REG)
+ reg = pctrl->tlmm_base + LPI_TLMM_REG_OFFSET * group + LPI_GPIO_CFG_REG;
+ else
+ reg = pctrl->slew_base + LPI_SLEW_RATE_CTL_REG;
+
mutex_lock(&pctrl->lock);
- sval = ioread32(pctrl->slew_base + LPI_SLEW_RATE_CTL_REG);
+ sval = ioread32(reg);
sval &= ~(LPI_SLEW_RATE_MASK << slew_offset);
sval |= slew << slew_offset;
- iowrite32(sval, pctrl->slew_base + LPI_SLEW_RATE_CTL_REG);
+ iowrite32(sval, reg);
mutex_unlock(&pctrl->lock);
@@ -452,10 +458,12 @@ int lpi_pinctrl_probe(struct platform_device *pdev)
return dev_err_probe(dev, PTR_ERR(pctrl->tlmm_base),
"TLMM resource not provided\n");
- pctrl->slew_base = devm_platform_ioremap_resource(pdev, 1);
- if (IS_ERR(pctrl->slew_base))
- return dev_err_probe(dev, PTR_ERR(pctrl->slew_base),
- "Slew resource not provided\n");
+ if (!(data->flags & LPI_FLAG_SLEW_RATE_SAME_REG)) {
+ pctrl->slew_base = devm_platform_ioremap_resource(pdev, 1);
+ if (IS_ERR(pctrl->slew_base))
+ return dev_err_probe(dev, PTR_ERR(pctrl->slew_base),
+ "Slew resource not provided\n");
+ }
ret = devm_clk_bulk_get_optional(dev, MAX_LPI_NUM_CLKS, pctrl->clks);
if (ret)
diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
index 29047bb80bb8..8a4cd8aef38c 100644
--- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
+++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h
@@ -60,6 +60,12 @@ struct pinctrl_pin_desc;
.nfuncs = 5, \
}
+/*
+ * Slew rate control is done in the same register as rest of the
+ * pin configuration.
+ */
+#define LPI_FLAG_SLEW_RATE_SAME_REG BIT(0)
+
struct lpi_pingroup {
struct group_desc group;
unsigned int pin;
@@ -82,6 +88,7 @@ struct lpi_pinctrl_variant_data {
int ngroups;
const struct lpi_function *functions;
int nfunctions;
+ unsigned int flags;
};
int lpi_pinctrl_probe(struct platform_device *pdev);
--
2.34.1
^ permalink raw reply related [flat|nested] 5+ messages in thread