From: Mika Westerberg <mika.westerberg@linux.intel.com>
To: "Zhu, Lejun" <lejun.zhu@linux.intel.com>
Cc: linus.walleij@linaro.org, gnurou@gmail.com,
linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org,
bin.yang@intel.com
Subject: Re: [PATCH] gpio: Add support for Intel SoC PMIC (Crystal Cove)
Date: Tue, 20 May 2014 11:30:46 +0300 [thread overview]
Message-ID: <20140520083046.GD1651@lahna.fi.intel.com> (raw)
In-Reply-To: <20140519103933.GK2067@lahna.fi.intel.com>
On Mon, May 19, 2014 at 01:39:33PM +0300, Mika Westerberg wrote:
> On Wed, May 14, 2014 at 11:44:07PM +0800, Zhu, Lejun wrote:
> > Devices based on Intel SoC products such as Baytrail have a Power
> > Management IC. In the PMIC there are subsystems for voltage regulation,
> > A/D conversion, GPIO and PWMs. The PMIC in Baytrail-T platform is called
> > Crystal Cove.
> >
> > This patch adds support for the GPIO function in Crystal Cove.
>
> I have few comments as well in addition to comments from Linus and
> Alexandre.
One more thing, I just remembered. The crystal cove GPIO driver is
supposed to provide ACPI Operation Regions to the ASL code so you need
to make sure you have ACPI handle associated with the device before you
register your driver to the GPIO core.
next prev parent reply other threads:[~2014-05-20 8:30 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-05-14 15:44 [PATCH] gpio: Add support for Intel SoC PMIC (Crystal Cove) Zhu, Lejun
2014-05-16 17:33 ` Linus Walleij
2014-05-19 0:27 ` Zhu, Lejun
2014-05-19 14:13 ` Mathias Nyman
2014-05-20 9:16 ` Zhu, Lejun
2014-05-16 17:46 ` Daniel Glöckner
2014-05-19 1:46 ` Zhu, Lejun
2014-05-17 14:37 ` [PATCH] " Alexandre Courbot
2014-05-19 0:28 ` Zhu, Lejun
2014-05-27 9:01 ` Linus Walleij
2014-05-19 10:39 ` Mika Westerberg
2014-05-20 8:30 ` Mika Westerberg [this message]
2014-05-20 9:15 ` Zhu, Lejun
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