From: Mika Westerberg <mika.westerberg@linux.intel.com>
To: Aaron Lu <aaron.lu@intel.com>
Cc: "Linus Walleij" <linus.walleij@linaro.org>,
"Alexandre Courbot" <gnurou@gmail.com>,
"Samuel Ortiz" <sameo@linux.intel.com>,
"Lee Jones" <lee.jones@linaro.org>,
"Arnd Bergmann" <arnd@arndb.de>,
"linux-gpio@vger.kernel.org" <linux-gpio@vger.kernel.org>,
"linux-arch@vger.kernel.org" <linux-arch@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"Jacob Pan" <jacob.jun.pan@linux.intel.com>,
"Lejun Zhu" <lejun.zhu@intel.com>,
"Radivoje Jovanovic" <radivoje.jovanovic@intel.com>,
"Daniel Glöckner" <dg@emlix.com>,
"ACPI Devel Maling List" <linux-acpi@vger.kernel.org>,
"Rafael J. Wysocki" <rjw@rjwysocki.net>
Subject: Re: [PATCH v2 1/2] gpio / CrystalCove: support virtual GPIO
Date: Thu, 25 Sep 2014 14:15:55 +0300 [thread overview]
Message-ID: <20140925111555.GG1786@lahna.fi.intel.com> (raw)
In-Reply-To: <54238496.70505@intel.com>
On Thu, Sep 25, 2014 at 10:57:26AM +0800, Aaron Lu wrote:
> The virtual GPIO introduced in ACPI table of Baytrail-T based system is
> used to solve a problem under Windows. We do not have such problems
> under Linux so we do not actually need them. But we have to tell GPIO
> library that the Crystal Cove GPIO chip has this many GPIO pins or the
> common GPIO handler will refuse any access to those high number GPIO
> pins, which will resulted in a failure evaluation of every ACPI control
> method that is used to turn on/off power resource and/or report sensor
> temperatures.
>
> Signed-off-by: Aaron Lu <aaron.lu@intel.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
A minor nit, see below:
> ---
> v2: remove the hunk to increase NR_GPIO to 512.
>
> drivers/gpio/gpio-crystalcove.c | 19 ++++++++++++++++---
> 1 file changed, 16 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpio/gpio-crystalcove.c b/drivers/gpio/gpio-crystalcove.c
> index e3712f0e51ab..186b76ef71a1 100644
> --- a/drivers/gpio/gpio-crystalcove.c
> +++ b/drivers/gpio/gpio-crystalcove.c
> @@ -24,6 +24,7 @@
> #include <linux/mfd/intel_soc_pmic.h>
>
> #define CRYSTALCOVE_GPIO_NUM 16
> +#define CRYSTALCOVE_VGPIO_NUM 0x5e
I would rather see this spelled in decimal base.
next prev parent reply other threads:[~2014-09-25 11:15 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-09-09 2:32 [PATCH 0/2] Support CrystalCove PMIC ACPI operation region Aaron Lu
2014-09-09 2:32 ` [PATCH 1/2] gpio / CrystalCove: support virtual GPIO Aaron Lu
2014-09-23 10:13 ` Linus Walleij
2014-09-24 11:18 ` Linus Walleij
2014-09-25 2:57 ` [PATCH v2 " Aaron Lu
2014-09-25 11:15 ` Mika Westerberg [this message]
2014-09-26 5:21 ` Aaron Lu
2014-09-25 13:16 ` Linus Walleij
2014-09-26 5:22 ` Aaron Lu
2014-09-09 2:32 ` [PATCH 2/2] PMIC / opregion: support PMIC customized operation region for CrystalCove Aaron Lu
2014-10-08 8:05 ` Lee Jones
2014-10-08 9:16 ` Linus Walleij
2014-10-08 11:58 ` Jacob Pan
2014-10-08 12:54 ` Mark Brown
2014-10-09 9:21 ` Aaron Lu
2014-10-13 9:02 ` Aaron Lu
2014-10-13 14:51 ` Rafael J. Wysocki
2014-09-09 2:37 ` [PATCH 0/2] Support CrystalCove PMIC ACPI operation region Aaron Lu
2014-09-15 2:57 ` Aaron Lu
2014-09-15 22:43 ` Lee Jones
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