[PATCH v2 0/5] pinctrl: sunxi: Add H3 R_PIO controller support

[PATCH v2 0/5] pinctrl: sunxi: Add H3 R_PIO controller support

[Krzysztof Adamski]

This patch series is extension of my original single patch with the
same subject. It adds support for R_PIO so that GPIO port L can be
used in H3 based devices. It was tested on OrangePi PC where PL is
connected amount others to an onboard led, a switch and IR receiver and
some VCC controllers.

Patchset was based on next-20160129.

--- 

Changes since v1:
- splited patch to two separate - dtsi and c files
- added APB0 clocks a parent for R_PIO
- added fix in sunxi_pinctrl_gpio_get for getting pin value when in irq
  mode and on 2nd pinctrl
- fixed a "pwn" > "pwm" typo
- fixed order in allwinner,sunxi-pinctrl.txt


Krzysztof Adamski (5):
  clk: sunxi: Add apb0 gates for H3
  dts: sun8i-h3: Add APB0 related clocks and resets
  pinctrl: sunxi: Add H3 R_PIO controller support
  ARM: dts: sun8i-h3: Add R_PIO controller node to the dtsi
  pinctrl: sunxi: Use pin number when calling sunxi_pmx_set

 Documentation/devicetree/bindings/clock/sunxi.txt  |   1 +
 .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt   |   1 +
 arch/arm/boot/dts/sun8i-h3.dtsi                    |  44 +++++++++
 drivers/clk/sunxi/clk-simple-gates.c               |   2 +
 drivers/pinctrl/sunxi/Kconfig                      |   4 +
 drivers/pinctrl/sunxi/Makefile                     |   1 +
 drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c         | 106 +++++++++++++++++++++
 drivers/pinctrl/sunxi/pinctrl-sunxi.c              |   9 +-
 8 files changed, 165 insertions(+), 3 deletions(-)
 create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c

-- 
2.1.4

[PATCH v2 1/5] clk: sunxi: Add apb0 gates for H3

[Krzysztof Adamski]

This patch adds support for APB0 in H3. It seems to be compatible with
earlier SOCs. apb0 gates controls R_ block peripherals (R_PIO, R_IR,
etc).

Signed-off-by: Krzysztof Adamski <k@japko.eu>
---
 Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
 drivers/clk/sunxi/clk-simple-gates.c              | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index e59f57b..6ee6875 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -32,6 +32,7 @@ Required properties:
 	"allwinner,sun8i-h3-ahb2-clk" - for the AHB2 clock on H3
 	"allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
 	"allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
+	"allwinner,sun8i-h3-abp0-gates-clk" - for the APB0 gates on H3
 	"allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80
 	"allwinner,sun9i-a80-ahb1-gates-clk" - for the AHB1 gates on A80
 	"allwinner,sun9i-a80-ahb2-gates-clk" - for the AHB2 gates on A80
diff --git a/drivers/clk/sunxi/clk-simple-gates.c b/drivers/clk/sunxi/clk-simple-gates.c
index f4da52b..8a1fa3e 100644
--- a/drivers/clk/sunxi/clk-simple-gates.c
+++ b/drivers/clk/sunxi/clk-simple-gates.c
@@ -130,6 +130,8 @@ CLK_OF_DECLARE(sun8i_a23_apb2, "allwinner,sun8i-a23-apb2-gates-clk",
 	       sunxi_simple_gates_init);
 CLK_OF_DECLARE(sun8i_a33_ahb1, "allwinner,sun8i-a33-ahb1-gates-clk",
 	       sunxi_simple_gates_init);
+CLK_OF_DECLARE(sun8i_h3_abp0, "allwinner,sun8i-h3-abp0-gates-clk",
+	       sunxi_simple_gates_init);
 CLK_OF_DECLARE(sun9i_a80_ahb0, "allwinner,sun9i-a80-ahb0-gates-clk",
 	       sunxi_simple_gates_init);
 CLK_OF_DECLARE(sun9i_a80_ahb1, "allwinner,sun9i-a80-ahb1-gates-clk",
-- 
2.1.4

Re: [PATCH v2 1/5] clk: sunxi: Add apb0 gates for H3

[Chen-Yu Tsai]

On Wed, Feb 3, 2016 at 5:21 AM, Krzysztof Adamski <k@japko.eu> wrote:
> This patch adds support for APB0 in H3. It seems to be compatible with
> earlier SOCs. apb0 gates controls R_ block peripherals (R_PIO, R_IR,
> etc).
>
> Signed-off-by: Krzysztof Adamski <k@japko.eu>
> ---
>  Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
>  drivers/clk/sunxi/clk-simple-gates.c              | 2 ++
>  2 files changed, 3 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
> index e59f57b..6ee6875 100644
> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
> @@ -32,6 +32,7 @@ Required properties:
>         "allwinner,sun8i-h3-ahb2-clk" - for the AHB2 clock on H3
>         "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
>         "allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
> +       "allwinner,sun8i-h3-abp0-gates-clk" - for the APB0 gates on H3

The list is grouped by clock type (AHB/APB/...) then family then SoC.
Please put this in the apb0 section below.

ChenYu

>         "allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80
>         "allwinner,sun9i-a80-ahb1-gates-clk" - for the AHB1 gates on A80
>         "allwinner,sun9i-a80-ahb2-gates-clk" - for the AHB2 gates on A80
> diff --git a/drivers/clk/sunxi/clk-simple-gates.c b/drivers/clk/sunxi/clk-simple-gates.c
> index f4da52b..8a1fa3e 100644
> --- a/drivers/clk/sunxi/clk-simple-gates.c
> +++ b/drivers/clk/sunxi/clk-simple-gates.c
> @@ -130,6 +130,8 @@ CLK_OF_DECLARE(sun8i_a23_apb2, "allwinner,sun8i-a23-apb2-gates-clk",
>                sunxi_simple_gates_init);
>  CLK_OF_DECLARE(sun8i_a33_ahb1, "allwinner,sun8i-a33-ahb1-gates-clk",
>                sunxi_simple_gates_init);
> +CLK_OF_DECLARE(sun8i_h3_abp0, "allwinner,sun8i-h3-abp0-gates-clk",
> +              sunxi_simple_gates_init);
>  CLK_OF_DECLARE(sun9i_a80_ahb0, "allwinner,sun9i-a80-ahb0-gates-clk",
>                sunxi_simple_gates_init);
>  CLK_OF_DECLARE(sun9i_a80_ahb1, "allwinner,sun9i-a80-ahb1-gates-clk",
> --
> 2.1.4
>

[PATCH v2 3/5] pinctrl: sunxi: Add H3 R_PIO controller support

[Krzysztof Adamski]

H3 has additional PIO controller similar to what we can find on A23.
It's a 12 pin port, described in H3 Datasheet rev 1.1, pages 345-350.

Signed-off-by: Krzysztof Adamski <k@japko.eu>
---
 drivers/pinctrl/sunxi/Kconfig              |   4 ++
 drivers/pinctrl/sunxi/Makefile             |   1 +
 drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c | 106 +++++++++++++++++++++++++++++
 3 files changed, 111 insertions(+)
 create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c

diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index f8dbc8b..75a26c9 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -55,6 +55,10 @@ config PINCTRL_SUN8I_H3
 	def_bool MACH_SUN8I
 	select PINCTRL_SUNXI_COMMON
 
+config PINCTRL_SUN8I_H3_R
+	def_bool MACH_SUN8I
+	select PINCTRL_SUNXI_COMMON
+
 config PINCTRL_SUN9I_A80
 	def_bool MACH_SUN9I
 	select PINCTRL_SUNXI_COMMON
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index ef82f22..a5d56f1 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -14,5 +14,6 @@ obj-$(CONFIG_PINCTRL_SUN8I_A23_R)	+= pinctrl-sun8i-a23-r.o
 obj-$(CONFIG_PINCTRL_SUN8I_A33)		+= pinctrl-sun8i-a33.o
 obj-$(CONFIG_PINCTRL_SUN8I_A83T)	+= pinctrl-sun8i-a83t.o
 obj-$(CONFIG_PINCTRL_SUN8I_H3)		+= pinctrl-sun8i-h3.o
+obj-$(CONFIG_PINCTRL_SUN8I_H3_R)	+= pinctrl-sun8i-h3-r.o
 obj-$(CONFIG_PINCTRL_SUN9I_A80)		+= pinctrl-sun9i-a80.o
 obj-$(CONFIG_PINCTRL_SUN9I_A80_R)	+= pinctrl-sun9i-a80-r.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c
new file mode 100644
index 0000000..686ec21
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c
@@ -0,0 +1,106 @@
+/*
+ * Allwinner H3 SoCs pinctrl driver.
+ *
+ * Copyright (C) 2016 Krzysztof Adamski <k@japko.eu>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-sunxi.h"
+
+static const struct sunxi_desc_pin sun8i_h3_r_pins[] = {
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_twi"),         /* SCK */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),	/* PL_EINT0 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_twi"),         /* SDA */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),	/* PL_EINT1 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_uart"),        /* TX */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),	/* PL_EINT2 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_uart"),        /* RX */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),	/* PL_EINT3 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_jtag"),        /* MS */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),	/* PL_EINT4 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_jtag"),        /* CK */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),	/* PL_EINT5 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_jtag"),        /* DO */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),	/* PL_EINT6 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_jtag"),        /* DI */
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),	/* PL_EINT7 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),	/* PL_EINT8 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),	/* PL_EINT9 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_pwm"),
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)),	/* PL_EINT10 */
+	SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 11),
+		  SUNXI_FUNCTION(0x0, "gpio_in"),
+		  SUNXI_FUNCTION(0x1, "gpio_out"),
+		  SUNXI_FUNCTION(0x2, "s_cir_rx"),
+		  SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)),	/* PL_EINT11 */
+};
+
+static const struct sunxi_pinctrl_desc sun8i_h3_r_pinctrl_data = {
+	.pins = sun8i_h3_r_pins,
+	.npins = ARRAY_SIZE(sun8i_h3_r_pins),
+	.irq_banks = 1,
+	.pin_base = PL_BASE,
+	.irq_read_needs_mux = true
+};
+
+static int sun8i_h3_r_pinctrl_probe(struct platform_device *pdev)
+{
+	return sunxi_pinctrl_init(pdev,
+				  &sun8i_h3_r_pinctrl_data);
+}
+
+static const struct of_device_id sun8i_h3_r_pinctrl_match[] = {
+	{ .compatible = "allwinner,sun8i-h3-r-pinctrl", },
+	{}
+};
+
+static struct platform_driver sun8i_h3_r_pinctrl_driver = {
+	.probe	= sun8i_h3_r_pinctrl_probe,
+	.driver	= {
+		.name		= "sun8i-h3-r-pinctrl",
+		.of_match_table	= sun8i_h3_r_pinctrl_match,
+	},
+};
+builtin_platform_driver(sun8i_h3_r_pinctrl_driver);
-- 
2.1.4

Re: [PATCH v2 3/5] pinctrl: sunxi: Add H3 R_PIO controller support

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 475 bytes --]

On Tue, Feb 02, 2016 at 10:21:51PM +0100, Krzysztof Adamski wrote:
> H3 has additional PIO controller similar to what we can find on A23.
> It's a 12 pin port, described in H3 Datasheet rev 1.1, pages 345-350.
> 
> Signed-off-by: Krzysztof Adamski <k@japko.eu>

Acked-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

Re: [PATCH v2 3/5] pinctrl: sunxi: Add H3 R_PIO controller support

[Linus Walleij]

On Tue, Feb 2, 2016 at 10:21 PM, Krzysztof Adamski <k@japko.eu> wrote:

> H3 has additional PIO controller similar to what we can find on A23.
> It's a 12 pin port, described in H3 Datasheet rev 1.1, pages 345-350.
>
> Signed-off-by: Krzysztof Adamski <k@japko.eu>

Patch applied with Maxime's ACK.

Yours,
Linus Walleij

Re: [linux-sunxi] Re: [PATCH v2 3/5] pinctrl: sunxi: Add H3 R_PIO controller support

[Krzysztof Adamski]

On Thu, Feb 11, 2016 at 02:21:15PM +0100, Linus Walleij wrote:
>On Tue, Feb 2, 2016 at 10:21 PM, Krzysztof Adamski <k@japko.eu> wrote:
>
>> H3 has additional PIO controller similar to what we can find on A23.
>> It's a 12 pin port, described in H3 Datasheet rev 1.1, pages 345-350.
>>
>> Signed-off-by: Krzysztof Adamski <k@japko.eu>
>
>Patch applied with Maxime's ACK.

Hi Linus,

You took v2 which does not add documentation for 
allwinner,sun8i-h3-r-pinctrl compatible that is added in this patch.  
This was fixed in v3. Should I prepare a patch for you that only adds 
this to the documentation or you can handle this by taking v3/v4 instead 
of this patch?

Best regards,
Krzysztof Adamski

Re: Re: [PATCH v2 3/5] pinctrl: sunxi: Add H3 R_PIO controller support

[Linus Walleij]

On Mon, Feb 15, 2016 at 9:08 AM, Krzysztof Adamski <k@japko.eu> wrote:
> On Thu, Feb 11, 2016 at 02:21:15PM +0100, Linus Walleij wrote:
>>
>> On Tue, Feb 2, 2016 at 10:21 PM, Krzysztof Adamski <k@japko.eu> wrote:
>>
>>> H3 has additional PIO controller similar to what we can find on A23.
>>> It's a 12 pin port, described in H3 Datasheet rev 1.1, pages 345-350.
>>>
>>> Signed-off-by: Krzysztof Adamski <k@japko.eu>
>>
>>
>> Patch applied with Maxime's ACK.
>
>
> Hi Linus,
>
> You took v2 which does not add documentation for
> allwinner,sun8i-h3-r-pinctrl compatible that is added in this patch.  This
> was fixed in v3. Should I prepare a patch for you that only adds this to the
> documentation or you can handle this by taking v3/v4 instead of this patch?

Ooops please send a fixup patch, I don't like to rebase the
tree if possible. Sorry for the mess and thanks for your help.

Yours,
Linus Walleij

[PATCH] clk: sunxi: Add missing H3 apb0 clock documentation

[Krzysztof Adamski]

allwinner,sun8i-h3-apb0-gates-clk was added by
commit ba83a11104ae ("pinctrl: sunxi: Add H3 R_PIO controller support")
but the patch was missing proper binding documentation. This patch fixes
this issue.

Signed-off-by: Krzysztof Adamski <k@japko.eu>
---
 Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index c09f59b..37d0fd6 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -38,6 +38,7 @@ Required properties:
 	"allwinner,sun4i-a10-apb0-clk" - for the APB0 clock
 	"allwinner,sun6i-a31-apb0-clk" - for the APB0 clock on A31
 	"allwinner,sun8i-a23-apb0-clk" - for the APB0 clock on A23
+	"allwinner,sun8i-h3-apb0-gates-clk" - for the APB0 gates on H3
 	"allwinner,sun9i-a80-apb0-clk" - for the APB0 bus clock on A80
 	"allwinner,sun8i-a83t-apb0-gates-clk" - for the APB0 gates on A83T
 	"allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10
-- 
2.1.4

Re: [PATCH] clk: sunxi: Add missing H3 apb0 clock documentation

[Chen-Yu Tsai]

On Thu, Feb 18, 2016 at 7:03 AM, Krzysztof Adamski
<krzysztof.adamski-++hxYGjEMp0AvxtiuMwx3w@public.gmane.org> wrote:
> allwinner,sun8i-h3-apb0-gates-clk was added by
> commit ba83a11104ae ("pinctrl: sunxi: Add H3 R_PIO controller support")
> but the patch was missing proper binding documentation. This patch fixes
> this issue.

What are you talking about? The commit you mentioned only adds the pinctrl
driver. Your H3 PRCM related clock and reset patches are still pending.
No need for this patch as your earlier patches includes this.

ChenYu

>
> Signed-off-by: Krzysztof Adamski <k@japko.eu>
> ---
>  Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
> index c09f59b..37d0fd6 100644
> --- a/Documentation/devicetree/bindings/clock/sunxi.txt
> +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
> @@ -38,6 +38,7 @@ Required properties:
>         "allwinner,sun4i-a10-apb0-clk" - for the APB0 clock
>         "allwinner,sun6i-a31-apb0-clk" - for the APB0 clock on A31
>         "allwinner,sun8i-a23-apb0-clk" - for the APB0 clock on A23
> +       "allwinner,sun8i-h3-apb0-gates-clk" - for the APB0 gates on H3
>         "allwinner,sun9i-a80-apb0-clk" - for the APB0 bus clock on A80
>         "allwinner,sun8i-a83t-apb0-gates-clk" - for the APB0 gates on A83T
>         "allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10
> --
> 2.1.4
>

Re: [linux-sunxi] Re: [PATCH] clk: sunxi: Add missing H3 apb0 clock documentation

[Krzysztof Adamski]

On Thu, Feb 18, 2016 at 09:07:16AM -0800, Chen-Yu Tsai wrote:
>On Thu, Feb 18, 2016 at 7:03 AM, Krzysztof Adamski
><krzysztof.adamski@tieto.com> wrote:
>> allwinner,sun8i-h3-apb0-gates-clk was added by
>> commit ba83a11104ae ("pinctrl: sunxi: Add H3 R_PIO controller support")
>> but the patch was missing proper binding documentation. This patch fixes
>> this issue.
>
>What are you talking about? The commit you mentioned only adds the pinctrl
>driver. Your H3 PRCM related clock and reset patches are still pending.
>No need for this patch as your earlier patches includes this.

Damn, I messed up patches, I must have been tired or something. It was 
documentation for "allwinner,sun8i-h3-r-pinctrl" that was missing. I'm 
sending a new patch. Sorry for confusion.

Best regards,
Krzysztof Adamski

[PATCH] pinctrl: sunxi: Add missing H3 R_PIO binding documentation

[Krzysztof Adamski]

allwinner,sun8i-h3-r-pinctrl was added by
commit ba83a11104ae ("pinctrl: sunxi: Add H3 R_PIO controller support")
but the patch was missing proper binding documentation. This patch fixes
this issue.

Signed-off-by: Krzysztof Adamski <k@japko.eu>
---
 Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index 9213b27..3e56b16 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -21,6 +21,7 @@ Required properties:
   "allwinner,sun9i-a80-r-pinctrl"
   "allwinner,sun8i-a83t-pinctrl"
   "allwinner,sun8i-h3-pinctrl"
+  "allwinner,sun8i-h3-r-pinctrl"
 
 - reg: Should contain the register physical address and length for the
   pin controller.
-- 
2.1.4

Re: [PATCH] pinctrl: sunxi: Add missing H3 R_PIO binding documentation

[Chen-Yu Tsai]

On Thu, Feb 18, 2016 at 11:49 AM, Krzysztof Adamski <k@japko.eu> wrote:
> allwinner,sun8i-h3-r-pinctrl was added by
> commit ba83a11104ae ("pinctrl: sunxi: Add H3 R_PIO controller support")
> but the patch was missing proper binding documentation. This patch fixes
> this issue.
>
> Signed-off-by: Krzysztof Adamski <k@japko.eu>

Acked-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>

Re: [PATCH] pinctrl: sunxi: Add missing H3 R_PIO binding documentation

[Linus Walleij]

On Thu, Feb 18, 2016 at 8:49 PM, Krzysztof Adamski <k@japko.eu> wrote:

> allwinner,sun8i-h3-r-pinctrl was added by
> commit ba83a11104ae ("pinctrl: sunxi: Add H3 R_PIO controller support")
> but the patch was missing proper binding documentation. This patch fixes
> this issue.
>
> Signed-off-by: Krzysztof Adamski <k@japko.eu>

Patch applied with Chen-Yu's ACK.

Yours,
Linus Walleij

[PATCH v2 4/5] ARM: dts: sun8i-h3: Add R_PIO controller node to the dtsi

[Krzysztof Adamski]

Add the corresponding device node for R_PIO on H3 to the dtsi. Support
for the controller was added in earlier commit.

Signed-off-by: Krzysztof Adamski <k@japko.eu>
---
 .../devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt  |  1 +
 arch/arm/boot/dts/sun8i-h3.dtsi                              | 12 ++++++++++++
 2 files changed, 13 insertions(+)

diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index 9213b27..3e56b16 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -21,6 +21,7 @@ Required properties:
   "allwinner,sun9i-a80-r-pinctrl"
   "allwinner,sun8i-a83t-pinctrl"
   "allwinner,sun8i-h3-pinctrl"
+  "allwinner,sun8i-h3-r-pinctrl"
 
 - reg: Should contain the register physical address and length for the
   pin controller.
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index ce35e93..1593e2d 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -525,5 +525,17 @@
 			compatible = "allwinner,sun6i-a31-clock-reset";
 			#reset-cells = <1>;
 		};
+
+		r_pio: pinctrl@01f02c00 {
+			compatible = "allwinner,sun8i-h3-r-pinctrl";
+			reg = <0x01f02c00 0x400>;
+			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&apb0_gates 0>;
+			resets = <&apb0_reset 0>;
+			gpio-controller;
+			#gpio-cells = <3>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
 	};
 };
-- 
2.1.4

Re: [PATCH v2 4/5] ARM: dts: sun8i-h3: Add R_PIO controller node to the dtsi

[Julian Calaby]

Hi Krzysztof,

On Wed, Feb 3, 2016 at 8:21 AM, Krzysztof Adamski <k@japko.eu> wrote:
> Add the corresponding device node for R_PIO on H3 to the dtsi. Support
> for the controller was added in earlier commit.
>
> Signed-off-by: Krzysztof Adamski <k@japko.eu>
> ---
>  .../devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt  |  1 +
>  arch/arm/boot/dts/sun8i-h3.dtsi                              | 12 ++++++++++++
>  2 files changed, 13 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> index 9213b27..3e56b16 100644
> --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> @@ -21,6 +21,7 @@ Required properties:
>    "allwinner,sun9i-a80-r-pinctrl"
>    "allwinner,sun8i-a83t-pinctrl"
>    "allwinner,sun8i-h3-pinctrl"
> +  "allwinner,sun8i-h3-r-pinctrl"

Shouldn't this change go in the patch that introduces the driver for
this pinctl?

Thanks,

-- 
Julian Calaby

Email: julian.calaby-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
Profile: http://www.google.com/profiles/julian.calaby/

[PATCH v2 5/5] pinctrl: sunxi: Use pin number when calling sunxi_pmx_set

[Krzysztof Adamski]

sunxi_pmx_set accepts pin number and then calculates offset by
subtracting pin_base from it. sunxi_pinctrl_gpio_get, on the other hand,
gets offset so we have to convert it to pin number so we won't get
negative value in sunxi_pmx_set.

This was only used on A10 so far, where there is only one GPIO chip with
pin_base set to 0 so it didn't matter. However H3 also requires this
workaround but have two pinmux sections, triggering problem for PL port.

Signed-off-by: Krzysztof Adamski <k@japko.eu>
---
 drivers/pinctrl/sunxi/pinctrl-sunxi.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index 7a2465f..9e5bac9 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -460,14 +460,17 @@ static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset)
 	u32 set_mux = pctl->desc->irq_read_needs_mux &&
 			test_bit(FLAG_USED_AS_IRQ, &chip->desc[offset].flags);
 	u32 val;
+	u32 pin;
 
-	if (set_mux)
-		sunxi_pmx_set(pctl->pctl_dev, offset, SUN4I_FUNC_INPUT);
+	if (set_mux) {
+		pin = offset + pctl->desc->pin_base;
+		sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_INPUT);
+	}
 
 	val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK;
 
 	if (set_mux)
-		sunxi_pmx_set(pctl->pctl_dev, offset, SUN4I_FUNC_IRQ);
+		sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_IRQ);
 
 	return !!val;
 }
-- 
2.1.4

Re: [PATCH v2 5/5] pinctrl: sunxi: Use pin number when calling sunxi_pmx_set

[Chen-Yu Tsai]

Hi,

On Wed, Feb 3, 2016 at 5:21 AM, Krzysztof Adamski <k@japko.eu> wrote:
> sunxi_pmx_set accepts pin number and then calculates offset by
> subtracting pin_base from it. sunxi_pinctrl_gpio_get, on the other hand,
> gets offset so we have to convert it to pin number so we won't get
> negative value in sunxi_pmx_set.
>
> This was only used on A10 so far, where there is only one GPIO chip with
> pin_base set to 0 so it didn't matter. However H3 also requires this
> workaround but have two pinmux sections, triggering problem for PL port.
>
> Signed-off-by: Krzysztof Adamski <k@japko.eu>
> ---
>  drivers/pinctrl/sunxi/pinctrl-sunxi.c | 9 ++++++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> index 7a2465f..9e5bac9 100644
> --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> @@ -460,14 +460,17 @@ static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset)
>         u32 set_mux = pctl->desc->irq_read_needs_mux &&
>                         test_bit(FLAG_USED_AS_IRQ, &chip->desc[offset].flags);
>         u32 val;
> +       u32 pin;
>
> -       if (set_mux)
> -               sunxi_pmx_set(pctl->pctl_dev, offset, SUN4I_FUNC_INPUT);
> +       if (set_mux) {
> +               pin = offset + pctl->desc->pin_base;

You can use chip->base directly. It's value is set to pin_base in the
init function.
You could also move this out of the if block, and not add the braces.

Otherwise this looks good.

ChenYu

> +               sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_INPUT);
> +       }
>
>         val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK;
>
>         if (set_mux)
> -               sunxi_pmx_set(pctl->pctl_dev, offset, SUN4I_FUNC_IRQ);
> +               sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_IRQ);
>
>         return !!val;
>  }
> --
> 2.1.4
>

Re: [PATCH v2 5/5] pinctrl: sunxi: Use pin number when calling sunxi_pmx_set

[Linus Walleij]

On Tue, Feb 2, 2016 at 10:21 PM, Krzysztof Adamski <k@japko.eu> wrote:

> sunxi_pmx_set accepts pin number and then calculates offset by
> subtracting pin_base from it. sunxi_pinctrl_gpio_get, on the other hand,
> gets offset so we have to convert it to pin number so we won't get
> negative value in sunxi_pmx_set.
>
> This was only used on A10 so far, where there is only one GPIO chip with
> pin_base set to 0 so it didn't matter. However H3 also requires this
> workaround but have two pinmux sections, triggering problem for PL port.
>
> Signed-off-by: Krzysztof Adamski <k@japko.eu>

Waiting for Maxime to review this. I guess this patch can be merged
independently of the other patches?

Yours,
Linus Walleij

Re: Re: [PATCH v2 5/5] pinctrl: sunxi: Use pin number when calling sunxi_pmx_set

[Krzysztof Adamski]

On Thu, Feb 11, 2016 at 02:17:41PM +0100, Linus Walleij wrote:
>On Tue, Feb 2, 2016 at 10:21 PM, Krzysztof Adamski <k@japko.eu> wrote:
>
>> sunxi_pmx_set accepts pin number and then calculates offset by
>> subtracting pin_base from it. sunxi_pinctrl_gpio_get, on the other hand,
>> gets offset so we have to convert it to pin number so we won't get
>> negative value in sunxi_pmx_set.
>>
>> This was only used on A10 so far, where there is only one GPIO chip with
>> pin_base set to 0 so it didn't matter. However H3 also requires this
>> workaround but have two pinmux sections, triggering problem for PL port.
>>
>> Signed-off-by: Krzysztof Adamski <k@japko.eu>
>
>Waiting for Maxime to review this. I guess this patch can be merged
>independently of the other patches?

Yes it can but it won't have any effect, as stated in the commit 
message, since other SoCs either don't use this flag or have only one 
port so theri pin_base=0.

Best regards,
Krzysztof Adamski

Re: Re: [PATCH v2 5/5] pinctrl: sunxi: Use pin number when calling sunxi_pmx_set

[Linus Walleij]

On Thu, Feb 11, 2016 at 2:20 PM, Krzysztof Adamski <k@japko.eu> wrote:
> On Thu, Feb 11, 2016 at 02:17:41PM +0100, Linus Walleij wrote:
>>
>> On Tue, Feb 2, 2016 at 10:21 PM, Krzysztof Adamski <k@japko.eu> wrote:
>>
>>> sunxi_pmx_set accepts pin number and then calculates offset by
>>> subtracting pin_base from it. sunxi_pinctrl_gpio_get, on the other hand,
>>> gets offset so we have to convert it to pin number so we won't get
>>> negative value in sunxi_pmx_set.
>>>
>>> This was only used on A10 so far, where there is only one GPIO chip with
>>> pin_base set to 0 so it didn't matter. However H3 also requires this
>>> workaround but have two pinmux sections, triggering problem for PL port.
>>>
>>> Signed-off-by: Krzysztof Adamski <k@japko.eu>
>>
>>
>> Waiting for Maxime to review this. I guess this patch can be merged
>> independently of the other patches?
>
> Yes it can but it won't have any effect, as stated in the commit message,
> since other SoCs either don't use this flag or have only one port so theri
> pin_base=0.

Who cares as long as it will be used eventually.

Merged v4 as stated earlier.

Yours,
Linus Walleij

Re: [PATCH v2 5/5] pinctrl: sunxi: Use pin number when calling sunxi_pmx_set

[Chen-Yu Tsai]

Hi,

On Thu, Feb 11, 2016 at 9:17 PM, Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> wrote:
> On Tue, Feb 2, 2016 at 10:21 PM, Krzysztof Adamski <k@japko.eu> wrote:
>
>> sunxi_pmx_set accepts pin number and then calculates offset by
>> subtracting pin_base from it. sunxi_pinctrl_gpio_get, on the other hand,
>> gets offset so we have to convert it to pin number so we won't get
>> negative value in sunxi_pmx_set.
>>
>> This was only used on A10 so far, where there is only one GPIO chip with
>> pin_base set to 0 so it didn't matter. However H3 also requires this
>> workaround but have two pinmux sections, triggering problem for PL port.
>>
>> Signed-off-by: Krzysztof Adamski <k@japko.eu>
>
> Waiting for Maxime to review this. I guess this patch can be merged
> independently of the other patches?

FYI there's a v4 of this patch that both Maxime and I acked.

ChenYu

[PATCH v2 2/5] dts: sun8i-h3: Add APB0 related clocks and resets

[Krzysztof Adamski]

APB0 is bearly mentioned in H3 User Manual and it is only setup in the
Allwinners kernel dump for CIR. I have verified experimentally that the
gate for R_PIO exists and works, though. There are probably other gates
there but I don't know their order right now and I don't have access to
their peripherals on my board to test them.

Signed-off-by: Krzysztof Adamski <k@japko.eu>
---
 arch/arm/boot/dts/sun8i-h3.dtsi | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 1524130e..ce35e93 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -276,6 +276,32 @@
 			clocks = <&osc24M>, <&pll6 1>, <&pll5>;
 			clock-output-names = "mbus";
 		};
+
+		ahb0: ahb0_clk {
+			compatible = "fixed-factor-clock";
+			#clock-cells = <0>;
+			clock-div = <1>;
+			clock-mult = <1>;
+			clocks = <&osc24M>, <&osc32k>;
+			clock-output-names = "ahb0";
+		};
+
+		apb0: clk@01f0140c {
+			compatible = "allwinner,sun8i-a23-apb0-clk";
+			reg = <0x01f0140c 0x4>;
+			#clock-cells = <0>;
+			clocks = <&ahb0>;
+			clock-output-names = "apb0";
+		};
+
+		apb0_gates: clk@01f01428 {
+			compatible = "allwinner,sun8i-h3-abp0-gates-clk";
+			reg = <0x01f01428 0x4>;
+			#clock-cells = <1>;
+			clocks = <&apb0>;
+			clock-indices = <0>, <1>;
+			clock-output-names = "apb0_pio", "apb0_ir";
+		};
 	};
 
 	soc {
@@ -493,5 +519,11 @@
 			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 		};
+
+		apb0_reset: reset@01f014b0 {
+			reg = <0x01f014b0 0x4>;
+			compatible = "allwinner,sun6i-a31-clock-reset";
+			#reset-cells = <1>;
+		};
 	};
 };
-- 
2.1.4

Re: [PATCH v2 2/5] dts: sun8i-h3: Add APB0 related clocks and resets

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 1331 bytes --]

Hi,

On Tue, Feb 02, 2016 at 10:21:50PM +0100, Krzysztof Adamski wrote:
> APB0 is bearly mentioned in H3 User Manual and it is only setup in the
> Allwinners kernel dump for CIR. I have verified experimentally that the
> gate for R_PIO exists and works, though. There are probably other gates
> there but I don't know their order right now and I don't have access to
> their peripherals on my board to test them.
> 
> Signed-off-by: Krzysztof Adamski <k@japko.eu>
> ---
>  arch/arm/boot/dts/sun8i-h3.dtsi | 32 ++++++++++++++++++++++++++++++++
>  1 file changed, 32 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
> index 1524130e..ce35e93 100644
> --- a/arch/arm/boot/dts/sun8i-h3.dtsi
> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
> @@ -276,6 +276,32 @@
>  			clocks = <&osc24M>, <&pll6 1>, <&pll5>;
>  			clock-output-names = "mbus";
>  		};
> +
> +		ahb0: ahb0_clk {
> +			compatible = "fixed-factor-clock";
> +			#clock-cells = <0>;
> +			clock-div = <1>;
> +			clock-mult = <1>;
> +			clocks = <&osc24M>, <&osc32k>;
> +			clock-output-names = "ahb0";
> +		};

I'm not sure what you mean there. The fixed factor clocks only take a
single parent, and you provided two.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

Re: [PATCH v2 2/5] dts: sun8i-h3: Add APB0 related clocks and resets

[Krzysztof Adamski]

On Wed, Feb 03, 2016 at 01:35:34PM +0100, Maxime Ripard wrote:
>Hi,
>
>On Tue, Feb 02, 2016 at 10:21:50PM +0100, Krzysztof Adamski wrote:
>> APB0 is bearly mentioned in H3 User Manual and it is only setup in the
>> Allwinners kernel dump for CIR. I have verified experimentally that the
>> gate for R_PIO exists and works, though. There are probably other gates
>> there but I don't know their order right now and I don't have access to
>> their peripherals on my board to test them.
>>
>> Signed-off-by: Krzysztof Adamski <k@japko.eu>
>> ---
>>  arch/arm/boot/dts/sun8i-h3.dtsi | 32 ++++++++++++++++++++++++++++++++
>>  1 file changed, 32 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
>> index 1524130e..ce35e93 100644
>> --- a/arch/arm/boot/dts/sun8i-h3.dtsi
>> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
>> @@ -276,6 +276,32 @@
>>  			clocks = <&osc24M>, <&pll6 1>, <&pll5>;
>>  			clock-output-names = "mbus";
>>  		};
>> +
>> +		ahb0: ahb0_clk {
>> +			compatible = "fixed-factor-clock";
>> +			#clock-cells = <0>;
>> +			clock-div = <1>;
>> +			clock-mult = <1>;
>> +			clocks = <&osc24M>, <&osc32k>;
>> +			clock-output-names = "ahb0";
>> +		};
>
>I'm not sure what you mean there. The fixed factor clocks only take a
>single parent, and you provided two.

True, I that's actually some stupid leftover. As mentioned in the commit 
message I didn't really know how the clock tree looks like here so I 
wanted to just pretend it's connectet to osc24M. After some experiments 
I think that 0x01f0140c register does not exist on H3 and I was finally 
(hopefully) able to understand how this clock is set up in Allwinner's 
code. So I changed the clock to factors clock with possible osc32k and 
osc24M parrents. Will send it in v3.

Re: [PATCH v2 2/5] dts: sun8i-h3: Add APB0 related clocks and resets

[Krzysztof Adamski]

On Wed, Feb 03, 2016 at 11:21:17PM +0100, Krzysztof Adamski wrote:
>On Wed, Feb 03, 2016 at 01:35:34PM +0100, Maxime Ripard wrote:
>>Hi,
>>
>>I'm not sure what you mean there. The fixed factor clocks only take a
>>single parent, and you provided two.
>
>True, I that's actually some stupid leftover. As mentioned in the 
>commit message I didn't really know how the clock tree looks like here 
>so I wanted to just pretend it's connectet to osc24M. After some 
>experiments I think that 0x01f0140c register does not exist on H3 and 
>I was finally (hopefully) able to understand how this clock is set up 
>in Allwinner's code. So I changed the clock to factors clock with 
>possible osc32k and osc24M parrents. Will send it in v3.

I've changed my mind about using factors clock. The clock I was thinking 
about is only setup for CIR peripheral and I have no information on how 
r_pio is clocked other than the fact it works by default so I assume 
it's clocked from 24M oscillator. New patchset send, let me know what 
you think.