Re: [PATCH v3] Fix sun7i pin assignment for IRQ's

[Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>]

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Hi,

On Sun, Feb 21, 2016 at 02:20:41PM +0100, Henry Paulissen wrote:
> After testing IRQ pins we found some bugs in the pinctrl declaration.

Your commit log is going to need some work. Which bugs? What tests did
you make? Why are you making these changes while the datasheet says
otherwise?

> Signed-off-by: Henry Paulissen <henry-oxlTVf6CAJF4HdFT58BDcQ@public.gmane.org>
> ---
> 
> Changes in v2:
>     After some more testing we found irq on PI pins.
>     they where on mux6 so this is included in my patch.
> 
>     Also included is a warning for PI17, this pin was not working
>     on apritzel his bPI and he thinks it might be correlated to
>     GIC and IRQ 29.
> 
> Changes in v3:
>     Changed name from nickname to realname in email and SoB.
> ---
>  drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c | 25 +++++++++++--------------
>  1 file changed, 11 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
> index cf1ce0c..0fe173e 100644
> --- a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
> +++ b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
> @@ -344,25 +344,21 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
>  		  SUNXI_FUNCTION(0x1, "gpio_out"),
>  		  SUNXI_FUNCTION(0x2, "nand0"),		/* NCE4 */
>  		  SUNXI_FUNCTION(0x3, "spi2"),		/* CS0 */
> -		  SUNXI_FUNCTION_IRQ(0x6, 12)),		/* EINT12 */

Have you tried to compile it?

Thanks,
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com