* [PATCH v6] Fix sun7i pin assignment for IRQ's
@ 2016-02-22 17:07 Henry Paulissen
0 siblings, 0 replies; 6+ messages in thread
From: Henry Paulissen @ 2016-02-22 17:07 UTC (permalink / raw)
To: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
Cc: Linus Walleij, Maxime Ripard, Chen-Yu Tsai, Hongzhou Yang,
Fabian Frederick, Patrice Chotard,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
After testing IRQ pins we found some bugs in the pinctrl declaration.
Both PI* and PC* pins didn't work. PI* pins seemed to be connected
to the wrong mux and PC* pins waren't working at all.
Please note that the A20 soc manual is contradicting between version
and even within the same document for both the PI and PC pins.
Patch is based on testing with the hardware itself.
Tested-by: Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org>
Reviewed-by: Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org>
Signed-off-by: Henry Paulissen <henry-oxlTVf6CAJF4HdFT58BDcQ@public.gmane.org>
---
Changes in v2:
After some more testing we found irq on PI pins.
they where on mux6 so this is included in my patch.
Also included is a warning for PI17, this pin was not working
on apritzel his bPI and he thinks it might be correlated to
GIC and IRQ 29.
Changes in v3:
Changed name from nickname to realname in email and SoB.
Changes in v4:
Added closing parenthesis for the C pins.
Changes in v5:
Added a more detailed description.
Changes in v6:
Removed extra comment about pin I17 (extra tests needed).
Added tested and reviewed by tags.
---
drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c | 33 ++++++++++++++-----------------
1 file changed, 15 insertions(+), 18 deletions(-)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
index cf1ce0c..ca7b9a3 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
@@ -343,26 +343,22 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */
- SUNXI_FUNCTION(0x3, "spi2"), /* CS0 */
- SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */
+ SUNXI_FUNCTION(0x3, "spi2")), /* CS0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 20),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NCE5 */
- SUNXI_FUNCTION(0x3, "spi2"), /* CLK */
- SUNXI_FUNCTION_IRQ(0x6, 13)), /* EINT13 */
+ SUNXI_FUNCTION(0x3, "spi2")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 21),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NCE6 */
- SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */
- SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */
+ SUNXI_FUNCTION(0x3, "spi2")), /* MOSI */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 22),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NCE7 */
- SUNXI_FUNCTION(0x3, "spi2"), /* MISO */
- SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */
+ SUNXI_FUNCTION(0x3, "spi2")), /* MISO */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 23),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
@@ -960,65 +956,66 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */
SUNXI_FUNCTION(0x3, "uart5"), /* TX */
- SUNXI_FUNCTION_IRQ(0x5, 22)), /* EINT22 */
+ SUNXI_FUNCTION_IRQ(0x6, 22)), /* EINT22 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
SUNXI_FUNCTION(0x3, "uart5"), /* RX */
- SUNXI_FUNCTION_IRQ(0x5, 23)), /* EINT23 */
+ SUNXI_FUNCTION_IRQ(0x6, 23)), /* EINT23 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */
SUNXI_FUNCTION(0x3, "uart6"), /* TX */
SUNXI_FUNCTION(0x4, "clk_out_a"), /* CLK_OUT_A */
- SUNXI_FUNCTION_IRQ(0x5, 24)), /* EINT24 */
+ SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* MISO */
SUNXI_FUNCTION(0x3, "uart6"), /* RX */
SUNXI_FUNCTION(0x4, "clk_out_b"), /* CLK_OUT_B */
- SUNXI_FUNCTION_IRQ(0x5, 25)), /* EINT25 */
+ SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* CS1 */
SUNXI_FUNCTION(0x3, "ps2"), /* SCK1 */
SUNXI_FUNCTION(0x4, "timer4"), /* TCLKIN0 */
- SUNXI_FUNCTION_IRQ(0x5, 26)), /* EINT26 */
+ SUNXI_FUNCTION_IRQ(0x6, 26)), /* EINT26 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
SUNXI_FUNCTION(0x3, "ps2"), /* SDA1 */
SUNXI_FUNCTION(0x4, "timer5"), /* TCLKIN1 */
- SUNXI_FUNCTION_IRQ(0x5, 27)), /* EINT27 */
+ SUNXI_FUNCTION_IRQ(0x6, 27)), /* EINT27 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
SUNXI_FUNCTION(0x3, "uart2"), /* RTS */
- SUNXI_FUNCTION_IRQ(0x5, 28)), /* EINT28 */
+ SUNXI_FUNCTION_IRQ(0x6, 28)), /* EINT28 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
SUNXI_FUNCTION(0x3, "uart2"), /* CTS */
- SUNXI_FUNCTION_IRQ(0x5, 29)), /* EINT29 */
+ SUNXI_FUNCTION_IRQ(0x6, 29)), /* EINT29 */
+ /* EINT29 might not work - more testing needed */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
SUNXI_FUNCTION(0x3, "uart2"), /* TX */
- SUNXI_FUNCTION_IRQ(0x5, 30)), /* EINT30 */
+ SUNXI_FUNCTION_IRQ(0x6, 30)), /* EINT30 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 19),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
SUNXI_FUNCTION(0x3, "uart2"), /* RX */
- SUNXI_FUNCTION_IRQ(0x5, 31)), /* EINT31 */
+ SUNXI_FUNCTION_IRQ(0x6, 31)), /* EINT31 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 20),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
--
2.5.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v6] Fix sun7i pin assignment for IRQ's
@ 2016-02-22 17:14 Henry Paulissen
[not found] ` <1456161251-2303-1-git-send-email-henry-oxlTVf6CAJF4HdFT58BDcQ@public.gmane.org>
0 siblings, 1 reply; 6+ messages in thread
From: Henry Paulissen @ 2016-02-22 17:14 UTC (permalink / raw)
To: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
Cc: Linus Walleij, Maxime Ripard, Chen-Yu Tsai, Andre Przywara,
Jean-Christophe PLAGNIOL-VILLARD, Maxime Coquelin, Lee Jones,
Hongzhou Yang, Fabian Frederick,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
After testing IRQ pins we found some bugs in the pinctrl declaration.
Both PI* and PC* pins didn't work. PI* pins seemed to be connected
to the wrong mux and PC* pins waren't working at all.
Please note that the A20 soc manual is contradicting between version
and even within the same document for both the PI and PC pins.
Patch is based on testing with the hardware itself.
Tested-by: Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org>
Reviewed-by: Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org>
Signed-off-by: Henry Paulissen <henry-oxlTVf6CAJF4HdFT58BDcQ@public.gmane.org>
---
Changes in v2:
After some more testing we found irq on PI pins.
they where on mux6 so this is included in my patch.
Also included is a warning for PI17, this pin was not working
on apritzel his bPI and he thinks it might be correlated to
GIC and IRQ 29.
Changes in v3:
Changed name from nickname to realname in email and SoB.
Changes in v4:
Added closing parenthesis for the C pins.
Changes in v5:
Added a more detailed description.
Changes in v6:
Removed extra comment about pin I17 (extra tests needed).
Added tested and reviewed by tags.
---
drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c | 32 ++++++++++++++-----------------
1 file changed, 14 insertions(+), 18 deletions(-)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
index cf1ce0c..435ad30 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
@@ -343,26 +343,22 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */
- SUNXI_FUNCTION(0x3, "spi2"), /* CS0 */
- SUNXI_FUNCTION_IRQ(0x6, 12)), /* EINT12 */
+ SUNXI_FUNCTION(0x3, "spi2")), /* CS0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 20),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NCE5 */
- SUNXI_FUNCTION(0x3, "spi2"), /* CLK */
- SUNXI_FUNCTION_IRQ(0x6, 13)), /* EINT13 */
+ SUNXI_FUNCTION(0x3, "spi2")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 21),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NCE6 */
- SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */
- SUNXI_FUNCTION_IRQ(0x6, 14)), /* EINT14 */
+ SUNXI_FUNCTION(0x3, "spi2")), /* MOSI */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 22),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0"), /* NCE7 */
- SUNXI_FUNCTION(0x3, "spi2"), /* MISO */
- SUNXI_FUNCTION_IRQ(0x6, 15)), /* EINT15 */
+ SUNXI_FUNCTION(0x3, "spi2")), /* MISO */
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 23),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
@@ -960,65 +956,65 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */
SUNXI_FUNCTION(0x3, "uart5"), /* TX */
- SUNXI_FUNCTION_IRQ(0x5, 22)), /* EINT22 */
+ SUNXI_FUNCTION_IRQ(0x6, 22)), /* EINT22 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
SUNXI_FUNCTION(0x3, "uart5"), /* RX */
- SUNXI_FUNCTION_IRQ(0x5, 23)), /* EINT23 */
+ SUNXI_FUNCTION_IRQ(0x6, 23)), /* EINT23 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */
SUNXI_FUNCTION(0x3, "uart6"), /* TX */
SUNXI_FUNCTION(0x4, "clk_out_a"), /* CLK_OUT_A */
- SUNXI_FUNCTION_IRQ(0x5, 24)), /* EINT24 */
+ SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* MISO */
SUNXI_FUNCTION(0x3, "uart6"), /* RX */
SUNXI_FUNCTION(0x4, "clk_out_b"), /* CLK_OUT_B */
- SUNXI_FUNCTION_IRQ(0x5, 25)), /* EINT25 */
+ SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi0"), /* CS1 */
SUNXI_FUNCTION(0x3, "ps2"), /* SCK1 */
SUNXI_FUNCTION(0x4, "timer4"), /* TCLKIN0 */
- SUNXI_FUNCTION_IRQ(0x5, 26)), /* EINT26 */
+ SUNXI_FUNCTION_IRQ(0x6, 26)), /* EINT26 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
SUNXI_FUNCTION(0x3, "ps2"), /* SDA1 */
SUNXI_FUNCTION(0x4, "timer5"), /* TCLKIN1 */
- SUNXI_FUNCTION_IRQ(0x5, 27)), /* EINT27 */
+ SUNXI_FUNCTION_IRQ(0x6, 27)), /* EINT27 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
SUNXI_FUNCTION(0x3, "uart2"), /* RTS */
- SUNXI_FUNCTION_IRQ(0x5, 28)), /* EINT28 */
+ SUNXI_FUNCTION_IRQ(0x6, 28)), /* EINT28 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
SUNXI_FUNCTION(0x3, "uart2"), /* CTS */
- SUNXI_FUNCTION_IRQ(0x5, 29)), /* EINT29 */
+ SUNXI_FUNCTION_IRQ(0x6, 29)), /* EINT29 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 18),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
SUNXI_FUNCTION(0x3, "uart2"), /* TX */
- SUNXI_FUNCTION_IRQ(0x5, 30)), /* EINT30 */
+ SUNXI_FUNCTION_IRQ(0x6, 30)), /* EINT30 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 19),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
SUNXI_FUNCTION(0x3, "uart2"), /* RX */
- SUNXI_FUNCTION_IRQ(0x5, 31)), /* EINT31 */
+ SUNXI_FUNCTION_IRQ(0x6, 31)), /* EINT31 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 20),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
--
2.5.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v6] Fix sun7i pin assignment for IRQ's
[not found] ` <1456161251-2303-1-git-send-email-henry-oxlTVf6CAJF4HdFT58BDcQ@public.gmane.org>
@ 2016-02-25 0:54 ` Maxime Ripard
2016-02-25 14:16 ` Linus Walleij
0 siblings, 1 reply; 6+ messages in thread
From: Maxime Ripard @ 2016-02-25 0:54 UTC (permalink / raw)
To: Henry Paulissen
Cc: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Linus Walleij, Chen-Yu Tsai,
Andre Przywara, Jean-Christophe PLAGNIOL-VILLARD, Maxime Coquelin,
Lee Jones, Hongzhou Yang, Fabian Frederick,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
[-- Attachment #1: Type: text/plain, Size: 938 bytes --]
Hi,
Usually, the patch title should be prefixed by the subsystem it
applies to so that maintainer and reviewers can spot it more
easily. In this case, it would be something like
pinctrl: sunxi: Fix sun7i pin assignment for IRQ's
On Mon, Feb 22, 2016 at 06:14:07PM +0100, Henry Paulissen wrote:
> After testing IRQ pins we found some bugs in the pinctrl declaration.
> Both PI* and PC* pins didn't work. PI* pins seemed to be connected
> to the wrong mux and PC* pins waren't working at all.
>
> Please note that the A20 soc manual is contradicting between version
> and even within the same document for both the PI and PC pins.
Which sections are in contradiction?
> Patch is based on testing with the hardware itself.
How did you test it? Using the sysfs API, or did you have any hardware
connected to it?
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v6] Fix sun7i pin assignment for IRQ's
2016-02-25 0:54 ` Maxime Ripard
@ 2016-02-25 14:16 ` Linus Walleij
[not found] ` <CACRpkdYmf8-ZPV5q9H3cdZtQDUkbx=bcrVg9a8M3zEAifXxF9A-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
0 siblings, 1 reply; 6+ messages in thread
From: Linus Walleij @ 2016-02-25 14:16 UTC (permalink / raw)
To: Maxime Ripard
Cc: Henry Paulissen, linux-sunxi, Chen-Yu Tsai, Andre Przywara,
Jean-Christophe PLAGNIOL-VILLARD, Maxime Coquelin, Lee Jones,
Hongzhou Yang, Fabian Frederick, linux-gpio@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
On Thu, Feb 25, 2016 at 1:54 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
>
> Usually, the patch title should be prefixed by the subsystem it
> applies to so that maintainer and reviewers can spot it more
> easily. In this case, it would be something like
>
> pinctrl: sunxi: Fix sun7i pin assignment for IRQ's
>
> On Mon, Feb 22, 2016 at 06:14:07PM +0100, Henry Paulissen wrote:
>> After testing IRQ pins we found some bugs in the pinctrl declaration.
>> Both PI* and PC* pins didn't work. PI* pins seemed to be connected
>> to the wrong mux and PC* pins waren't working at all.
>>
>> Please note that the A20 soc manual is contradicting between version
>> and even within the same document for both the PI and PC pins.
>
> Which sections are in contradiction?
>
>> Patch is based on testing with the hardware itself.
>
> How did you test it? Using the sysfs API, or did you have any hardware
> connected to it?
I'm taking this patch out of my tree now following Maxime's comments.
I'm a bit annoyed that it is iterating too quickly as well, I will
wait and see for a while.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v6] Fix sun7i pin assignment for IRQ's
[not found] ` <CACRpkdYmf8-ZPV5q9H3cdZtQDUkbx=bcrVg9a8M3zEAifXxF9A-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
@ 2016-02-25 14:26 ` Henry Paulissen
[not found] ` <280e414e-546e-4a91-91a6-a4fa7157db49-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org>
0 siblings, 1 reply; 6+ messages in thread
From: Henry Paulissen @ 2016-02-25 14:26 UTC (permalink / raw)
To: linux-sunxi
Cc: maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
draakje197-Re5JQEeQqe8AvxtiuMwx3w, wens-jdAy2FN1RRM,
andre.przywara-5wv7dgnIgG8, plagnioj-sclMFOaUSTBWk0Htik3J/w,
maxime.coquelin-qxv4g6HH51o, lee-DgEjT+Ai2ygdnm+yROfE0A,
hongzhou.yang-NuS5LvNUpcJWk0Htik3J/w, fabf-AgBVmzD5pcezQB+pC5nmwQ,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linus.walleij-QSEj5FYQhm4dnm+yROfE0A
[-- Attachment #1.1: Type: text/plain, Size: 852 bytes --]
Op donderdag 25 februari 2016 15:16:49 UTC+1 schreef Linus Walleij:
>
> I'm taking this patch out of my tree now following Maxime's comments.
>
> I'm a bit annoyed that it is iterating too quickly as well, I will
> wait and see for a while.
>
>
All of Maxime his questions where already answered in a reply to him at:
Date: Sun, 21 Feb 2016 11:27:46 -0800 (PST)
Patch V6 is the latest and final.
Code itself is reviewed and tested and the last few iterations where only
cosmetic (changing description, etc).
Regards,
Henry
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v6] Fix sun7i pin assignment for IRQ's
[not found] ` <280e414e-546e-4a91-91a6-a4fa7157db49-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org>
@ 2016-02-25 17:42 ` Maxime Ripard
0 siblings, 0 replies; 6+ messages in thread
From: Maxime Ripard @ 2016-02-25 17:42 UTC (permalink / raw)
To: Henry Paulissen
Cc: linux-sunxi, draakje197-Re5JQEeQqe8AvxtiuMwx3w, wens-jdAy2FN1RRM,
andre.przywara-5wv7dgnIgG8, plagnioj-sclMFOaUSTBWk0Htik3J/w,
maxime.coquelin-qxv4g6HH51o, lee-DgEjT+Ai2ygdnm+yROfE0A,
hongzhou.yang-NuS5LvNUpcJWk0Htik3J/w, fabf-AgBVmzD5pcezQB+pC5nmwQ,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linus.walleij-QSEj5FYQhm4dnm+yROfE0A
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Hi,
On Thu, Feb 25, 2016 at 06:26:22AM -0800, Henry Paulissen wrote:
>
>
> Op donderdag 25 februari 2016 15:16:49 UTC+1 schreef Linus Walleij:
>
> >
> > I'm taking this patch out of my tree now following Maxime's comments.
> >
> > I'm a bit annoyed that it is iterating too quickly as well, I will
> > wait and see for a while.
> >
> >
> All of Maxime his questions where already answered in a reply to him at:
> Date: Sun, 21 Feb 2016 11:27:46 -0800 (PST)
And I was not among the recipients of that mail, please try to keep
everyone in Cc.
Commenting on it right now....
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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2016-02-22 17:14 [PATCH v6] Fix sun7i pin assignment for IRQ's Henry Paulissen
[not found] ` <1456161251-2303-1-git-send-email-henry-oxlTVf6CAJF4HdFT58BDcQ@public.gmane.org>
2016-02-25 0:54 ` Maxime Ripard
2016-02-25 14:16 ` Linus Walleij
[not found] ` <CACRpkdYmf8-ZPV5q9H3cdZtQDUkbx=bcrVg9a8M3zEAifXxF9A-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2016-02-25 14:26 ` Henry Paulissen
[not found] ` <280e414e-546e-4a91-91a6-a4fa7157db49-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org>
2016-02-25 17:42 ` Maxime Ripard
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2016-02-22 17:07 Henry Paulissen
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