[PATCH v3] Fix sun7i pin assignment for IRQ's

[PATCH v3] Fix sun7i pin assignment for IRQ's

[Henry Paulissen]

After testing IRQ pins we found some bugs in the pinctrl declaration.

Signed-off-by: Henry Paulissen <henry-oxlTVf6CAJF4HdFT58BDcQ@public.gmane.org>
---

Changes in v2:
    After some more testing we found irq on PI pins.
    they where on mux6 so this is included in my patch.

    Also included is a warning for PI17, this pin was not working
    on apritzel his bPI and he thinks it might be correlated to
    GIC and IRQ 29.

Changes in v3:
    Changed name from nickname to realname in email and SoB.
---
 drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c | 25 +++++++++++--------------
 1 file changed, 11 insertions(+), 14 deletions(-)

diff --git a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
index cf1ce0c..0fe173e 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
@@ -344,25 +344,21 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
 		  SUNXI_FUNCTION(0x1, "gpio_out"),
 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NCE4 */
 		  SUNXI_FUNCTION(0x3, "spi2"),		/* CS0 */
-		  SUNXI_FUNCTION_IRQ(0x6, 12)),		/* EINT12 */
 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 20),
 		  SUNXI_FUNCTION(0x0, "gpio_in"),
 		  SUNXI_FUNCTION(0x1, "gpio_out"),
 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NCE5 */
 		  SUNXI_FUNCTION(0x3, "spi2"),		/* CLK */
-		  SUNXI_FUNCTION_IRQ(0x6, 13)),		/* EINT13 */
 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 21),
 		  SUNXI_FUNCTION(0x0, "gpio_in"),
 		  SUNXI_FUNCTION(0x1, "gpio_out"),
 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NCE6 */
 		  SUNXI_FUNCTION(0x3, "spi2"),		/* MOSI */
-		  SUNXI_FUNCTION_IRQ(0x6, 14)),		/* EINT14 */
 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 22),
 		  SUNXI_FUNCTION(0x0, "gpio_in"),
 		  SUNXI_FUNCTION(0x1, "gpio_out"),
 		  SUNXI_FUNCTION(0x2, "nand0"),		/* NCE7 */
 		  SUNXI_FUNCTION(0x3, "spi2"),		/* MISO */
-		  SUNXI_FUNCTION_IRQ(0x6, 15)),		/* EINT15 */
 	SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 23),
 		  SUNXI_FUNCTION(0x0, "gpio_in"),
 		  SUNXI_FUNCTION(0x1, "gpio_out"),
@@ -960,65 +956,66 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
 		  SUNXI_FUNCTION(0x1, "gpio_out"),
 		  SUNXI_FUNCTION(0x2, "spi0"),		/* CS0 */
 		  SUNXI_FUNCTION(0x3, "uart5"),		/* TX */
-		  SUNXI_FUNCTION_IRQ(0x5, 22)),		/* EINT22 */
+		  SUNXI_FUNCTION_IRQ(0x6, 22)),		/* EINT22 */
 	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 11),
 		  SUNXI_FUNCTION(0x0, "gpio_in"),
 		  SUNXI_FUNCTION(0x1, "gpio_out"),
 		  SUNXI_FUNCTION(0x2, "spi0"),		/* CLK */
 		  SUNXI_FUNCTION(0x3, "uart5"),		/* RX */
-		  SUNXI_FUNCTION_IRQ(0x5, 23)),		/* EINT23 */
+		  SUNXI_FUNCTION_IRQ(0x6, 23)),		/* EINT23 */
 	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 12),
 		  SUNXI_FUNCTION(0x0, "gpio_in"),
 		  SUNXI_FUNCTION(0x1, "gpio_out"),
 		  SUNXI_FUNCTION(0x2, "spi0"),		/* MOSI */
 		  SUNXI_FUNCTION(0x3, "uart6"),		/* TX */
 		  SUNXI_FUNCTION(0x4, "clk_out_a"),	/* CLK_OUT_A */
-		  SUNXI_FUNCTION_IRQ(0x5, 24)),		/* EINT24 */
+		  SUNXI_FUNCTION_IRQ(0x6, 24)),		/* EINT24 */
 	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 13),
 		  SUNXI_FUNCTION(0x0, "gpio_in"),
 		  SUNXI_FUNCTION(0x1, "gpio_out"),
 		  SUNXI_FUNCTION(0x2, "spi0"),		/* MISO */
 		  SUNXI_FUNCTION(0x3, "uart6"),		/* RX */
 		  SUNXI_FUNCTION(0x4, "clk_out_b"),	/* CLK_OUT_B */
-		  SUNXI_FUNCTION_IRQ(0x5, 25)),		/* EINT25 */
+		  SUNXI_FUNCTION_IRQ(0x6, 25)),		/* EINT25 */
 	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 14),
 		  SUNXI_FUNCTION(0x0, "gpio_in"),
 		  SUNXI_FUNCTION(0x1, "gpio_out"),
 		  SUNXI_FUNCTION(0x2, "spi0"),		/* CS1 */
 		  SUNXI_FUNCTION(0x3, "ps2"),		/* SCK1 */
 		  SUNXI_FUNCTION(0x4, "timer4"),	/* TCLKIN0 */
-		  SUNXI_FUNCTION_IRQ(0x5, 26)),		/* EINT26 */
+		  SUNXI_FUNCTION_IRQ(0x6, 26)),		/* EINT26 */
 	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 15),
 		  SUNXI_FUNCTION(0x0, "gpio_in"),
 		  SUNXI_FUNCTION(0x1, "gpio_out"),
 		  SUNXI_FUNCTION(0x2, "spi1"),		/* CS1 */
 		  SUNXI_FUNCTION(0x3, "ps2"),		/* SDA1 */
 		  SUNXI_FUNCTION(0x4, "timer5"),	/* TCLKIN1 */
-		  SUNXI_FUNCTION_IRQ(0x5, 27)),		/* EINT27 */
+		  SUNXI_FUNCTION_IRQ(0x6, 27)),		/* EINT27 */
 	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 16),
 		  SUNXI_FUNCTION(0x0, "gpio_in"),
 		  SUNXI_FUNCTION(0x1, "gpio_out"),
 		  SUNXI_FUNCTION(0x2, "spi1"),		/* CS0 */
 		  SUNXI_FUNCTION(0x3, "uart2"),		/* RTS */
-		  SUNXI_FUNCTION_IRQ(0x5, 28)),		/* EINT28 */
+		  SUNXI_FUNCTION_IRQ(0x6, 28)),		/* EINT28 */
 	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 17),
 		  SUNXI_FUNCTION(0x0, "gpio_in"),
 		  SUNXI_FUNCTION(0x1, "gpio_out"),
 		  SUNXI_FUNCTION(0x2, "spi1"),		/* CLK */
 		  SUNXI_FUNCTION(0x3, "uart2"),		/* CTS */
-		  SUNXI_FUNCTION_IRQ(0x5, 29)),		/* EINT29 */
+		  SUNXI_FUNCTION_IRQ(0x6, 29)),		/* EINT29 */
+		  /* EINT29 might not work - more testing needed */
 	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 18),
 		  SUNXI_FUNCTION(0x0, "gpio_in"),
 		  SUNXI_FUNCTION(0x1, "gpio_out"),
 		  SUNXI_FUNCTION(0x2, "spi1"),		/* MOSI */
 		  SUNXI_FUNCTION(0x3, "uart2"),		/* TX */
-		  SUNXI_FUNCTION_IRQ(0x5, 30)),		/* EINT30 */
+		  SUNXI_FUNCTION_IRQ(0x6, 30)),		/* EINT30 */
 	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 19),
 		  SUNXI_FUNCTION(0x0, "gpio_in"),
 		  SUNXI_FUNCTION(0x1, "gpio_out"),
 		  SUNXI_FUNCTION(0x2, "spi1"),		/* MISO */
 		  SUNXI_FUNCTION(0x3, "uart2"),		/* RX */
-		  SUNXI_FUNCTION_IRQ(0x5, 31)),		/* EINT31 */
+		  SUNXI_FUNCTION_IRQ(0x6, 31)),		/* EINT31 */
 	SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 20),
 		  SUNXI_FUNCTION(0x0, "gpio_in"),
 		  SUNXI_FUNCTION(0x1, "gpio_out"),
-- 
2.5.0

Re: [PATCH v3] Fix sun7i pin assignment for IRQ's

[Maxime Ripard]

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Hi,

On Sun, Feb 21, 2016 at 02:20:41PM +0100, Henry Paulissen wrote:
> After testing IRQ pins we found some bugs in the pinctrl declaration.

Your commit log is going to need some work. Which bugs? What tests did
you make? Why are you making these changes while the datasheet says
otherwise?

> Signed-off-by: Henry Paulissen <henry-oxlTVf6CAJF4HdFT58BDcQ@public.gmane.org>
> ---
> 
> Changes in v2:
>     After some more testing we found irq on PI pins.
>     they where on mux6 so this is included in my patch.
> 
>     Also included is a warning for PI17, this pin was not working
>     on apritzel his bPI and he thinks it might be correlated to
>     GIC and IRQ 29.
> 
> Changes in v3:
>     Changed name from nickname to realname in email and SoB.
> ---
>  drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c | 25 +++++++++++--------------
>  1 file changed, 11 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
> index cf1ce0c..0fe173e 100644
> --- a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
> +++ b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
> @@ -344,25 +344,21 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
>  		  SUNXI_FUNCTION(0x1, "gpio_out"),
>  		  SUNXI_FUNCTION(0x2, "nand0"),		/* NCE4 */
>  		  SUNXI_FUNCTION(0x3, "spi2"),		/* CS0 */
> -		  SUNXI_FUNCTION_IRQ(0x6, 12)),		/* EINT12 */

Have you tried to compile it?

Thanks,
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

Re: [PATCH v3] Fix sun7i pin assignment for IRQ's

[Henry Paulissen]

[-- Attachment #1.1: Type: text/plain, Size: 1964 bytes --]


Op zondag 21 februari 2016 18:18:37 UTC+1 schreef Maxime Ripard:

>
> Your commit log is going to need some work. Which bugs? What tests did 
> you make? Why are you making these changes while the datasheet says 
> otherwise? 
>

Its a fix for a not yet existing bug. I was fiddling around with IRQ's and 
couldn't get them to work.
I took a dumpster dive into it and found a shitload of contradicting 
manuals and datasheets.


Take for example the A20 user manual:
http://dl.linux-sunxi.org/A20/A20%20user%20manual%20v1.3%2020141010.pdf

(pin PI14)
Page 237: EINT26 is on mux *5* in the pin overview.
Page 288: EINT26 is on mux *6* in the registers.
 
Page 233: EINT12 is on pin PC19 mux6 in the pin overview.
Page 236: EINT12 is on pin PH12 mux6 in the pin overview.
Page 253: EINT12 is *not* on pin PC19 on the registers.
Page 281: EINT12 is on pin PH12 mux6 in the registers.

So manual may say otherwise, but I hope I have proven that the manual isn't 
to be trusted.

My patch is based onto testing from both me and Andre (apritzel).
He with a Banana PI M1 and me with a Cubietruck (both A20 soc).

We did a basic test by connecting a pulsing signal to a port and configure 
kernel to use irq.

e.g.
echo pin# > /sys/class/gpio/export
echo in > /sys/class/gpio/gpio#/direction
echo rising > /sys/class/gpio/gpio#/edge

and check on /proc/interrupts to see if a irq was attached and if it was 
receiving.

Im not sure what andre his pulse source was, but mine was a 1pps coming 
from a gps.



> Have you tried to compile it? 
>
>
Yes, otherwise we could have never confirmed that the irq's where on mux6 
for the PI ports.

Regards,
Henry

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Re: Re: [PATCH v3] Fix sun7i pin assignment for IRQ's

[Julian Calaby]

Hi Henry,

On Mon, Feb 22, 2016 at 6:27 AM, Henry Paulissen <henry-oxlTVf6CAJF4HdFT58BDcQ@public.gmane.org> wrote:
>
> Op zondag 21 februari 2016 18:18:37 UTC+1 schreef Maxime Ripard:
>>
>>
>> Your commit log is going to need some work. Which bugs? What tests did
>> you make? Why are you making these changes while the datasheet says
>> otherwise?
>
>
> Its a fix for a not yet existing bug. I was fiddling around with IRQ's and
> couldn't get them to work.
> I took a dumpster dive into it and found a shitload of contradicting manuals
> and datasheets.
>
>
> Take for example the A20 user manual:
> http://dl.linux-sunxi.org/A20/A20%20user%20manual%20v1.3%2020141010.pdf
>
> (pin PI14)
> Page 237: EINT26 is on mux *5* in the pin overview.
> Page 288: EINT26 is on mux *6* in the registers.
>
> Page 233: EINT12 is on pin PC19 mux6 in the pin overview.
> Page 236: EINT12 is on pin PH12 mux6 in the pin overview.
> Page 253: EINT12 is *not* on pin PC19 on the registers.
> Page 281: EINT12 is on pin PH12 mux6 in the registers.
>
> So manual may say otherwise, but I hope I have proven that the manual isn't
> to be trusted.
>
> My patch is based onto testing from both me and Andre (apritzel).
> He with a Banana PI M1 and me with a Cubietruck (both A20 soc).
>
> We did a basic test by connecting a pulsing signal to a port and configure
> kernel to use irq.
>
> e.g.
> echo pin# > /sys/class/gpio/export
> echo in > /sys/class/gpio/gpio#/direction
> echo rising > /sys/class/gpio/gpio#/edge
>
> and check on /proc/interrupts to see if a irq was attached and if it was
> receiving.
>
> Im not sure what andre his pulse source was, but mine was a 1pps coming from
> a gps.
>
>
>>
>> Have you tried to compile it?
>>
>
> Yes, otherwise we could have never confirmed that the irq's where on mux6
> for the PI ports.

I think Maxime is referring to the fact that your patch removes two
closing parenthesis when one would expect that you'd only remove one.

You have compiled the kernel with this patch applied and no other
modifications, right?

Thanks,

-- 
Julian Calaby

Email: julian.calaby-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
Profile: http://www.google.com/profiles/julian.calaby/

Re: Re: [PATCH v3] Fix sun7i pin assignment for IRQ's

[Henry Paulissen]

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Op zondag 21 februari 2016 22:55:31 UTC+1 schreef Julian Calaby:

>
> I think Maxime is referring to the fact that your patch removes two 
> closing parenthesis when one would expect that you'd only remove one. 
>
> You have compiled the kernel with this patch applied and no other 
> modifications, right? 
>   
>

Hmm, I see your (and Maxime his) point.
I guess the C bank changes made it into the diff after testing the build.

For what its worth, I corrected and completely checked the new upcoming 
diff.
My apologies.

Regards,
Henry Paulissen

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Re: Re: [PATCH v3] Fix sun7i pin assignment for IRQ's

[Krzysztof Adamski]

On Sun, Feb 21, 2016 at 11:27:46AM -0800, Henry Paulissen wrote:
>
>Op zondag 21 februari 2016 18:18:37 UTC+1 schreef Maxime Ripard:
>
>>
>> Your commit log is going to need some work. Which bugs? What tests did
>> you make? Why are you making these changes while the datasheet says
>> otherwise?
>>
>
>Its a fix for a not yet existing bug. I was fiddling around with IRQ's and
>couldn't get them to work.
>I took a dumpster dive into it and found a shitload of contradicting
>manuals and datasheets.
>
>
>Take for example the A20 user manual:
>http://dl.linux-sunxi.org/A20/A20%20user%20manual%20v1.3%2020141010.pdf
>
>(pin PI14)
>Page 237: EINT26 is on mux *5* in the pin overview.
>Page 288: EINT26 is on mux *6* in the registers.
>
>Page 233: EINT12 is on pin PC19 mux6 in the pin overview.
>Page 236: EINT12 is on pin PH12 mux6 in the pin overview.
>Page 253: EINT12 is *not* on pin PC19 on the registers.
>Page 281: EINT12 is on pin PH12 mux6 in the registers.
>
>So manual may say otherwise, but I hope I have proven that the manual isn't
>to be trusted.
>
>My patch is based onto testing from both me and Andre (apritzel).
>He with a Banana PI M1 and me with a Cubietruck (both A20 soc).
>
>We did a basic test by connecting a pulsing signal to a port and configure
>kernel to use irq.
>
>e.g.
>echo pin# > /sys/class/gpio/export
>echo in > /sys/class/gpio/gpio#/direction
>echo rising > /sys/class/gpio/gpio#/edge
>
>and check on /proc/interrupts to see if a irq was attached and if it was
>receiving.
>
>Im not sure what andre his pulse source was, but mine was a 1pps coming
>from a gps.

That's quite clear to anybody reading this mailinglist but it won't be 
to anyone reading just commit message (and there will be many of them).  
You should try to put some of this into the commit message.

Re: Re: [PATCH v3] Fix sun7i pin assignment for IRQ's

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 2360 bytes --]

Hi,

On Sun, Feb 21, 2016 at 11:27:46AM -0800, Henry Paulissen wrote:
> 
> Op zondag 21 februari 2016 18:18:37 UTC+1 schreef Maxime Ripard:
> 
> >
> > Your commit log is going to need some work. Which bugs? What tests did 
> > you make? Why are you making these changes while the datasheet says 
> > otherwise? 
> >
> 
> Its a fix for a not yet existing bug. I was fiddling around with IRQ's and 
> couldn't get them to work.
> I took a dumpster dive into it and found a shitload of contradicting 
> manuals and datasheets.
> 
> 
> Take for example the A20 user manual:
> http://dl.linux-sunxi.org/A20/A20%20user%20manual%20v1.3%2020141010.pdf
> 
> (pin PI14)
> Page 237: EINT26 is on mux *5* in the pin overview.
> Page 288: EINT26 is on mux *6* in the registers.
>  
> Page 233: EINT12 is on pin PC19 mux6 in the pin overview.
> Page 236: EINT12 is on pin PH12 mux6 in the pin overview.
> Page 253: EINT12 is *not* on pin PC19 on the registers.
> Page 281: EINT12 is on pin PH12 mux6 in the registers.

Ok, so i guess you're actually fixing two different things: the first
one is that some interrupts are using the wrong function, while some
others are just not there at all. It would be great if you could make
two different patches for these.

I guess we could also change SUNXI_FUNCTION_IRQ to enforce the mux
value 6, since you're removing the last users of a different value,
but that can be done as a followup

> So manual may say otherwise, but I hope I have proven that the manual isn't 
> to be trusted.
> 
> My patch is based onto testing from both me and Andre (apritzel).
> He with a Banana PI M1 and me with a Cubietruck (both A20 soc).
> 
> We did a basic test by connecting a pulsing signal to a port and configure 
> kernel to use irq.
> 
> e.g.
> echo pin# > /sys/class/gpio/export
> echo in > /sys/class/gpio/gpio#/direction
> echo rising > /sys/class/gpio/gpio#/edge
> 
> and check on /proc/interrupts to see if a irq was attached and if it was 
> receiving.
> 
> Im not sure what andre his pulse source was, but mine was a 1pps coming 
> from a gps.

That's a great explanation overall, it should just be in the commit
log itself. A git commit is easy to find, the discussion that was
triggered by it not so much.

Thanks!
Maxime


-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com