* [PATCH 01/17] pinctrl: qcom: ipq4019: set ngpios to correct value
[not found] <1458770712-10880-1-git-send-email-mmcclint@codeaurora.org>
@ 2016-03-23 22:04 ` Matthew McClintock
2016-03-25 21:19 ` Bjorn Andersson
2016-03-31 9:53 ` Linus Walleij
2016-03-23 22:04 ` [PATCH 02/17] pinctrl: qcom: ipq4019: fix the function enum for gpio mode Matthew McClintock
2016-03-23 22:04 ` [PATCH 03/17] pinctrl: qcom: ipq4019: fix register offsets Matthew McClintock
2 siblings, 2 replies; 9+ messages in thread
From: Matthew McClintock @ 2016-03-23 22:04 UTC (permalink / raw)
To: andy.gross, linux-arm-msm
Cc: qca-upstream.external, Matthew McClintock, linus.walleij,
bjorn.andersson, Sricharan R, Mathieu Olivari,
Varadarajan Narayanan, open list:PIN CONTROL SUBSYSTEM, open list
This should have been bumped to 100 when the extra pins
were added in the original pinctrl patch
CC: linus.walleij@linaro.org
CC: bjorn.andersson@linaro.org
Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
---
drivers/pinctrl/qcom/pinctrl-ipq4019.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
index b5d81ce..cb5f0a8 100644
--- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
+++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
@@ -414,7 +414,7 @@ static const struct msm_pinctrl_soc_data ipq4019_pinctrl = {
.nfunctions = ARRAY_SIZE(ipq4019_functions),
.groups = ipq4019_groups,
.ngroups = ARRAY_SIZE(ipq4019_groups),
- .ngpios = 70,
+ .ngpios = 100,
};
static int ipq4019_pinctrl_probe(struct platform_device *pdev)
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH 01/17] pinctrl: qcom: ipq4019: set ngpios to correct value
2016-03-23 22:04 ` [PATCH 01/17] pinctrl: qcom: ipq4019: set ngpios to correct value Matthew McClintock
@ 2016-03-25 21:19 ` Bjorn Andersson
2016-03-31 9:53 ` Linus Walleij
1 sibling, 0 replies; 9+ messages in thread
From: Bjorn Andersson @ 2016-03-25 21:19 UTC (permalink / raw)
To: Matthew McClintock
Cc: andy.gross, linux-arm-msm, qca-upstream.external, linus.walleij,
Sricharan R, Mathieu Olivari, Varadarajan Narayanan,
open list:PIN CONTROL SUBSYSTEM, open list
On Wed 23 Mar 15:04 PDT 2016, Matthew McClintock wrote:
> This should have been bumped to 100 when the extra pins
> were added in the original pinctrl patch
>
> CC: linus.walleij@linaro.org
Sorry for missing this in the initial review of this driver.
Acked-by: bjorn.andersson@linaro.org
Regards,
Bjorn
> Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
> ---
> drivers/pinctrl/qcom/pinctrl-ipq4019.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
> index b5d81ce..cb5f0a8 100644
> --- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
> +++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
> @@ -414,7 +414,7 @@ static const struct msm_pinctrl_soc_data ipq4019_pinctrl = {
> .nfunctions = ARRAY_SIZE(ipq4019_functions),
> .groups = ipq4019_groups,
> .ngroups = ARRAY_SIZE(ipq4019_groups),
> - .ngpios = 70,
> + .ngpios = 100,
> };
>
> static int ipq4019_pinctrl_probe(struct platform_device *pdev)
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH 01/17] pinctrl: qcom: ipq4019: set ngpios to correct value
2016-03-23 22:04 ` [PATCH 01/17] pinctrl: qcom: ipq4019: set ngpios to correct value Matthew McClintock
2016-03-25 21:19 ` Bjorn Andersson
@ 2016-03-31 9:53 ` Linus Walleij
1 sibling, 0 replies; 9+ messages in thread
From: Linus Walleij @ 2016-03-31 9:53 UTC (permalink / raw)
To: Matthew McClintock
Cc: Andy Gross, linux-arm-msm@vger.kernel.org, qca-upstream.external,
Bjorn Andersson, Sricharan R, Mathieu Olivari,
Varadarajan Narayanan, open list:PIN CONTROL SUBSYSTEM, open list
On Wed, Mar 23, 2016 at 11:04 PM, Matthew McClintock
<mmcclint@codeaurora.org> wrote:
> This should have been bumped to 100 when the extra pins
> were added in the original pinctrl patch
>
> CC: linus.walleij@linaro.org
> CC: bjorn.andersson@linaro.org
> Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
Patch applied for fixes with Björn's ACK.
Yours,
Linus Walleij
--
To unsubscribe from this list: send the line "unsubscribe linux-gpio" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 02/17] pinctrl: qcom: ipq4019: fix the function enum for gpio mode
[not found] <1458770712-10880-1-git-send-email-mmcclint@codeaurora.org>
2016-03-23 22:04 ` [PATCH 01/17] pinctrl: qcom: ipq4019: set ngpios to correct value Matthew McClintock
@ 2016-03-23 22:04 ` Matthew McClintock
2016-03-25 21:22 ` Bjorn Andersson
2016-03-31 9:55 ` Linus Walleij
2016-03-23 22:04 ` [PATCH 03/17] pinctrl: qcom: ipq4019: fix register offsets Matthew McClintock
2 siblings, 2 replies; 9+ messages in thread
From: Matthew McClintock @ 2016-03-23 22:04 UTC (permalink / raw)
To: andy.gross, linux-arm-msm
Cc: qca-upstream.external, Matthew McClintock, linus.walleij,
bjorn.andersson, Rob Herring, Varadarajan Narayanan,
Mathieu Olivari, open list:PIN CONTROL SUBSYSTEM, open list
Without this, we would fail to set the mode to gpio if trying to
configure for that mode
CC: linus.walleij@linaro.org
CC: bjorn.andersson@linaro.org
Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
---
drivers/pinctrl/qcom/pinctrl-ipq4019.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
index cb5f0a8..cb9f16a 100644
--- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
+++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
@@ -237,7 +237,7 @@ DECLARE_QCA_GPIO_PINS(99);
.pins = gpio##id##_pins, \
.npins = (unsigned)ARRAY_SIZE(gpio##id##_pins), \
.funcs = (int[]){ \
- qca_mux_NA, /* gpio mode */ \
+ qca_mux_gpio, /* gpio mode */ \
qca_mux_##f1, \
qca_mux_##f2, \
qca_mux_##f3, \
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH 02/17] pinctrl: qcom: ipq4019: fix the function enum for gpio mode
2016-03-23 22:04 ` [PATCH 02/17] pinctrl: qcom: ipq4019: fix the function enum for gpio mode Matthew McClintock
@ 2016-03-25 21:22 ` Bjorn Andersson
2016-03-31 9:55 ` Linus Walleij
1 sibling, 0 replies; 9+ messages in thread
From: Bjorn Andersson @ 2016-03-25 21:22 UTC (permalink / raw)
To: Matthew McClintock, linus.walleij
Cc: andy.gross, linux-arm-msm, qca-upstream.external, Rob Herring,
Varadarajan Narayanan, Mathieu Olivari,
open list:PIN CONTROL SUBSYSTEM, open list
On Wed 23 Mar 15:04 PDT 2016, Matthew McClintock wrote:
> Without this, we would fail to set the mode to gpio if trying to
> configure for that mode
>
> CC: linus.walleij@linaro.org
Linus is the maintainer of the pinctrl subsystem, as such you should
have him as recipient of these patches - so that he doesn't miss them
while being only Cc.
Acked-by: bjorn.andersson@linaro.org
Regards,
Bjorn
> Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
> ---
> drivers/pinctrl/qcom/pinctrl-ipq4019.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
> index cb5f0a8..cb9f16a 100644
> --- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
> +++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
> @@ -237,7 +237,7 @@ DECLARE_QCA_GPIO_PINS(99);
> .pins = gpio##id##_pins, \
> .npins = (unsigned)ARRAY_SIZE(gpio##id##_pins), \
> .funcs = (int[]){ \
> - qca_mux_NA, /* gpio mode */ \
> + qca_mux_gpio, /* gpio mode */ \
> qca_mux_##f1, \
> qca_mux_##f2, \
> qca_mux_##f3, \
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH 02/17] pinctrl: qcom: ipq4019: fix the function enum for gpio mode
2016-03-23 22:04 ` [PATCH 02/17] pinctrl: qcom: ipq4019: fix the function enum for gpio mode Matthew McClintock
2016-03-25 21:22 ` Bjorn Andersson
@ 2016-03-31 9:55 ` Linus Walleij
1 sibling, 0 replies; 9+ messages in thread
From: Linus Walleij @ 2016-03-31 9:55 UTC (permalink / raw)
To: Matthew McClintock
Cc: Andy Gross, linux-arm-msm@vger.kernel.org, qca-upstream.external,
Bjorn Andersson, Rob Herring, Varadarajan Narayanan,
Mathieu Olivari, open list:PIN CONTROL SUBSYSTEM, open list
On Wed, Mar 23, 2016 at 11:04 PM, Matthew McClintock
<mmcclint@codeaurora.org> wrote:
> Without this, we would fail to set the mode to gpio if trying to
> configure for that mode
>
> CC: linus.walleij@linaro.org
> CC: bjorn.andersson@linaro.org
> Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
Patch applied for fixes with Björn's ACK.
Yours,
Linus Walleij
--
To unsubscribe from this list: send the line "unsubscribe linux-gpio" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 03/17] pinctrl: qcom: ipq4019: fix register offsets
[not found] <1458770712-10880-1-git-send-email-mmcclint@codeaurora.org>
2016-03-23 22:04 ` [PATCH 01/17] pinctrl: qcom: ipq4019: set ngpios to correct value Matthew McClintock
2016-03-23 22:04 ` [PATCH 02/17] pinctrl: qcom: ipq4019: fix the function enum for gpio mode Matthew McClintock
@ 2016-03-23 22:04 ` Matthew McClintock
2016-03-25 21:31 ` Bjorn Andersson
2016-03-31 9:57 ` Linus Walleij
2 siblings, 2 replies; 9+ messages in thread
From: Matthew McClintock @ 2016-03-23 22:04 UTC (permalink / raw)
To: andy.gross, linux-arm-msm
Cc: qca-upstream.external, Matthew McClintock, linus.walleij,
bjorn.andersson, Sricharan R, Rob Herring, Mathieu Olivari,
Varadarajan Narayanan, open list:PIN CONTROL SUBSYSTEM, open list
For this SoC the register offsets changed from previous versions to be
separated by a larger amount.
CC: linus.walleij@linaro.org
CC: bjorn.andersson@linaro.org
Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
---
drivers/pinctrl/qcom/pinctrl-ipq4019.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
index cb9f16a..b68ae42 100644
--- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
+++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
@@ -254,11 +254,11 @@ DECLARE_QCA_GPIO_PINS(99);
qca_mux_##f14 \
}, \
.nfuncs = 15, \
- .ctl_reg = 0x1000 + 0x10 * id, \
- .io_reg = 0x1004 + 0x10 * id, \
- .intr_cfg_reg = 0x1008 + 0x10 * id, \
- .intr_status_reg = 0x100c + 0x10 * id, \
- .intr_target_reg = 0x400 + 0x4 * id, \
+ .ctl_reg = 0x0 + 0x1000 * id, \
+ .io_reg = 0x4 + 0x1000 * id, \
+ .intr_cfg_reg = 0x8 + 0x1000 * id, \
+ .intr_status_reg = 0xc + 0x1000 * id, \
+ .intr_target_reg = 0x8 + 0x1000 * id, \
.mux_bit = 2, \
.pull_bit = 0, \
.drv_bit = 6, \
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH 03/17] pinctrl: qcom: ipq4019: fix register offsets
2016-03-23 22:04 ` [PATCH 03/17] pinctrl: qcom: ipq4019: fix register offsets Matthew McClintock
@ 2016-03-25 21:31 ` Bjorn Andersson
2016-03-31 9:57 ` Linus Walleij
1 sibling, 0 replies; 9+ messages in thread
From: Bjorn Andersson @ 2016-03-25 21:31 UTC (permalink / raw)
To: Matthew McClintock, linus.walleij
Cc: andy.gross, linux-arm-msm, qca-upstream.external, Sricharan R,
Rob Herring, Mathieu Olivari, Varadarajan Narayanan,
open list:PIN CONTROL SUBSYSTEM, open list
On Wed 23 Mar 15:04 PDT 2016, Matthew McClintock wrote:
> For this SoC the register offsets changed from previous versions to be
> separated by a larger amount.
>
> CC: linus.walleij@linaro.org
So the HW guys changed the register layout of the TLMM block? Matches
the layout of contemporary MSMs, so I see no problems with this.
Acked-by: bjorn.andersson@linaro.org
Regards,
Bjorn
> Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
> ---
> drivers/pinctrl/qcom/pinctrl-ipq4019.c | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
> index cb9f16a..b68ae42 100644
> --- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
> +++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
> @@ -254,11 +254,11 @@ DECLARE_QCA_GPIO_PINS(99);
> qca_mux_##f14 \
> }, \
> .nfuncs = 15, \
> - .ctl_reg = 0x1000 + 0x10 * id, \
> - .io_reg = 0x1004 + 0x10 * id, \
> - .intr_cfg_reg = 0x1008 + 0x10 * id, \
> - .intr_status_reg = 0x100c + 0x10 * id, \
> - .intr_target_reg = 0x400 + 0x4 * id, \
> + .ctl_reg = 0x0 + 0x1000 * id, \
> + .io_reg = 0x4 + 0x1000 * id, \
> + .intr_cfg_reg = 0x8 + 0x1000 * id, \
> + .intr_status_reg = 0xc + 0x1000 * id, \
> + .intr_target_reg = 0x8 + 0x1000 * id, \
> .mux_bit = 2, \
> .pull_bit = 0, \
> .drv_bit = 6, \
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 03/17] pinctrl: qcom: ipq4019: fix register offsets
2016-03-23 22:04 ` [PATCH 03/17] pinctrl: qcom: ipq4019: fix register offsets Matthew McClintock
2016-03-25 21:31 ` Bjorn Andersson
@ 2016-03-31 9:57 ` Linus Walleij
1 sibling, 0 replies; 9+ messages in thread
From: Linus Walleij @ 2016-03-31 9:57 UTC (permalink / raw)
To: Matthew McClintock
Cc: Andy Gross, linux-arm-msm@vger.kernel.org, qca-upstream.external,
Bjorn Andersson, Sricharan R, Rob Herring, Mathieu Olivari,
Varadarajan Narayanan, open list:PIN CONTROL SUBSYSTEM, open list
On Wed, Mar 23, 2016 at 11:04 PM, Matthew McClintock
<mmcclint@codeaurora.org> wrote:
> For this SoC the register offsets changed from previous versions to be
> separated by a larger amount.
>
> CC: linus.walleij@linaro.org
> CC: bjorn.andersson@linaro.org
> Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
Patch applied for fixes with Björn's ACK.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 9+ messages in thread