From: "Niklas Söderlund" <niklas.soderlund+renesas@ragnatech.se>
To: geert+renesas@glider.be, linux-renesas-soc@vger.kernel.org,
linux-gpio@vger.kernel.org
Cc: laurent.pinchart@ideasonboard.com, linus.walleij@linaro.org,
"Niklas Söderlund" <niklas.soderlund+renesas@ragnatech.se>
Subject: [PATCH 1/4] pinctrl: sh-pfc: Support named pins with custom configuration
Date: Tue, 13 Sep 2016 16:03:11 +0200 [thread overview]
Message-ID: <20160913140314.22035-2-niklas.soderlund+renesas@ragnatech.se> (raw)
In-Reply-To: <20160913140314.22035-1-niklas.soderlund+renesas@ragnatech.se>
Pins not associated with a GPIO port can still have other configuration
parameters. Add a new macro SH_PFC_PIN_NAMED_CFG which allows for named
pins to be declared with a set of configurations. The new macro is an
modification of SH_PFC_PIN_NAMED to allow for optional configuration to
be assigned.
The flag SH_PFC_PIN_CFG_NO_GPIO is still enforced as this should only be
used to define pins not associated with a GPIO port.
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
---
drivers/pinctrl/sh-pfc/sh_pfc.h | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index 5e966c0..a6a2346 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -507,6 +507,14 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
.configs = SH_PFC_PIN_CFG_NO_GPIO, \
}
+/* SH_PFC_PIN_NAMED_CFG - Expand to a sh_pfc_pin entry with the given name */
+#define SH_PFC_PIN_NAMED_CFG(row, col, _name, cfgs) \
+ { \
+ .pin = PIN_NUMBER(row, col), \
+ .name = __stringify(PIN_##_name), \
+ .configs = SH_PFC_PIN_CFG_NO_GPIO | cfgs, \
+ }
+
/* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0,
* PORT_name_OUT, PORT_name_IN marks
*/
--
2.9.3
next prev parent reply other threads:[~2016-09-13 14:03 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-09-13 14:03 [PATCH 0/4] pinctrl: sh-pfc: r8a7795: Support none GPIO pins with configurable drive-strength Niklas Söderlund
2016-09-13 14:03 ` Niklas Söderlund [this message]
2016-09-13 14:28 ` [PATCH 1/4] pinctrl: sh-pfc: Support named pins with custom configuration Laurent Pinchart
2016-10-04 19:08 ` Geert Uytterhoeven
2016-09-13 14:03 ` [PATCH 2/4] pinctrl: sh-pfc: r8a7795: Support none GPIO pins with configurable drive-strength Niklas Söderlund
2016-10-04 19:13 ` Geert Uytterhoeven
2016-10-05 8:33 ` Niklas Söderlund
2016-10-05 9:51 ` Geert Uytterhoeven
2016-10-05 10:12 ` Laurent Pinchart
2016-10-06 9:27 ` Niklas Söderlund
2016-09-13 14:03 ` [PATCH 3/4] pinctrl: sh-pfc: r8a7795: Add group for AVB MDIO and MII pins Niklas Söderlund
2016-09-14 9:05 ` Sergei Shtylyov
2016-10-05 7:41 ` Geert Uytterhoeven
2016-09-13 14:03 ` [PATCH 4/4] pinctrl: sh-pfc: r8a7795: Add group for QSPI0 and QSPI1 pins Niklas Söderlund
2016-10-05 7:33 ` Geert Uytterhoeven
2016-10-04 19:09 ` [PATCH 0/4] pinctrl: sh-pfc: r8a7795: Support none GPIO pins with configurable drive-strength Geert Uytterhoeven
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