* [PATCHv2 0/5] Support for Marvell switches with integrated CPUs
@ 2017-01-05 3:36 Chris Packham
2017-01-05 3:36 ` [PATCHv2 3/5] pinctrl: mvebu: pinctrl driver for 98DX3236 SoC Chris Packham
` (3 more replies)
0 siblings, 4 replies; 16+ messages in thread
From: Chris Packham @ 2017-01-05 3:36 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: Chris Packham, Rob Herring, Mark Rutland, Michael Turquette,
Stephen Boyd, Linus Walleij, Jason Cooper, Andrew Lunn,
Gregory Clement, Sebastian Hesselbarth, Russell King,
Geert Uytterhoeven, Chris Brand, Florian Fainelli, Arnd Bergmann,
Thierry Reding, Sudeep Holla, Juri Lelli,
Thomas Petazzoni <thomas.
The 98DX3236, 98DX3336 and 98DX4251 are a set of switch ASICs with
integrated CPUs. They CPU block is common within these product lines and
(as far as I can tell/have been told) is based on the Armada XP. There
are a few differences due to the fact they have to squeeze the CPU into
the same package as the switch.
Chris Packham (4):
clk: mvebu: support for 98DX3236 SoC
arm: mvebu: support for SMP on 98DX3336 SoC
arm: mvebu: Add device tree for 98DX3236 SoCs
arm: mvebu: Add device tree for db-dxbc2 and db-xc3-24g4xg boards
Kalyan Kinthada (1):
pinctrl: mvebu: pinctrl driver for 98DX3236 SoC
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
.../bindings/arm/marvell/98dx3236-resume-ctrl.txt | 18 ++
.../devicetree/bindings/arm/marvell/98dx3236.txt | 23 ++
.../devicetree/bindings/clock/mvebu-cpu-clock.txt | 1 +
.../pinctrl/marvell,armada-98dx3236-pinctrl.txt | 46 ++++
arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 247 +++++++++++++++++++++
arch/arm/boot/dts/armada-xp-98dx3336.dtsi | 78 +++++++
arch/arm/boot/dts/armada-xp-98dx4251.dtsi | 92 ++++++++
arch/arm/boot/dts/db-dxbc2.dts | 159 +++++++++++++
arch/arm/boot/dts/db-xc3-24g4xg.dts | 155 +++++++++++++
arch/arm/mach-mvebu/Makefile | 1 +
arch/arm/mach-mvebu/common.h | 1 +
arch/arm/mach-mvebu/platsmp.c | 43 ++++
arch/arm/mach-mvebu/pmsu-98dx3236.c | 69 ++++++
drivers/clk/mvebu/Makefile | 2 +-
drivers/clk/mvebu/armada-xp.c | 42 ++++
drivers/clk/mvebu/clk-cpu.c | 33 ++-
drivers/clk/mvebu/mv98dx3236-corediv.c | 207 +++++++++++++++++
drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 155 +++++++++++++
19 files changed, 1369 insertions(+), 4 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
create mode 100644 Documentation/devicetree/bindings/arm/marvell/98dx3236.txt
create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
create mode 100644 arch/arm/boot/dts/armada-xp-98dx3236.dtsi
create mode 100644 arch/arm/boot/dts/armada-xp-98dx3336.dtsi
create mode 100644 arch/arm/boot/dts/armada-xp-98dx4251.dtsi
create mode 100644 arch/arm/boot/dts/db-dxbc2.dts
create mode 100644 arch/arm/boot/dts/db-xc3-24g4xg.dts
create mode 100644 arch/arm/mach-mvebu/pmsu-98dx3236.c
create mode 100644 drivers/clk/mvebu/mv98dx3236-corediv.c
--
2.11.0.24.ge6920cf
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^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCHv2 3/5] pinctrl: mvebu: pinctrl driver for 98DX3236 SoC 2017-01-05 3:36 [PATCHv2 0/5] Support for Marvell switches with integrated CPUs Chris Packham @ 2017-01-05 3:36 ` Chris Packham 2017-01-05 4:07 ` [PATCHv2 0/5] Support for Marvell switches with integrated CPUs Florian Fainelli ` (2 subsequent siblings) 3 siblings, 0 replies; 16+ messages in thread From: Chris Packham @ 2017-01-05 3:36 UTC (permalink / raw) To: linux-arm-kernel Cc: Kalyan Kinthada, Chris Packham, Linus Walleij, Rob Herring, Mark Rutland, Laxman Dewangan, Thomas Petazzoni, linux-gpio, devicetree, linux-kernel From: Kalyan Kinthada <kalyan.kinthada@alliedtelesis.co.nz> This pinctrl driver supports the 98DX3236, 98DX3336 and 98DX4251 SoCs from Marvell. Signed-off-by: Kalyan Kinthada <kalyan.kinthada@alliedtelesis.co.nz> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> --- Changes in v2: - include sdio support for the 98DX4251 .../pinctrl/marvell,armada-98dx3236-pinctrl.txt | 46 ++++++ drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 155 +++++++++++++++++++++ 2 files changed, 201 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt new file mode 100644 index 000000000000..d4e6ecdfc853 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt @@ -0,0 +1,46 @@ +* Marvell 98dx3236 pinctrl driver for mpp + +Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding +part and usage + +Required properties: +- compatible: "marvell,98dx3236-pinctrl" or "marvell,98dx4251-pinctrl" +- reg: register specifier of MPP registers + +This driver supports all 98dx3236, 98dx3336 and 98dx4251 variants + +name pins functions +================================================================================ +mpp0 0 gpio, spi0(mosi), dev(ad8) +mpp1 1 gpio, spi0(miso), dev(ad9) +mpp2 2 gpio, spi0(sck), dev(ad10) +mpp3 3 gpio, spi0(cs0), dev(ad11) +mpp4 4 gpio, spi0(cs1), smi(mdc), dev(cs0) +mpp5 5 gpio, pex(rsto), sd0(cmd), dev(bootcs) +mpp6 6 gpio, sd0(clk), dev(a2) +mpp7 7 gpio, sd0(d0), dev(ale0) +mpp8 8 gpio, sd0(d1), dev(ale1) +mpp9 9 gpio, sd0(d2), dev(ready0) +mpp10 10 gpio, sd0(d3), dev(ad12) +mpp11 11 gpio, uart1(rxd), uart0(cts), dev(ad13) +mpp12 12 gpio, uart1(txd), uart0(rts), dev(ad14) +mpp13 13 gpio, intr(out), dev(ad15) +mpp14 14 gpio, i2c0(sck) +mpp15 15 gpio, i2c0(sda) +mpp16 16 gpio, dev(oe) +mpp17 17 gpio, dev(clk) +mpp18 18 gpio, uart1(txd) +mpp19 19 gpio, uart1(rxd), dev(rb) +mpp20 20 gpio, dev(we) +mpp21 21 gpio, dev(ad0) +mpp22 22 gpio, dev(ad1) +mpp23 23 gpio, dev(ad2) +mpp24 24 gpio, dev(ad3) +mpp25 25 gpio, dev(ad4) +mpp26 26 gpio, dev(ad5) +mpp27 27 gpio, dev(ad6) +mpp28 28 gpio, dev(ad7) +mpp29 29 gpio, dev(a0) +mpp30 30 gpio, dev(a1) +mpp31 31 gpio, slv_smi(mdc), smi(mdc), dev(we1) +mpp32 32 gpio, slv_smi(mdio), smi(mdio), dev(cs1) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c index e4ea71a9d985..554eeae8cd21 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c @@ -49,6 +49,10 @@ enum armada_xp_variant { V_MV78460 = BIT(2), V_MV78230_PLUS = (V_MV78230 | V_MV78260 | V_MV78460), V_MV78260_PLUS = (V_MV78260 | V_MV78460), + V_98DX3236 = BIT(3), + V_98DX3336 = BIT(4), + V_98DX4251 = BIT(5), + V_98DX3236_PLUS = (V_98DX3236 | V_98DX3336 | V_98DX4251), }; static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { @@ -360,6 +364,130 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x1, "dev", "ad31", V_MV78260_PLUS)), }; +static struct mvebu_mpp_mode mv98dx3236_mpp_modes[] = { + MPP_MODE(0, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "spi0", "mosi", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "ad8", V_98DX3236_PLUS)), + MPP_MODE(1, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "spi0", "miso", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "ad9", V_98DX3236_PLUS)), + MPP_MODE(2, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "spi0", "csk", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "ad10", V_98DX3236_PLUS)), + MPP_MODE(3, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "spi0", "cs0", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "ad11", V_98DX3236_PLUS)), + MPP_MODE(4, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "spi0", "cs1", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x3, "smi", "mdc", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "cs0", V_98DX3236_PLUS)), + MPP_MODE(5, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "pex", "rsto", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "sd0", "cmd", V_98DX4251), + MPP_VAR_FUNCTION(0x4, "dev", "bootcs0", V_98DX3236_PLUS)), + MPP_MODE(6, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "sd0", "clk", V_98DX4251), + MPP_VAR_FUNCTION(0x4, "dev", "a2", V_98DX3236_PLUS)), + MPP_MODE(7, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "sd0", "d0", V_98DX4251), + MPP_VAR_FUNCTION(0x4, "dev", "ale0", V_98DX3236_PLUS)), + MPP_MODE(8, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "sd0", "d1", V_98DX4251), + MPP_VAR_FUNCTION(0x4, "dev", "ale1", V_98DX3236_PLUS)), + MPP_MODE(9, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "sd0", "d2", V_98DX4251), + MPP_VAR_FUNCTION(0x4, "dev", "ready0", V_98DX3236_PLUS)), + MPP_MODE(10, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "sd0", "d3", V_98DX4251), + MPP_VAR_FUNCTION(0x4, "dev", "ad12", V_98DX3236_PLUS)), + MPP_MODE(11, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "uart1", "rxd", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x3, "uart0", "cts", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "ad13", V_98DX3236_PLUS)), + MPP_MODE(12, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "uart1", "txd", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x3, "uart0", "rts", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "ad14", V_98DX3236_PLUS)), + MPP_MODE(13, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "intr", "out", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "ad15", V_98DX3236_PLUS)), + MPP_MODE(14, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "i2c0", "sck", V_98DX3236_PLUS)), + MPP_MODE(15, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "i2c0", "sda", V_98DX3236_PLUS)), + MPP_MODE(16, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "oe", V_98DX3236_PLUS)), + MPP_MODE(17, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "clkout", V_98DX3236_PLUS)), + MPP_MODE(18, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x3, "uart1", "txd", V_98DX3236_PLUS)), + MPP_MODE(19, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V_98DX3236_PLUS)), + MPP_MODE(20, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "we0", V_98DX3236_PLUS)), + MPP_MODE(21, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "dev", "ad0", V_98DX3236_PLUS)), + MPP_MODE(22, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "dev", "ad1", V_98DX3236_PLUS)), + MPP_MODE(23, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "dev", "ad2", V_98DX3236_PLUS)), + MPP_MODE(24, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "dev", "ad3", V_98DX3236_PLUS)), + MPP_MODE(25, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "dev", "ad4", V_98DX3236_PLUS)), + MPP_MODE(26, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "dev", "ad5", V_98DX3236_PLUS)), + MPP_MODE(27, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "dev", "ad6", V_98DX3236_PLUS)), + MPP_MODE(28, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "dev", "ad7", V_98DX3236_PLUS)), + MPP_MODE(29, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "dev", "a0", V_98DX3236_PLUS)), + MPP_MODE(30, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "dev", "a1", V_98DX3236_PLUS)), + MPP_MODE(31, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "slv_smi", "mdc", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x3, "smi", "mdc", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "we1", V_98DX3236_PLUS)), + MPP_MODE(32, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "slv_smi", "mdio", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x3, "smi", "mdio", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "cs1", V_98DX3236_PLUS)), +}; + static struct mvebu_pinctrl_soc_info armada_xp_pinctrl_info; static const struct of_device_id armada_xp_pinctrl_of_match[] = { @@ -375,6 +503,14 @@ static const struct of_device_id armada_xp_pinctrl_of_match[] = { .compatible = "marvell,mv78460-pinctrl", .data = (void *) V_MV78460, }, + { + .compatible = "marvell,98dx3236-pinctrl", + .data = (void *) V_98DX3236, + }, + { + .compatible = "marvell,98dx4251-pinctrl", + .data = (void *) V_98DX4251, + }, { }, }; @@ -407,6 +543,14 @@ static struct pinctrl_gpio_range mv78460_mpp_gpio_ranges[] = { MPP_GPIO_RANGE(2, 64, 64, 3), }; +static struct mvebu_mpp_ctrl mv98dx3236_mpp_controls[] = { + MPP_FUNC_CTRL(0, 32, NULL, armada_xp_mpp_ctrl), +}; + +static struct pinctrl_gpio_range mv98dx3236_mpp_gpio_ranges[] = { + MPP_GPIO_RANGE(0, 0, 0, 32), +}; + static int armada_xp_pinctrl_suspend(struct platform_device *pdev, pm_message_t state) { @@ -488,6 +632,17 @@ static int armada_xp_pinctrl_probe(struct platform_device *pdev) soc->gpioranges = mv78460_mpp_gpio_ranges; soc->ngpioranges = ARRAY_SIZE(mv78460_mpp_gpio_ranges); break; + case V_98DX3236: + case V_98DX3336: + case V_98DX4251: + /* fall-through */ + soc->controls = mv98dx3236_mpp_controls; + soc->ncontrols = ARRAY_SIZE(mv98dx3236_mpp_controls); + soc->modes = mv98dx3236_mpp_modes; + soc->nmodes = mv98dx3236_mpp_controls[0].npins; + soc->gpioranges = mv98dx3236_mpp_gpio_ranges; + soc->ngpioranges = ARRAY_SIZE(mv98dx3236_mpp_gpio_ranges); + break; } nregs = DIV_ROUND_UP(soc->nmodes, MVEBU_MPPS_PER_REG); -- 2.11.0.24.ge6920cf ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCHv2 0/5] Support for Marvell switches with integrated CPUs 2017-01-05 3:36 [PATCHv2 0/5] Support for Marvell switches with integrated CPUs Chris Packham 2017-01-05 3:36 ` [PATCHv2 3/5] pinctrl: mvebu: pinctrl driver for 98DX3236 SoC Chris Packham @ 2017-01-05 4:07 ` Florian Fainelli 2017-01-05 4:24 ` Chris Packham 2017-01-05 14:09 ` Marcin Wojtas 2017-01-06 4:14 ` Chris Packham 3 siblings, 1 reply; 16+ messages in thread From: Florian Fainelli @ 2017-01-05 4:07 UTC (permalink / raw) To: Chris Packham, linux-arm-kernel Cc: Mark Rutland, Andrew Lunn, Geert Uytterhoeven, Michael Turquette, Laxman Dewangan, linux-clk, Juri Lelli, Russell King, Thierry Reding, Linus Walleij, Sebastian Hesselbarth, devicetree, Jason Cooper, Arnd Bergmann, Kalyan Kinthada, Rob Herring, Gregory Clement, Thomas Petazzoni, linux-gpio, Stephen Boyd, linux-kernel, Sudeep Holla Le 01/04/17 à 19:36, Chris Packham a écrit : > The 98DX3236, 98DX3336 and 98DX4251 are a set of switch ASICs with > integrated CPUs. They CPU block is common within these product lines and > (as far as I can tell/have been told) is based on the Armada XP. There > are a few differences due to the fact they have to squeeze the CPU into > the same package as the switch. It's really great to see these changes, do you have a plan to also add support for the integrated switch using a DSA/switchdev driver? Thanks! -- Florian _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCHv2 0/5] Support for Marvell switches with integrated CPUs 2017-01-05 4:07 ` [PATCHv2 0/5] Support for Marvell switches with integrated CPUs Florian Fainelli @ 2017-01-05 4:24 ` Chris Packham 2017-01-05 13:09 ` Andrew Lunn 0 siblings, 1 reply; 16+ messages in thread From: Chris Packham @ 2017-01-05 4:24 UTC (permalink / raw) To: Florian Fainelli, linux-arm-kernel@lists.infradead.org Cc: Mark Rutland, Andrew Lunn, Geert Uytterhoeven, Michael Turquette, Laxman Dewangan, linux-clk@vger.kernel.org, Juri Lelli, Russell King, Thierry Reding, Linus Walleij, Sebastian Hesselbarth, devicetree@vger.kernel.org, Jason Cooper, Arnd Bergmann, Kalyan Kinthada, Rob Herring, Gregory Clement, Thomas Petazzoni, linux-gpio@vger.kernel.org, Stephen Boyd On 05/01/17 17:07, Florian Fainelli wrote: > Le 01/04/17 à 19:36, Chris Packham a écrit : >> The 98DX3236, 98DX3336 and 98DX4251 are a set of switch ASICs with >> integrated CPUs. They CPU block is common within these product lines and >> (as far as I can tell/have been told) is based on the Armada XP. There >> are a few differences due to the fact they have to squeeze the CPU into >> the same package as the switch. > > It's really great to see these changes, do you have a plan to also add > support for the integrated switch using a DSA/switchdev driver? I'd love to see a switchdev driver but it's a huge task (and no I'm not committing to writing it). As it stands Marvell ship a switch SDK largely executes in userspace with a small kernel module providing some linkage to the underlying hardware. We (a few of us here at Allied Telesis NZ) have discussed switchdev and how we get from using Marvell's SDK in our products to using switchdev proper. The first step would probably be some kind of trampoline driver which communicates with a userspace helper to do the actual work. Alternatively there is some support in Marvell's SDK for compilation as a binary blob so a proprietary kernel module is another option. Neither of these are particularly nice in a free software world. A full "free" implementation would be a large undertaking. Ideally I'd like to see Marvell involved with producing one but so far they've not been interested whenever I've brought it up. ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCHv2 0/5] Support for Marvell switches with integrated CPUs 2017-01-05 4:24 ` Chris Packham @ 2017-01-05 13:09 ` Andrew Lunn 2017-01-05 14:07 ` Marcin Wojtas 2017-01-05 19:46 ` Chris Packham 0 siblings, 2 replies; 16+ messages in thread From: Andrew Lunn @ 2017-01-05 13:09 UTC (permalink / raw) To: Chris Packham Cc: Mark Rutland, Geert Uytterhoeven, Michael Turquette, Laxman Dewangan, linux-clk@vger.kernel.org, Florian Fainelli, Juri Lelli, Russell King, Thierry Reding, Linus Walleij, Sebastian Hesselbarth, devicetree@vger.kernel.org, Jason Cooper, Arnd Bergmann, Kalyan Kinthada, Rob Herring, Gregory Clement, linux-arm-kernel@lists.infradead.org, Thomas Petazzoni > I'd love to see a switchdev driver but it's a huge task (and no I'm not > committing to writing it). As it stands Marvell ship a switch SDK > largely executes in userspace with a small kernel module providing some > linkage to the underlying hardware. Is there any similarity to the mv88e6xxx family? If it was similar registers, just a different access mechanising, we could probably extend the mv88e6xxx to support MMIO as well as MDIO. Andrew ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCHv2 0/5] Support for Marvell switches with integrated CPUs 2017-01-05 13:09 ` Andrew Lunn @ 2017-01-05 14:07 ` Marcin Wojtas 2017-01-05 19:46 ` Chris Packham 1 sibling, 0 replies; 16+ messages in thread From: Marcin Wojtas @ 2017-01-05 14:07 UTC (permalink / raw) To: Andrew Lunn Cc: Chris Packham, Mark Rutland, Geert Uytterhoeven, Michael Turquette, Laxman Dewangan, linux-clk@vger.kernel.org, Florian Fainelli, Juri Lelli, Russell King, Thierry Reding, Linus Walleij, Sebastian Hesselbarth, devicetree@vger.kernel.org, Jason Cooper, Arnd Bergmann, Kalyan Kinthada, Rob Herring, Gregory Clement <gre> Hi Andrew, 2017-01-05 14:09 GMT+01:00 Andrew Lunn <andrew@lunn.ch>: >> I'd love to see a switchdev driver but it's a huge task (and no I'm not >> committing to writing it). As it stands Marvell ship a switch SDK >> largely executes in userspace with a small kernel module providing some >> linkage to the underlying hardware. > > Is there any similarity to the mv88e6xxx family? Prestera switches (they are sold as standalone devices and with integrated CPU's, like ones submitted) are as far from mv88e6xxx as possible. There are various mix of 1/2.5/10/40G ports, depending on model. > > If it was similar registers, just a different access mechanising, we > could probably extend the mv88e6xxx to support MMIO as well as MDIO. > The difference is huge, nothing existing in the mainline can fit. The driver, that exposes resources to the userspace SDK (called CPSS, it's huge and complex piece of code) is existing in Marvell internal branches (kernel v4.4 is the latest one), but I doubt such solution (despite it's really small) is upstreamable. I believe it can be shipped to the customers along with the SDK as a kernel module. Having the CPU's support in the mainline is IMO sufficient. Best regards, Marcin ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCHv2 0/5] Support for Marvell switches with integrated CPUs 2017-01-05 13:09 ` Andrew Lunn 2017-01-05 14:07 ` Marcin Wojtas @ 2017-01-05 19:46 ` Chris Packham 2017-01-05 19:52 ` Florian Fainelli 1 sibling, 1 reply; 16+ messages in thread From: Chris Packham @ 2017-01-05 19:46 UTC (permalink / raw) To: Andrew Lunn Cc: Florian Fainelli, linux-arm-kernel@lists.infradead.org, Rob Herring, Mark Rutland, Michael Turquette, Stephen Boyd, Linus Walleij, Jason Cooper, Gregory Clement, Sebastian Hesselbarth, Russell King, Geert Uytterhoeven, Arnd Bergmann, Thierry Reding, Sudeep Holla, Juri Lelli, Thomas Petazzoni, Laxman On 06/01/17 02:10, Andrew Lunn wrote: >> I'd love to see a switchdev driver but it's a huge task (and no I'm not >> committing to writing it). As it stands Marvell ship a switch SDK >> largely executes in userspace with a small kernel module providing some >> linkage to the underlying hardware. > > Is there any similarity to the mv88e6xxx family? > > If it was similar registers, just a different access mechanising, we > could probably extend the mv88e6xxx to support MMIO as well as MDIO. No the prestera family of devices are considerably more powerful (and complex) than the linkstreet devices. ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCHv2 0/5] Support for Marvell switches with integrated CPUs 2017-01-05 19:46 ` Chris Packham @ 2017-01-05 19:52 ` Florian Fainelli 0 siblings, 0 replies; 16+ messages in thread From: Florian Fainelli @ 2017-01-05 19:52 UTC (permalink / raw) To: Chris Packham, Andrew Lunn Cc: Mark Rutland, Geert Uytterhoeven, Michael Turquette, Laxman Dewangan, linux-clk@vger.kernel.org, Juri Lelli, Russell King, Thierry Reding, Linus Walleij, Sebastian Hesselbarth, devicetree@vger.kernel.org, Jason Cooper, Arnd Bergmann, Kalyan Kinthada, Rob Herring, Gregory Clement, linux-arm-kernel@lists.infradead.org, Thomas Petazzoni, linux-gpio@vger.kernel.org On 01/05/2017 11:46 AM, Chris Packham wrote: > On 06/01/17 02:10, Andrew Lunn wrote: >>> I'd love to see a switchdev driver but it's a huge task (and no I'm not >>> committing to writing it). As it stands Marvell ship a switch SDK >>> largely executes in userspace with a small kernel module providing some >>> linkage to the underlying hardware. >> >> Is there any similarity to the mv88e6xxx family? >> >> If it was similar registers, just a different access mechanising, we >> could probably extend the mv88e6xxx to support MMIO as well as MDIO. > > No the prestera family of devices are considerably more powerful (and > complex) than the linkstreet devices. I see, we have a similar situation with some of the Broadcom SoCs, the BCM534xx/BCM5334x have a completely different integrated switching engine that is not roboswitch compatible. Thanks for the information, this is still valuable to have this supported upstream. -- Florian ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCHv2 0/5] Support for Marvell switches with integrated CPUs 2017-01-05 3:36 [PATCHv2 0/5] Support for Marvell switches with integrated CPUs Chris Packham 2017-01-05 3:36 ` [PATCHv2 3/5] pinctrl: mvebu: pinctrl driver for 98DX3236 SoC Chris Packham 2017-01-05 4:07 ` [PATCHv2 0/5] Support for Marvell switches with integrated CPUs Florian Fainelli @ 2017-01-05 14:09 ` Marcin Wojtas 2017-01-05 20:02 ` Chris Packham 2017-01-06 4:14 ` Chris Packham 3 siblings, 1 reply; 16+ messages in thread From: Marcin Wojtas @ 2017-01-05 14:09 UTC (permalink / raw) To: Chris Packham Cc: linux-arm-kernel@lists.infradead.org, Mark Rutland, Andrew Lunn, Geert Uytterhoeven, Michael Turquette, Laxman Dewangan, linux-clk, Florian Fainelli, Juri Lelli, Russell King, Thierry Reding, Linus Walleij, Sebastian Hesselbarth, devicetree@vger.kernel.org, Jason Cooper, Arnd Bergmann, Kalyan Kinthada, Rob Herring Hi Chris, Thanks a lot for your work and v2. Can you please add changelog between patchset versions in your cover letter? Best regards, Marcin 2017-01-05 4:36 GMT+01:00 Chris Packham <chris.packham@alliedtelesis.co.nz>: > The 98DX3236, 98DX3336 and 98DX4251 are a set of switch ASICs with > integrated CPUs. They CPU block is common within these product lines and > (as far as I can tell/have been told) is based on the Armada XP. There > are a few differences due to the fact they have to squeeze the CPU into > the same package as the switch. > > Chris Packham (4): > clk: mvebu: support for 98DX3236 SoC > arm: mvebu: support for SMP on 98DX3336 SoC > arm: mvebu: Add device tree for 98DX3236 SoCs > arm: mvebu: Add device tree for db-dxbc2 and db-xc3-24g4xg boards > > Kalyan Kinthada (1): > pinctrl: mvebu: pinctrl driver for 98DX3236 SoC > > Documentation/devicetree/bindings/arm/cpus.txt | 1 + > .../bindings/arm/marvell/98dx3236-resume-ctrl.txt | 18 ++ > .../devicetree/bindings/arm/marvell/98dx3236.txt | 23 ++ > .../devicetree/bindings/clock/mvebu-cpu-clock.txt | 1 + > .../pinctrl/marvell,armada-98dx3236-pinctrl.txt | 46 ++++ > arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 247 +++++++++++++++++++++ > arch/arm/boot/dts/armada-xp-98dx3336.dtsi | 78 +++++++ > arch/arm/boot/dts/armada-xp-98dx4251.dtsi | 92 ++++++++ > arch/arm/boot/dts/db-dxbc2.dts | 159 +++++++++++++ > arch/arm/boot/dts/db-xc3-24g4xg.dts | 155 +++++++++++++ > arch/arm/mach-mvebu/Makefile | 1 + > arch/arm/mach-mvebu/common.h | 1 + > arch/arm/mach-mvebu/platsmp.c | 43 ++++ > arch/arm/mach-mvebu/pmsu-98dx3236.c | 69 ++++++ > drivers/clk/mvebu/Makefile | 2 +- > drivers/clk/mvebu/armada-xp.c | 42 ++++ > drivers/clk/mvebu/clk-cpu.c | 33 ++- > drivers/clk/mvebu/mv98dx3236-corediv.c | 207 +++++++++++++++++ > drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 155 +++++++++++++ > 19 files changed, 1369 insertions(+), 4 deletions(-) > create mode 100644 Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt > create mode 100644 Documentation/devicetree/bindings/arm/marvell/98dx3236.txt > create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt > create mode 100644 arch/arm/boot/dts/armada-xp-98dx3236.dtsi > create mode 100644 arch/arm/boot/dts/armada-xp-98dx3336.dtsi > create mode 100644 arch/arm/boot/dts/armada-xp-98dx4251.dtsi > create mode 100644 arch/arm/boot/dts/db-dxbc2.dts > create mode 100644 arch/arm/boot/dts/db-xc3-24g4xg.dts > create mode 100644 arch/arm/mach-mvebu/pmsu-98dx3236.c > create mode 100644 drivers/clk/mvebu/mv98dx3236-corediv.c > > -- > 2.11.0.24.ge6920cf > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCHv2 0/5] Support for Marvell switches with integrated CPUs 2017-01-05 14:09 ` Marcin Wojtas @ 2017-01-05 20:02 ` Chris Packham 0 siblings, 0 replies; 16+ messages in thread From: Chris Packham @ 2017-01-05 20:02 UTC (permalink / raw) To: Marcin Wojtas Cc: linux-arm-kernel@lists.infradead.org, Mark Rutland, Andrew Lunn, Geert Uytterhoeven, Michael Turquette, Laxman Dewangan, linux-clk@vger.kernel.org, Florian Fainelli, Juri Lelli, Russell King, Thierry Reding, Linus Walleij, Sebastian Hesselbarth, devicetree@vger.kernel.org, Jason Cooper, Arnd Bergmann, Kalyan Kinthada On 06/01/17 03:09, Marcin Wojtas wrote: > Hi Chris, > > Thanks a lot for your work and v2. Can you please add changelog > between patchset versions in your cover letter? Will do for v3. I did actually include a changelog in the individual patches but I can collate that here. clk: mvebu: support for 98DX3236 SoC - Update devicetree binding documentation for new compatible string arm: mvebu: support for SMP on 98DX3336 SoC - Document new enable-method value - Correct some references from 98DX4521 to 98DX3236 pinctrl: mvebu: pinctrl driver for 98DX3236 SoC - include sdio support for the 98DX4251 arm: mvebu: Add device tree for 98DX3236 SoCs - Update devicetree binding documentation to reflect that 98DX3336 and 984251 are supersets of 98DX3236. - disable crypto block - disable sdio for 98DX3236, enable for 98DX4251 arm: mvebu: Add device tree for db-dxbc2 and db-xc3-24g4xg boards - None Here's the interdiff diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index a1bcfeed5f24..3c2fd72d0bf9 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -202,6 +202,7 @@ nodes to be present and contain the properties described below. "marvell,armada-380-smp" "marvell,armada-390-smp" "marvell,armada-xp-smp" + "marvell,98dx3236-smp" "mediatek,mt6589-smp" "mediatek,mt81xx-tz-smp" "qcom,gcc-msm8660" diff --git a/Documentation/devicetree/bindings/arm/marvell/98dx3236.txt b/Documentation/devicetree/bindings/arm/marvell/98dx3236.txt index e7dc9b2dd90b..64e8c73fc5ab 100644 --- a/Documentation/devicetree/bindings/arm/marvell/98dx3236.txt +++ b/Documentation/devicetree/bindings/arm/marvell/98dx3236.txt @@ -6,5 +6,18 @@ shall have the following property: Required root node property: -compatible: one of "marvell,armadaxp-98dx3236", "marvell,armadaxp-98dx3336" - or "marvell,armadaxp-98dx4251" +compatible: must contain "marvell,armadaxp-98dx3236" + +In addition, boards using the Marvell 98DX3336 SoC shall have the +following property: + +Required root node property: + +compatible: must contain "marvell,armadaxp-98dx3336" + +In addition, boards using the Marvell 98DX4251 SoC shall have the +following property: + +Required root node property: + +compatible: must contain "marvell,armadaxp-98dx4251" diff --git a/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt index 99c214660bdc..7f28506eaee7 100644 --- a/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt +++ b/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt @@ -3,6 +3,7 @@ Device Tree Clock bindings for cpu clock of Marvell EBU platforms Required properties: - compatible : shall be one of the following: "marvell,armada-xp-cpu-clock" - cpu clocks for Armada XP + "marvell,mv98dx3236-cpu-clock" - cpu clocks for 98DX3236 SoC - reg : Address and length of the clock complex register set, followed by address and length of the PMU DFS registers - #clock-cells : should be set to 1. diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt index 34c1e380adaa..d4e6ecdfc853 100644 --- a/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt @@ -4,7 +4,7 @@ Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding part and usage Required properties: -- compatible: "marvell,98dx3236-pinctrl" +- compatible: "marvell,98dx3236-pinctrl" or "marvell,98dx4251-pinctrl" - reg: register specifier of MPP registers This driver supports all 98dx3236, 98dx3336 and 98dx4251 variants @@ -16,12 +16,12 @@ mpp1 1 gpio, spi0(miso), dev(ad9) mpp2 2 gpio, spi0(sck), dev(ad10) mpp3 3 gpio, spi0(cs0), dev(ad11) mpp4 4 gpio, spi0(cs1), smi(mdc), dev(cs0) -mpp5 5 gpio, pex(rsto), dev(bootcs) -mpp6 6 gpio, dev(a2) -mpp7 7 gpio, dev(ale0) -mpp8 8 gpio, dev(ale1) -mpp9 9 gpio, dev(ready0) -mpp10 10 gpio, dev(ad12) +mpp5 5 gpio, pex(rsto), sd0(cmd), dev(bootcs) +mpp6 6 gpio, sd0(clk), dev(a2) +mpp7 7 gpio, sd0(d0), dev(ale0) +mpp8 8 gpio, sd0(d1), dev(ale1) +mpp9 9 gpio, sd0(d2), dev(ready0) +mpp10 10 gpio, sd0(d3), dev(ad12) mpp11 11 gpio, uart1(rxd), uart0(cts), dev(ad13) mpp12 12 gpio, uart1(txd), uart0(rts), dev(ad14) mpp13 13 gpio, intr(out), dev(ad15) diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi index bac53f8b44af..61bd3acc5cfe 100644 --- a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi +++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi @@ -138,6 +138,10 @@ status = "disabled"; }; + crypto@90000 { + status = "disabled"; + }; + xor@f0900 { status = "disabled"; }; @@ -229,3 +233,15 @@ marvell,function = "spi0"; }; }; + +&sdio { + status = "disabled"; +}; + +&crypto_sram0 { + status = "disabled"; +}; + +&crypto_sram1 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/armada-xp-98dx4251.dtsi b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi index 5d1da8513fae..5f7edc23d5ae 100644 --- a/arch/arm/boot/dts/armada-xp-98dx4251.dtsi +++ b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi @@ -76,3 +76,17 @@ }; }; }; + +&sdio { + status = "okay"; +}; + +&pinctrl { + compatible = "marvell,98dx4251-pinctrl"; + + sdio_pins: sdio-pins { + marvell,pins = "mpp5", "mpp6", "mpp7", + "mpp8", "mpp9", "mpp10"; + marvell,function = "sd0"; + }; +}; diff --git a/arch/arm/mach-mvebu/pmsu-98dx3236.c b/arch/arm/mach-mvebu/pmsu-98dx3236.c index fadc81d0c051..87ca42ef40c7 100644 --- a/arch/arm/mach-mvebu/pmsu-98dx3236.c +++ b/arch/arm/mach-mvebu/pmsu-98dx3236.c @@ -1,5 +1,5 @@ /** - * CPU resume support for 98DX4521 internal CPU (a.k.a. MSYS). + * CPU resume support for 98DX3236 internal CPU (a.k.a. MSYS). */ #define pr_fmt(fmt) "mv98dx3236-resume: " fmt @@ -38,7 +38,7 @@ static int __init mv98dx3236_resume_init(void) if (!np) return 0; - pr_info("Initializing 98DX4521 Resume\n"); + pr_info("Initializing 98DX3236 Resume\n"); if (of_address_to_resource(np, 0, &res)) { pr_err("unable to get resource\n"); diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c index 2586903c59f0..554eeae8cd21 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c @@ -389,21 +389,27 @@ static struct mvebu_mpp_mode mv98dx3236_mpp_modes[] = { MPP_MODE(5, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), MPP_VAR_FUNCTION(0x1, "pex", "rsto", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "sd0", "cmd", V_98DX4251), MPP_VAR_FUNCTION(0x4, "dev", "bootcs0", V_98DX3236_PLUS)), MPP_MODE(6, MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "sd0", "clk", V_98DX4251), MPP_VAR_FUNCTION(0x4, "dev", "a2", V_98DX3236_PLUS)), MPP_MODE(7, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "sd0", "d0", V_98DX4251), MPP_VAR_FUNCTION(0x4, "dev", "ale0", V_98DX3236_PLUS)), MPP_MODE(8, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "sd0", "d1", V_98DX4251), MPP_VAR_FUNCTION(0x4, "dev", "ale1", V_98DX3236_PLUS)), MPP_MODE(9, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "sd0", "d2", V_98DX4251), MPP_VAR_FUNCTION(0x4, "dev", "ready0", V_98DX3236_PLUS)), MPP_MODE(10, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "sd0", "d3", V_98DX4251), MPP_VAR_FUNCTION(0x4, "dev", "ad12", V_98DX3236_PLUS)), MPP_MODE(11, MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), @@ -501,6 +507,10 @@ static const struct of_device_id armada_xp_pinctrl_of_match[] = { .compatible = "marvell,98dx3236-pinctrl", .data = (void *) V_98DX3236, }, + { + .compatible = "marvell,98dx4251-pinctrl", + .data = (void *) V_98DX4251, + }, { }, }; > > Best regards, > Marcin > > 2017-01-05 4:36 GMT+01:00 Chris Packham <chris.packham@alliedtelesis.co.nz>: >> The 98DX3236, 98DX3336 and 98DX4251 are a set of switch ASICs with >> integrated CPUs. They CPU block is common within these product lines and >> (as far as I can tell/have been told) is based on the Armada XP. There >> are a few differences due to the fact they have to squeeze the CPU into >> the same package as the switch. >> >> Chris Packham (4): >> clk: mvebu: support for 98DX3236 SoC >> arm: mvebu: support for SMP on 98DX3336 SoC >> arm: mvebu: Add device tree for 98DX3236 SoCs >> arm: mvebu: Add device tree for db-dxbc2 and db-xc3-24g4xg boards >> >> Kalyan Kinthada (1): >> pinctrl: mvebu: pinctrl driver for 98DX3236 SoC >> >> Documentation/devicetree/bindings/arm/cpus.txt | 1 + >> .../bindings/arm/marvell/98dx3236-resume-ctrl.txt | 18 ++ >> .../devicetree/bindings/arm/marvell/98dx3236.txt | 23 ++ >> .../devicetree/bindings/clock/mvebu-cpu-clock.txt | 1 + >> .../pinctrl/marvell,armada-98dx3236-pinctrl.txt | 46 ++++ >> arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 247 +++++++++++++++++++++ >> arch/arm/boot/dts/armada-xp-98dx3336.dtsi | 78 +++++++ >> arch/arm/boot/dts/armada-xp-98dx4251.dtsi | 92 ++++++++ >> arch/arm/boot/dts/db-dxbc2.dts | 159 +++++++++++++ >> arch/arm/boot/dts/db-xc3-24g4xg.dts | 155 +++++++++++++ >> arch/arm/mach-mvebu/Makefile | 1 + >> arch/arm/mach-mvebu/common.h | 1 + >> arch/arm/mach-mvebu/platsmp.c | 43 ++++ >> arch/arm/mach-mvebu/pmsu-98dx3236.c | 69 ++++++ >> drivers/clk/mvebu/Makefile | 2 +- >> drivers/clk/mvebu/armada-xp.c | 42 ++++ >> drivers/clk/mvebu/clk-cpu.c | 33 ++- >> drivers/clk/mvebu/mv98dx3236-corediv.c | 207 +++++++++++++++++ >> drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 155 +++++++++++++ >> 19 files changed, 1369 insertions(+), 4 deletions(-) >> create mode 100644 Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt >> create mode 100644 Documentation/devicetree/bindings/arm/marvell/98dx3236.txt >> create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt >> create mode 100644 arch/arm/boot/dts/armada-xp-98dx3236.dtsi >> create mode 100644 arch/arm/boot/dts/armada-xp-98dx3336.dtsi >> create mode 100644 arch/arm/boot/dts/armada-xp-98dx4251.dtsi >> create mode 100644 arch/arm/boot/dts/db-dxbc2.dts >> create mode 100644 arch/arm/boot/dts/db-xc3-24g4xg.dts >> create mode 100644 arch/arm/mach-mvebu/pmsu-98dx3236.c >> create mode 100644 drivers/clk/mvebu/mv98dx3236-corediv.c >> >> -- >> 2.11.0.24.ge6920cf >> >> >> _______________________________________________ >> linux-arm-kernel mailing list >> linux-arm-kernel@lists.infradead.org >> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel > ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCHv2 0/5] Support for Marvell switches with integrated CPUs 2017-01-05 3:36 [PATCHv2 0/5] Support for Marvell switches with integrated CPUs Chris Packham ` (2 preceding siblings ...) 2017-01-05 14:09 ` Marcin Wojtas @ 2017-01-06 4:14 ` Chris Packham 2017-01-06 4:15 ` [PATCHv3 3/5] pinctrl: mvebu: pinctrl driver for 98DX3236 SoC Chris Packham 3 siblings, 1 reply; 16+ messages in thread From: Chris Packham @ 2017-01-06 4:14 UTC (permalink / raw) To: linux-arm-kernel Cc: Mark Rutland, Andrew Lunn, Geert Uytterhoeven, Michael Turquette, Laxman Dewangan, linux-clk, Florian Fainelli, Juri Lelli, Russell King, Thierry Reding, Linus Walleij, Sebastian Hesselbarth, devicetree, Jason Cooper, Arnd Bergmann, Kalyan Kinthada, Rob Herring, Chris Brand, Gregory Clement, Thomas Petazzoni, linux-gpio, netdev, Stephen Boyd The 98DX3236, 98DX3336 and 98DX4251 are a set of switch ASICs with integrated CPUs. They CPU block is common within these product lines and (as far as I can tell/have been told) is based on the Armada XP. There are a few differences due to the fact they have to squeeze the CPU into the same package as the switch. Chris Packham (4): clk: mvebu: support for 98DX3236 SoC Changes in v2: - Update devicetree binding documentation for new compatible string Changes in v3: - Add 98dx3236 support to mvebu/clk-corediv.c rather than creating a new driver. - Document mv98dx3236-corediv-clock binding arm: mvebu: support for SMP on 98DX3336 SoC Changes in v2: - Document new enable-method value - Correct some references from 98DX4521 to 98DX3236 Changes in v3: - Simplify mv98dx3236_resume_init by using of_io_request_and_map() arm: mvebu: Add device tree for 98DX3236 SoCs Changes in v2: - Update devicetree binding documentation to reflect that 98DX3336 and 984251 are supersets of 98DX3236. - disable crypto block - disable sdio for 98DX3236, enable for 98DX4251 Changes in v3: - fix typo 4521 -> 4251 - document prestera bindings - rework corediv-clock binding - add label to packet processor node - add new compativle string for DFX server arm: mvebu: Add device tree for db-dxbc2 and db-xc3-24g4xg boards Changes in v2/v3: - none Kalyan Kinthada (1): pinctrl: mvebu: pinctrl driver for 98DX3236 SoC Changes in v2: - include sdio support for the 98DX4251 Changes in v3: - None Documentation/devicetree/bindings/arm/cpus.txt | 1 + .../bindings/arm/marvell/98dx3236-resume-ctrl.txt | 18 ++ .../devicetree/bindings/arm/marvell/98dx3236.txt | 23 ++ .../bindings/clock/mvebu-corediv-clock.txt | 1 + .../devicetree/bindings/clock/mvebu-cpu-clock.txt | 1 + .../devicetree/bindings/net/marvell,prestera.txt | 50 ++++ .../pinctrl/marvell,armada-98dx3236-pinctrl.txt | 46 ++++ arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 254 +++++++++++++++++++++ arch/arm/boot/dts/armada-xp-98dx3336.dtsi | 76 ++++++ arch/arm/boot/dts/armada-xp-98dx4251.dtsi | 90 ++++++++ arch/arm/boot/dts/db-dxbc2.dts | 159 +++++++++++++ arch/arm/boot/dts/db-xc3-24g4xg.dts | 155 +++++++++++++ arch/arm/mach-mvebu/Makefile | 1 + arch/arm/mach-mvebu/common.h | 1 + arch/arm/mach-mvebu/platsmp.c | 43 ++++ arch/arm/mach-mvebu/pmsu-98dx3236.c | 52 +++++ drivers/clk/mvebu/armada-xp.c | 42 ++++ drivers/clk/mvebu/clk-corediv.c | 23 ++ drivers/clk/mvebu/clk-cpu.c | 31 ++- drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 155 +++++++++++++ 20 files changed, 1220 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt create mode 100644 Documentation/devicetree/bindings/arm/marvell/98dx3236.txt create mode 100644 Documentation/devicetree/bindings/net/marvell,prestera.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt create mode 100644 arch/arm/boot/dts/armada-xp-98dx3236.dtsi create mode 100644 arch/arm/boot/dts/armada-xp-98dx3336.dtsi create mode 100644 arch/arm/boot/dts/armada-xp-98dx4251.dtsi create mode 100644 arch/arm/boot/dts/db-dxbc2.dts create mode 100644 arch/arm/boot/dts/db-xc3-24g4xg.dts create mode 100644 arch/arm/mach-mvebu/pmsu-98dx3236.c Interdiff to v2: diff --git a/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt index 520562a7dc2a..c7b4e3a6b2c6 100644 --- a/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt +++ b/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt @@ -7,6 +7,7 @@ Required properties: - compatible : must be "marvell,armada-370-corediv-clock", "marvell,armada-375-corediv-clock", "marvell,armada-380-corediv-clock", + "marvell,mv98dx3236-corediv-clock", - reg : must be the register address of Core Divider control register - #clock-cells : from common clock binding; shall be set to 1 diff --git a/Documentation/devicetree/bindings/net/marvell,prestera.txt b/Documentation/devicetree/bindings/net/marvell,prestera.txt new file mode 100644 index 000000000000..5fbab29718e8 --- /dev/null +++ b/Documentation/devicetree/bindings/net/marvell,prestera.txt @@ -0,0 +1,50 @@ +Marvell Prestera Switch Chip bindings +------------------------------------- + +Required properties: +- compatible: one of the following + "marvell,prestera-98dx3236", + "marvell,prestera-98dx3336", + "marvell,prestera-98dx4251", +- reg: address and length of the register set for the device. +- interrupts: interrupt for the device + +Optional properties: +- dfx: phandle reference to the "DFX Server" node + +Example: + +switch { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>; + + packet-processor@0 { + compatible = "marvell,prestera-98dx3236"; + reg = <0 0x4000000>; + interrupts = <33>, <34>, <35>; + dfx = <&dfx>; + }; +}; + +DFX Server bindings +------------------- + +Required properties: +- compatible: must be "marvell,dfx-server" +- reg: address and length of the register set for the device. + +Example: + +dfx-registers { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>; + + dfx: dfx@0 { + compatible = "marvell,dfx-server"; + reg = <0 0x100000>; + }; +}; diff --git a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi index 61bd3acc5cfe..4b7b2fe3b682 100644 --- a/arch/arm/boot/dts/armada-xp-98dx3236.dtsi +++ b/arch/arm/boot/dts/armada-xp-98dx3236.dtsi @@ -126,12 +126,7 @@ }; corediv-clock@18740 { - compatible = "marvell,mv98dx3236-corediv-clock"; - reg = <0xf8268 0xc>; - base = <&dfx>; - #clock-cells = <1>; - clocks = <&mainpll>; - clock-output-names = "nand"; + status = "disabled"; }; xor@60900 { @@ -194,6 +189,10 @@ #interrupt-cells = <2>; interrupts = <87>; }; + + nand: nand@d0000 { + clocks = <&dfx_coredivclk 0>; + }; }; dfx-registers { @@ -202,8 +201,16 @@ #size-cells = <1>; ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>; + dfx_coredivclk: corediv-clock@f8268 { + compatible = "marvell,mv98dx3236-corediv-clock"; + reg = <0xf8268 0xc>; + #clock-cells = <1>; + clocks = <&mainpll>; + clock-output-names = "nand"; + }; + dfx: dfx@0 { - compatible = "simple-bus"; + compatible = "marvell,dfx-server"; reg = <0 0x100000>; }; }; @@ -214,7 +221,7 @@ #size-cells = <1>; ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>; - packet-processor@0 { + pp0: packet-processor@0 { compatible = "marvell,prestera-98dx3236"; reg = <0 0x4000000>; interrupts = <33>, <34>, <35>; diff --git a/arch/arm/boot/dts/armada-xp-98dx3336.dtsi b/arch/arm/boot/dts/armada-xp-98dx3336.dtsi index 9c9aa565fd82..a9b0f47f8df9 100644 --- a/arch/arm/boot/dts/armada-xp-98dx3336.dtsi +++ b/arch/arm/boot/dts/armada-xp-98dx3336.dtsi @@ -68,11 +68,9 @@ reg = <0x20980 0x10>; }; }; - - switch { - packet-processor@0 { - compatible = "marvell,prestera-98dx3336"; - }; - }; }; }; + +&pp0 { + compatible = "marvell,prestera-98dx3336"; +}; diff --git a/arch/arm/boot/dts/armada-xp-98dx4251.dtsi b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi index 5f7edc23d5ae..446e6e65ec59 100644 --- a/arch/arm/boot/dts/armada-xp-98dx4251.dtsi +++ b/arch/arm/boot/dts/armada-xp-98dx4251.dtsi @@ -68,12 +68,6 @@ reg = <0x20980 0x10>; }; }; - - switch { - packet-processor@0 { - compatible = "marvell,prestera-98dx4521"; - }; - }; }; }; @@ -90,3 +84,7 @@ marvell,function = "sd0"; }; }; + +&pp0 { + compatible = "marvell,prestera-98dx4251"; +}; diff --git a/arch/arm/mach-mvebu/pmsu-98dx3236.c b/arch/arm/mach-mvebu/pmsu-98dx3236.c index 87ca42ef40c7..1052674dd439 100644 --- a/arch/arm/mach-mvebu/pmsu-98dx3236.c +++ b/arch/arm/mach-mvebu/pmsu-98dx3236.c @@ -31,39 +31,22 @@ void mv98dx3236_resume_set_cpu_boot_addr(int hw_cpu, void *boot_addr) static int __init mv98dx3236_resume_init(void) { struct device_node *np; - struct resource res; - int ret = 0; + void __iomem *base; np = of_find_matching_node(NULL, of_mv98dx3236_resume_table); if (!np) return 0; - pr_info("Initializing 98DX3236 Resume\n"); - - if (of_address_to_resource(np, 0, &res)) { - pr_err("unable to get resource\n"); - ret = -ENOENT; - goto out; - } - - if (!request_mem_region(res.start, resource_size(&res), - np->full_name)) { - pr_err("unable to request region\n"); - ret = -EBUSY; - goto out; - } - - mv98dx3236_resume_base = ioremap(res.start, resource_size(&res)); - if (!mv98dx3236_resume_base) { + base = of_io_request_and_map(np, 0, of_node_full_name(np)); + if (IS_ERR(base)) { pr_err("unable to map registers\n"); - release_mem_region(res.start, resource_size(&res)); - ret = -ENOMEM; - goto out; + of_node_put(np); + return PTR_ERR(mv98dx3236_resume_base); } -out: + mv98dx3236_resume_base = base; of_node_put(np); - return ret; + return 0; } early_initcall(mv98dx3236_resume_init); diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile index 6a3681e3d6db..d9ae97fb43c4 100644 --- a/drivers/clk/mvebu/Makefile +++ b/drivers/clk/mvebu/Makefile @@ -9,7 +9,7 @@ obj-$(CONFIG_ARMADA_39X_CLK) += armada-39x.o obj-$(CONFIG_ARMADA_37XX_CLK) += armada-37xx-xtal.o obj-$(CONFIG_ARMADA_37XX_CLK) += armada-37xx-tbg.o obj-$(CONFIG_ARMADA_37XX_CLK) += armada-37xx-periph.o -obj-$(CONFIG_ARMADA_XP_CLK) += armada-xp.o mv98dx3236-corediv.o +obj-$(CONFIG_ARMADA_XP_CLK) += armada-xp.o obj-$(CONFIG_ARMADA_AP806_SYSCON) += ap806-system-controller.o obj-$(CONFIG_ARMADA_CP110_SYSCON) += cp110-system-controller.o obj-$(CONFIG_DOVE_CLK) += dove.o dove-divider.o diff --git a/drivers/clk/mvebu/clk-corediv.c b/drivers/clk/mvebu/clk-corediv.c index d1e5863d3375..8491979f4096 100644 --- a/drivers/clk/mvebu/clk-corediv.c +++ b/drivers/clk/mvebu/clk-corediv.c @@ -71,6 +71,10 @@ static const struct clk_corediv_desc mvebu_corediv_desc[] = { { .mask = 0x3f, .offset = 8, .fieldbit = 1 }, /* NAND clock */ }; +static const struct clk_corediv_desc mv98dx3236_corediv_desc[] = { + { .mask = 0x0f, .offset = 6, .fieldbit = 26 }, /* NAND clock */ +}; + #define to_corediv_clk(p) container_of(p, struct clk_corediv, hw) static int clk_corediv_is_enabled(struct clk_hw *hwclk) @@ -232,6 +236,18 @@ static const struct clk_corediv_soc_desc armada375_corediv_soc = { .ratio_offset = 0x4, }; +static const struct clk_corediv_soc_desc mv98dx3236_corediv_soc = { + .descs = mv98dx3236_corediv_desc, + .ndescs = ARRAY_SIZE(mv98dx3236_corediv_desc), + .ops = { + .recalc_rate = clk_corediv_recalc_rate, + .round_rate = clk_corediv_round_rate, + .set_rate = clk_corediv_set_rate, + }, + .ratio_reload = BIT(10), + .ratio_offset = 0x8, +}; + static void __init mvebu_corediv_clk_init(struct device_node *node, const struct clk_corediv_soc_desc *soc_desc) @@ -313,3 +329,10 @@ static void __init armada380_corediv_clk_init(struct device_node *node) } CLK_OF_DECLARE(armada380_corediv_clk, "marvell,armada-380-corediv-clock", armada380_corediv_clk_init); + +static void __init mv98dx3236_corediv_clk_init(struct device_node *node) +{ + return mvebu_corediv_clk_init(node, &mv98dx3236_corediv_soc); +} +CLK_OF_DECLARE(mv98dx3236_corediv_clk, "marvell,mv98dx3236-corediv-clock", + mv98dx3236_corediv_clk_init); diff --git a/drivers/clk/mvebu/clk-cpu.c b/drivers/clk/mvebu/clk-cpu.c index 29f295e7a36b..3b8f0e14fa01 100644 --- a/drivers/clk/mvebu/clk-cpu.c +++ b/drivers/clk/mvebu/clk-cpu.c @@ -254,7 +254,7 @@ static void __init of_cpu_clk_setup(struct device_node *node) } CLK_OF_DECLARE(armada_xp_cpu_clock, "marvell,armada-xp-cpu-clock", - of_cpu_clk_setup); + of_cpu_clk_setup); /* Define the clock and operations for the mv98dx3236 - it cannot * perform * any operations. diff --git a/drivers/clk/mvebu/mv98dx3236-corediv.c b/drivers/clk/mvebu/mv98dx3236-corediv.c deleted file mode 100644 index 3060764a8e5d..000000000000 --- a/drivers/clk/mvebu/mv98dx3236-corediv.c +++ /dev/null @@ -1,207 +0,0 @@ -/* - * MV98DX3236 Core divider clock - * - * Copyright (C) 2015 Allied Telesis Labs - * - * Based on armada-xp-corediv.c - * Copyright (C) 2015 Marvell - * - * John Thompson <john.thompson@alliedtelesis.co.nz> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ -#include <linux/kernel.h> -#include <linux/clk-provider.h> -#include <linux/of_address.h> -#include <linux/slab.h> -#include <linux/delay.h> -#include "common.h" - -#define CORE_CLK_DIV_RATIO_MASK 0xff - -#define CLK_DIV_RATIO_NAND_MASK 0x0f -#define CLK_DIV_RATIO_NAND_OFFSET 6 -#define CLK_DIV_RATIO_NAND_FORCE_RELOAD_BIT 26 - -#define RATIO_RELOAD_BIT BIT(10) -#define RATIO_REG_OFFSET 0x08 - -/* - * This structure represents one core divider clock for the clock - * framework, and is dynamically allocated for each core divider clock - * existing in the current SoC. - */ -struct clk_corediv { - struct clk_hw hw; - void __iomem *reg; - spinlock_t lock; -}; - -static struct clk_onecell_data clk_data; - - -#define to_corediv_clk(p) container_of(p, struct clk_corediv, hw) - -static int mv98dx3236_corediv_is_enabled(struct clk_hw *hwclk) -{ - /* Core divider is always active */ - return 1; -} - -static int mv98dx3236_corediv_enable(struct clk_hw *hwclk) -{ - /* always succeeds */ - return 0; -} - -static void mv98dx3236_corediv_disable(struct clk_hw *hwclk) -{ - /* can't be disabled so is left alone */ -} - -static unsigned long mv98dx3236_corediv_recalc_rate(struct clk_hw *hwclk, - unsigned long parent_rate) -{ - struct clk_corediv *corediv = to_corediv_clk(hwclk); - u32 reg, div; - - reg = readl(corediv->reg + RATIO_REG_OFFSET); - div = (reg >> CLK_DIV_RATIO_NAND_OFFSET) & CLK_DIV_RATIO_NAND_MASK; - return parent_rate / div; -} - -static long mv98dx3236_corediv_round_rate(struct clk_hw *hwclk, - unsigned long rate, unsigned long *parent_rate) -{ - /* Valid ratio are 1:4, 1:5, 1:6 and 1:8 */ - u32 div; - - div = *parent_rate / rate; - if (div < 4) - div = 4; - else if (div > 6) - div = 8; - - return *parent_rate / div; -} - -static int mv98dx3236_corediv_set_rate(struct clk_hw *hwclk, unsigned long rate, - unsigned long parent_rate) -{ - struct clk_corediv *corediv = to_corediv_clk(hwclk); - unsigned long flags = 0; - u32 reg, div; - - div = parent_rate / rate; - - spin_lock_irqsave(&corediv->lock, flags); - - /* Write new divider to the divider ratio register */ - reg = readl(corediv->reg + RATIO_REG_OFFSET); - reg &= ~(CLK_DIV_RATIO_NAND_MASK << CLK_DIV_RATIO_NAND_OFFSET); - reg |= (div & CLK_DIV_RATIO_NAND_MASK) << CLK_DIV_RATIO_NAND_OFFSET; - writel(reg, corediv->reg + RATIO_REG_OFFSET); - - /* Set reload-force for this clock */ - reg = readl(corediv->reg) | BIT(CLK_DIV_RATIO_NAND_FORCE_RELOAD_BIT); - writel(reg, corediv->reg); - - /* Now trigger the clock update */ - reg = readl(corediv->reg + RATIO_REG_OFFSET) | RATIO_RELOAD_BIT; - writel(reg, corediv->reg + RATIO_REG_OFFSET); - - /* - * Wait for clocks to settle down, and then clear all the - * ratios request and the reload request. - */ - udelay(1000); - reg &= ~(CORE_CLK_DIV_RATIO_MASK | RATIO_RELOAD_BIT); - writel(reg, corediv->reg + RATIO_REG_OFFSET); - udelay(1000); - - spin_unlock_irqrestore(&corediv->lock, flags); - - return 0; -} - -static const struct clk_ops ops = { - .enable = mv98dx3236_corediv_enable, - .disable = mv98dx3236_corediv_disable, - .is_enabled = mv98dx3236_corediv_is_enabled, - .recalc_rate = mv98dx3236_corediv_recalc_rate, - .round_rate = mv98dx3236_corediv_round_rate, - .set_rate = mv98dx3236_corediv_set_rate, -}; - -static void __init mv98dx3236_corediv_clk_init(struct device_node *node) -{ - struct clk_init_data init; - struct clk_corediv *corediv; - struct clk **clks; - void __iomem *base; - const __be32 *off; - const char *parent_name; - const char *clk_name; - int len; - struct device_node *dfx_node; - - dfx_node = of_parse_phandle(node, "base", 0); - if (WARN_ON(!dfx_node)) - return; - - off = of_get_property(node, "reg", &len); - if (WARN_ON(!off)) - return; - - base = of_iomap(dfx_node, 0); - if (WARN_ON(!base)) - return; - - of_node_put(dfx_node); - - parent_name = of_clk_get_parent_name(node, 0); - - clk_data.clk_num = 1; - - /* clks holds the clock array */ - clks = kcalloc(clk_data.clk_num, sizeof(struct clk *), - GFP_KERNEL); - if (WARN_ON(!clks)) - goto err_unmap; - /* corediv holds the clock specific array */ - corediv = kcalloc(clk_data.clk_num, sizeof(struct clk_corediv), - GFP_KERNEL); - if (WARN_ON(!corediv)) - goto err_free_clks; - - spin_lock_init(&corediv->lock); - - of_property_read_string_index(node, "clock-output-names", - 0, &clk_name); - - init.num_parents = 1; - init.parent_names = &parent_name; - init.name = clk_name; - init.ops = &ops; - init.flags = 0; - - corediv[0].reg = (void *)((int)base + be32_to_cpu(*off)); - corediv[0].hw.init = &init; - - clks[0] = clk_register(NULL, &corediv[0].hw); - WARN_ON(IS_ERR(clks[0])); - - clk_data.clks = clks; - of_clk_add_provider(node, of_clk_src_onecell_get, &clk_data); - return; - -err_free_clks: - kfree(clks); -err_unmap: - iounmap(base); -} - -CLK_OF_DECLARE(mv98dx3236_corediv_clk, "marvell,mv98dx3236-corediv-clock", - mv98dx3236_corediv_clk_init); -- 2.11.0.24.ge6920cf ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCHv3 3/5] pinctrl: mvebu: pinctrl driver for 98DX3236 SoC 2017-01-06 4:14 ` Chris Packham @ 2017-01-06 4:15 ` Chris Packham [not found] ` <20170106041517.9589-4-chris.packham-6g8wRflRTwXFdCa3tKVlE6U/zSkkHjvu@public.gmane.org> 2017-01-11 14:44 ` Linus Walleij 0 siblings, 2 replies; 16+ messages in thread From: Chris Packham @ 2017-01-06 4:15 UTC (permalink / raw) To: linux-arm-kernel Cc: Mark Rutland, Thomas Petazzoni, linux-gpio, Linus Walleij, linux-kernel, Rob Herring, Kalyan Kinthada, devicetree, Chris Packham, Laxman Dewangan From: Kalyan Kinthada <kalyan.kinthada@alliedtelesis.co.nz> This pinctrl driver supports the 98DX3236, 98DX3336 and 98DX4251 SoCs from Marvell. Signed-off-by: Kalyan Kinthada <kalyan.kinthada@alliedtelesis.co.nz> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> --- Changes in v2: - include sdio support for the 98DX4251 Changes in v3: - None .../pinctrl/marvell,armada-98dx3236-pinctrl.txt | 46 ++++++ drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 155 +++++++++++++++++++++ 2 files changed, 201 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt new file mode 100644 index 000000000000..d4e6ecdfc853 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt @@ -0,0 +1,46 @@ +* Marvell 98dx3236 pinctrl driver for mpp + +Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding +part and usage + +Required properties: +- compatible: "marvell,98dx3236-pinctrl" or "marvell,98dx4251-pinctrl" +- reg: register specifier of MPP registers + +This driver supports all 98dx3236, 98dx3336 and 98dx4251 variants + +name pins functions +================================================================================ +mpp0 0 gpio, spi0(mosi), dev(ad8) +mpp1 1 gpio, spi0(miso), dev(ad9) +mpp2 2 gpio, spi0(sck), dev(ad10) +mpp3 3 gpio, spi0(cs0), dev(ad11) +mpp4 4 gpio, spi0(cs1), smi(mdc), dev(cs0) +mpp5 5 gpio, pex(rsto), sd0(cmd), dev(bootcs) +mpp6 6 gpio, sd0(clk), dev(a2) +mpp7 7 gpio, sd0(d0), dev(ale0) +mpp8 8 gpio, sd0(d1), dev(ale1) +mpp9 9 gpio, sd0(d2), dev(ready0) +mpp10 10 gpio, sd0(d3), dev(ad12) +mpp11 11 gpio, uart1(rxd), uart0(cts), dev(ad13) +mpp12 12 gpio, uart1(txd), uart0(rts), dev(ad14) +mpp13 13 gpio, intr(out), dev(ad15) +mpp14 14 gpio, i2c0(sck) +mpp15 15 gpio, i2c0(sda) +mpp16 16 gpio, dev(oe) +mpp17 17 gpio, dev(clk) +mpp18 18 gpio, uart1(txd) +mpp19 19 gpio, uart1(rxd), dev(rb) +mpp20 20 gpio, dev(we) +mpp21 21 gpio, dev(ad0) +mpp22 22 gpio, dev(ad1) +mpp23 23 gpio, dev(ad2) +mpp24 24 gpio, dev(ad3) +mpp25 25 gpio, dev(ad4) +mpp26 26 gpio, dev(ad5) +mpp27 27 gpio, dev(ad6) +mpp28 28 gpio, dev(ad7) +mpp29 29 gpio, dev(a0) +mpp30 30 gpio, dev(a1) +mpp31 31 gpio, slv_smi(mdc), smi(mdc), dev(we1) +mpp32 32 gpio, slv_smi(mdio), smi(mdio), dev(cs1) diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c index e4ea71a9d985..554eeae8cd21 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c @@ -49,6 +49,10 @@ enum armada_xp_variant { V_MV78460 = BIT(2), V_MV78230_PLUS = (V_MV78230 | V_MV78260 | V_MV78460), V_MV78260_PLUS = (V_MV78260 | V_MV78460), + V_98DX3236 = BIT(3), + V_98DX3336 = BIT(4), + V_98DX4251 = BIT(5), + V_98DX3236_PLUS = (V_98DX3236 | V_98DX3336 | V_98DX4251), }; static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { @@ -360,6 +364,130 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = { MPP_VAR_FUNCTION(0x1, "dev", "ad31", V_MV78260_PLUS)), }; +static struct mvebu_mpp_mode mv98dx3236_mpp_modes[] = { + MPP_MODE(0, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "spi0", "mosi", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "ad8", V_98DX3236_PLUS)), + MPP_MODE(1, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "spi0", "miso", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "ad9", V_98DX3236_PLUS)), + MPP_MODE(2, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "spi0", "csk", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "ad10", V_98DX3236_PLUS)), + MPP_MODE(3, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "spi0", "cs0", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "ad11", V_98DX3236_PLUS)), + MPP_MODE(4, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "spi0", "cs1", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x3, "smi", "mdc", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "cs0", V_98DX3236_PLUS)), + MPP_MODE(5, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "pex", "rsto", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "sd0", "cmd", V_98DX4251), + MPP_VAR_FUNCTION(0x4, "dev", "bootcs0", V_98DX3236_PLUS)), + MPP_MODE(6, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "sd0", "clk", V_98DX4251), + MPP_VAR_FUNCTION(0x4, "dev", "a2", V_98DX3236_PLUS)), + MPP_MODE(7, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "sd0", "d0", V_98DX4251), + MPP_VAR_FUNCTION(0x4, "dev", "ale0", V_98DX3236_PLUS)), + MPP_MODE(8, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "sd0", "d1", V_98DX4251), + MPP_VAR_FUNCTION(0x4, "dev", "ale1", V_98DX3236_PLUS)), + MPP_MODE(9, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "sd0", "d2", V_98DX4251), + MPP_VAR_FUNCTION(0x4, "dev", "ready0", V_98DX3236_PLUS)), + MPP_MODE(10, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "sd0", "d3", V_98DX4251), + MPP_VAR_FUNCTION(0x4, "dev", "ad12", V_98DX3236_PLUS)), + MPP_MODE(11, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "uart1", "rxd", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x3, "uart0", "cts", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "ad13", V_98DX3236_PLUS)), + MPP_MODE(12, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x2, "uart1", "txd", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x3, "uart0", "rts", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "ad14", V_98DX3236_PLUS)), + MPP_MODE(13, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "intr", "out", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "ad15", V_98DX3236_PLUS)), + MPP_MODE(14, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "i2c0", "sck", V_98DX3236_PLUS)), + MPP_MODE(15, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "i2c0", "sda", V_98DX3236_PLUS)), + MPP_MODE(16, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "oe", V_98DX3236_PLUS)), + MPP_MODE(17, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "clkout", V_98DX3236_PLUS)), + MPP_MODE(18, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x3, "uart1", "txd", V_98DX3236_PLUS)), + MPP_MODE(19, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x3, "uart1", "rxd", V_98DX3236_PLUS)), + MPP_MODE(20, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "we0", V_98DX3236_PLUS)), + MPP_MODE(21, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "dev", "ad0", V_98DX3236_PLUS)), + MPP_MODE(22, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "dev", "ad1", V_98DX3236_PLUS)), + MPP_MODE(23, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "dev", "ad2", V_98DX3236_PLUS)), + MPP_MODE(24, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "dev", "ad3", V_98DX3236_PLUS)), + MPP_MODE(25, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "dev", "ad4", V_98DX3236_PLUS)), + MPP_MODE(26, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "dev", "ad5", V_98DX3236_PLUS)), + MPP_MODE(27, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "dev", "ad6", V_98DX3236_PLUS)), + MPP_MODE(28, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "dev", "ad7", V_98DX3236_PLUS)), + MPP_MODE(29, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "dev", "a0", V_98DX3236_PLUS)), + MPP_MODE(30, + MPP_VAR_FUNCTION(0x0, "gpo", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "dev", "a1", V_98DX3236_PLUS)), + MPP_MODE(31, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "slv_smi", "mdc", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x3, "smi", "mdc", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "we1", V_98DX3236_PLUS)), + MPP_MODE(32, + MPP_VAR_FUNCTION(0x0, "gpio", NULL, V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x1, "slv_smi", "mdio", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x3, "smi", "mdio", V_98DX3236_PLUS), + MPP_VAR_FUNCTION(0x4, "dev", "cs1", V_98DX3236_PLUS)), +}; + static struct mvebu_pinctrl_soc_info armada_xp_pinctrl_info; static const struct of_device_id armada_xp_pinctrl_of_match[] = { @@ -375,6 +503,14 @@ static const struct of_device_id armada_xp_pinctrl_of_match[] = { .compatible = "marvell,mv78460-pinctrl", .data = (void *) V_MV78460, }, + { + .compatible = "marvell,98dx3236-pinctrl", + .data = (void *) V_98DX3236, + }, + { + .compatible = "marvell,98dx4251-pinctrl", + .data = (void *) V_98DX4251, + }, { }, }; @@ -407,6 +543,14 @@ static struct pinctrl_gpio_range mv78460_mpp_gpio_ranges[] = { MPP_GPIO_RANGE(2, 64, 64, 3), }; +static struct mvebu_mpp_ctrl mv98dx3236_mpp_controls[] = { + MPP_FUNC_CTRL(0, 32, NULL, armada_xp_mpp_ctrl), +}; + +static struct pinctrl_gpio_range mv98dx3236_mpp_gpio_ranges[] = { + MPP_GPIO_RANGE(0, 0, 0, 32), +}; + static int armada_xp_pinctrl_suspend(struct platform_device *pdev, pm_message_t state) { @@ -488,6 +632,17 @@ static int armada_xp_pinctrl_probe(struct platform_device *pdev) soc->gpioranges = mv78460_mpp_gpio_ranges; soc->ngpioranges = ARRAY_SIZE(mv78460_mpp_gpio_ranges); break; + case V_98DX3236: + case V_98DX3336: + case V_98DX4251: + /* fall-through */ + soc->controls = mv98dx3236_mpp_controls; + soc->ncontrols = ARRAY_SIZE(mv98dx3236_mpp_controls); + soc->modes = mv98dx3236_mpp_modes; + soc->nmodes = mv98dx3236_mpp_controls[0].npins; + soc->gpioranges = mv98dx3236_mpp_gpio_ranges; + soc->ngpioranges = ARRAY_SIZE(mv98dx3236_mpp_gpio_ranges); + break; } nregs = DIV_ROUND_UP(soc->nmodes, MVEBU_MPPS_PER_REG); -- 2.11.0.24.ge6920cf ^ permalink raw reply related [flat|nested] 16+ messages in thread
[parent not found: <20170106041517.9589-4-chris.packham-6g8wRflRTwXFdCa3tKVlE6U/zSkkHjvu@public.gmane.org>]
* Re: [PATCHv3 3/5] pinctrl: mvebu: pinctrl driver for 98DX3236 SoC [not found] ` <20170106041517.9589-4-chris.packham-6g8wRflRTwXFdCa3tKVlE6U/zSkkHjvu@public.gmane.org> @ 2017-01-09 18:41 ` Rob Herring 0 siblings, 0 replies; 16+ messages in thread From: Rob Herring @ 2017-01-09 18:41 UTC (permalink / raw) To: Chris Packham Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Kalyan Kinthada, Linus Walleij, Mark Rutland, Thomas Petazzoni, Laxman Dewangan, linux-gpio-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA On Fri, Jan 06, 2017 at 05:15:00PM +1300, Chris Packham wrote: > From: Kalyan Kinthada <kalyan.kinthada-6g8wRflRTwXFdCa3tKVlE6U/zSkkHjvu@public.gmane.org> > > This pinctrl driver supports the 98DX3236, 98DX3336 and 98DX4251 SoCs > from Marvell. > > Signed-off-by: Kalyan Kinthada <kalyan.kinthada-6g8wRflRTwXFdCa3tKVlE6U/zSkkHjvu@public.gmane.org> > Signed-off-by: Chris Packham <chris.packham-6g8wRflRTwXFdCa3tKVlE6U/zSkkHjvu@public.gmane.org> > --- > Changes in v2: > - include sdio support for the 98DX4251 > Changes in v3: > - None > > .../pinctrl/marvell,armada-98dx3236-pinctrl.txt | 46 ++++++ Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> > drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 155 +++++++++++++++++++++ > 2 files changed, 201 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCHv3 3/5] pinctrl: mvebu: pinctrl driver for 98DX3236 SoC 2017-01-06 4:15 ` [PATCHv3 3/5] pinctrl: mvebu: pinctrl driver for 98DX3236 SoC Chris Packham [not found] ` <20170106041517.9589-4-chris.packham-6g8wRflRTwXFdCa3tKVlE6U/zSkkHjvu@public.gmane.org> @ 2017-01-11 14:44 ` Linus Walleij 2017-01-11 20:55 ` Sebastian Hesselbarth 1 sibling, 1 reply; 16+ messages in thread From: Linus Walleij @ 2017-01-11 14:44 UTC (permalink / raw) To: Chris Packham, Gregory CLEMENT, Thomas Petazzoni, Sebastian Hesselbarth Cc: linux-arm-kernel@lists.infradead.org, Kalyan Kinthada, Rob Herring, Mark Rutland, Laxman Dewangan, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org On Fri, Jan 6, 2017 at 5:15 AM, Chris Packham <chris.packham@alliedtelesis.co.nz> wrote: > From: Kalyan Kinthada <kalyan.kinthada@alliedtelesis.co.nz> > > This pinctrl driver supports the 98DX3236, 98DX3336 and 98DX4251 SoCs > from Marvell. > > Signed-off-by: Kalyan Kinthada <kalyan.kinthada@alliedtelesis.co.nz> > Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> I am waiting for an ACK or comment from the maintainers on this patch. Sebastian? Yours, Linus Walleij ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCHv3 3/5] pinctrl: mvebu: pinctrl driver for 98DX3236 SoC 2017-01-11 14:44 ` Linus Walleij @ 2017-01-11 20:55 ` Sebastian Hesselbarth 2017-01-12 9:13 ` Chris Packham 0 siblings, 1 reply; 16+ messages in thread From: Sebastian Hesselbarth @ 2017-01-11 20:55 UTC (permalink / raw) To: Linus Walleij, Chris Packham, Gregory CLEMENT, Thomas Petazzoni Cc: Mark Rutland, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Kalyan Kinthada, Rob Herring, Laxman Dewangan, linux-arm-kernel@lists.infradead.org On 01/11/2017 03:44 PM, Linus Walleij wrote: > On Fri, Jan 6, 2017 at 5:15 AM, Chris Packham > <chris.packham@alliedtelesis.co.nz> wrote: > >> From: Kalyan Kinthada <kalyan.kinthada@alliedtelesis.co.nz> >> >> This pinctrl driver supports the 98DX3236, 98DX3336 and 98DX4251 SoCs >> from Marvell. >> >> Signed-off-by: Kalyan Kinthada <kalyan.kinthada@alliedtelesis.co.nz> >> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> > > I am waiting for an ACK or comment from the maintainers on > this patch. Sebastian? Sorry for the ignorance. I don't have the patch to reply to inline, but: - In the driver MPP_MODE2, spi0 there is a typo "csk" instead of "sck". - MPP_MODE5 binding "dev","bootcs" and driver "dev","bootcs0" differ. - MPP_MODE6 binding "gpio" and driver "gpo" differ. - MPP_MODE17 binding "dev","clk" and driver "dev","clkout" differ. - MPP_MODE19 binding mentiones "dev","rb" but driver does not. - MPP_MODE20 binding "gpio" and driver "gpo" differ. - MPP_MODE20 binding "dev","we" and driver "dev","we0" differ. - MPP_MODE21 through MPP_MODE30 binding "gpio" and driver "gpo" differ. - remove spaces before "0, 0" in mv98dx3236_mpp_gpio_ranges. Most of it is cosmetic stuff, so if you fix it feel free to add my Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Sebastian ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCHv3 3/5] pinctrl: mvebu: pinctrl driver for 98DX3236 SoC 2017-01-11 20:55 ` Sebastian Hesselbarth @ 2017-01-12 9:13 ` Chris Packham 0 siblings, 0 replies; 16+ messages in thread From: Chris Packham @ 2017-01-12 9:13 UTC (permalink / raw) To: Sebastian Hesselbarth, Linus Walleij, Gregory CLEMENT, Thomas Petazzoni Cc: Mark Rutland, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Kalyan Kinthada, Rob Herring, Laxman Dewangan, linux-arm-kernel@lists.infradead.org On 12/01/17 09:56, Sebastian Hesselbarth wrote: > On 01/11/2017 03:44 PM, Linus Walleij wrote: >> On Fri, Jan 6, 2017 at 5:15 AM, Chris Packham >> <chris.packham@alliedtelesis.co.nz> wrote: >> >>> From: Kalyan Kinthada <kalyan.kinthada@alliedtelesis.co.nz> >>> >>> This pinctrl driver supports the 98DX3236, 98DX3336 and 98DX4251 SoCs >>> from Marvell. >>> >>> Signed-off-by: Kalyan Kinthada <kalyan.kinthada@alliedtelesis.co.nz> >>> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> >> >> I am waiting for an ACK or comment from the maintainers on >> this patch. Sebastian? > > Sorry for the ignorance. > > I don't have the patch to reply to inline, but: > > - In the driver MPP_MODE2, spi0 there is a typo "csk" instead of "sck". > - MPP_MODE5 binding "dev","bootcs" and driver "dev","bootcs0" differ. > - MPP_MODE6 binding "gpio" and driver "gpo" differ. > - MPP_MODE17 binding "dev","clk" and driver "dev","clkout" differ. > - MPP_MODE19 binding mentiones "dev","rb" but driver does not. > - MPP_MODE20 binding "gpio" and driver "gpo" differ. > - MPP_MODE20 binding "dev","we" and driver "dev","we0" differ. > - MPP_MODE21 through MPP_MODE30 binding "gpio" and driver "gpo" differ. > - remove spaces before "0, 0" in mv98dx3236_mpp_gpio_ranges. > > Most of it is cosmetic stuff, so if you fix it feel free to add my > > Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Hi Sebastian, Hopefully I can get a v4 out with the above fixed soon. One point on "gpio" vs "gpo" this one isn't a typo. Some of these pins can be driven as outputs but can't be used as inputs. From a pinctrl driver point of view there is no difference but I did want to convey that from a system design point of view if you really need something to be an input you shouldn't use one of these pins. This is also noted in the datasheets so it doesn't necessarily need repeating. If you still want me to use "gpio" in the code and binding I'm happy to do so. ^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2017-01-12 9:13 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2017-01-05 3:36 [PATCHv2 0/5] Support for Marvell switches with integrated CPUs Chris Packham
2017-01-05 3:36 ` [PATCHv2 3/5] pinctrl: mvebu: pinctrl driver for 98DX3236 SoC Chris Packham
2017-01-05 4:07 ` [PATCHv2 0/5] Support for Marvell switches with integrated CPUs Florian Fainelli
2017-01-05 4:24 ` Chris Packham
2017-01-05 13:09 ` Andrew Lunn
2017-01-05 14:07 ` Marcin Wojtas
2017-01-05 19:46 ` Chris Packham
2017-01-05 19:52 ` Florian Fainelli
2017-01-05 14:09 ` Marcin Wojtas
2017-01-05 20:02 ` Chris Packham
2017-01-06 4:14 ` Chris Packham
2017-01-06 4:15 ` [PATCHv3 3/5] pinctrl: mvebu: pinctrl driver for 98DX3236 SoC Chris Packham
[not found] ` <20170106041517.9589-4-chris.packham-6g8wRflRTwXFdCa3tKVlE6U/zSkkHjvu@public.gmane.org>
2017-01-09 18:41 ` Rob Herring
2017-01-11 14:44 ` Linus Walleij
2017-01-11 20:55 ` Sebastian Hesselbarth
2017-01-12 9:13 ` Chris Packham
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