From: Shawn Guo <shawnguo@kernel.org>
To: "A.S. Dong" <aisheng.dong@nxp.com>
Cc: Andy Duan <fugang.duan@nxp.com>, Jacky Bai <ping.bai@nxp.com>,
"linus.walleij@linaro.org" <linus.walleij@linaro.org>,
"stefan@agner.ch" <stefan@agner.ch>,
"linux-gpio@vger.kernel.org" <linux-gpio@vger.kernel.org>,
"kernel@pengutronix.de" <kernel@pengutronix.de>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH 2/5] pinctrl: imx: add soc specific mux_mode mask and shift property
Date: Mon, 15 May 2017 18:59:07 +0800 [thread overview]
Message-ID: <20170515105906.GO8471@dragon> (raw)
In-Reply-To: <AM3PR04MB306F70328E49CB7EE68E2C380E10@AM3PR04MB306.eurprd04.prod.outlook.com>
On Mon, May 15, 2017 at 09:00:32AM +0000, A.S. Dong wrote:
> > > @@ -432,7 +432,7 @@ static int imx_pinconf_get(struct pinctrl_dev
> > *pctldev,
> > > *config = readl(ipctl->base + pin_reg->conf_reg);
> > >
> > > if (info->flags & SHARE_MUX_CONF_REG)
> > > - *config &= 0xffff;
> > > + *config &= ~info->mux_mask;
> >
> > It changes the way how code works. We need a note in the commit log
> > explaining why it's safe.
> >
>
> Well, that's Vybrid tricks that BIT[15-0] are all configs part.
> So it hardcoded 0xffff there.
>
> But it's not true in ULP, so use mux_mask instead to address
> the difference.
So you make the assumption that for all SHARE_MUX_CONF_REG SoCs, all
bits in the register except mux ones are config bits. You at least need
to mention that in the commit log, IMO.
Shawn
next prev parent reply other threads:[~2017-05-15 10:59 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-05-12 12:38 [PATCH 0/5] pinctrl: imx: add generic pin config and imx7ulp support Dong Aisheng
2017-05-12 12:38 ` [PATCH 1/5] pinctrl: imx: add generic pin config core support Dong Aisheng
2017-05-15 8:35 ` Shawn Guo
2017-05-15 8:56 ` A.S. Dong
2017-05-15 10:56 ` Shawn Guo
2017-05-15 11:16 ` A.S. Dong
2017-05-15 11:56 ` Shawn Guo
2017-05-15 12:07 ` A.S. Dong
2017-05-12 12:38 ` [PATCH 2/5] pinctrl: imx: add soc specific mux_mode mask and shift property Dong Aisheng
2017-05-15 8:52 ` Shawn Guo
2017-05-15 9:00 ` A.S. Dong
2017-05-15 10:59 ` Shawn Guo [this message]
2017-05-15 11:04 ` A.S. Dong
2017-05-12 12:38 ` [PATCH 2/5] pinctrl: pinctrl-imx: " Dong Aisheng
2017-05-12 13:32 ` A.S. Dong
2017-05-12 12:38 ` [PATCH 3/5] dt-bindings: pinctrl: add imx7ulp pinctrl binding doc Dong Aisheng
2017-05-15 11:43 ` Shawn Guo
2017-05-15 12:06 ` A.S. Dong
[not found] ` <AM3PR04MB3069C90F23CF9C9CC84BA7580E10-f56W/S9L6NSIzFHTN1kKrAfhPeD8jYilXA4E9RH9d+qIuWR1G4zioA@public.gmane.org>
2017-05-15 12:20 ` Shawn Guo
2017-05-15 12:41 ` A.S. Dong
2017-05-15 12:59 ` Shawn Guo
2017-05-15 13:12 ` A.S. Dong
[not found] ` <1494592686-30967-5-git-send-email-aisheng.dong-3arQi8VN3Tc@public.gmane.org>
2017-05-15 13:31 ` Shawn Guo
2017-05-15 13:32 ` A.S. Dong
2017-05-12 12:38 ` [PATCH 4/5] pinctrl: imx: add imx7ulp driver Dong Aisheng
2017-05-12 12:38 ` [PATCH 5/5] pinctrl: imx: fix debug message for SHARE_MUX_CONF_REG case Dong Aisheng
2017-05-15 12:05 ` Shawn Guo
2017-05-15 12:08 ` A.S. Dong
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