From: Shawn Guo <shawnguo@kernel.org>
To: "Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>
Cc: Linus Walleij <linus.walleij@linaro.org>,
Fabio Estevam <fabio.estevam@nxp.com>,
kernel@pengutronix.de, linux-gpio@vger.kernel.org
Subject: Re: [PATCH] pinctrl: mxs: atomically switch mux and drive strength config
Date: Sun, 21 May 2017 16:46:12 +0800 [thread overview]
Message-ID: <20170521084611.GI26102@dragon> (raw)
In-Reply-To: <20170518092355.6735-1-u.kleine-koenig@pengutronix.de>
On Thu, May 18, 2017 at 11:23:55AM +0200, Uwe Kleine-König wrote:
> To set the mux mode of a pin two bits must be set. Up to now this is
> implemented using the following idiom:
>
> writel(mask, reg + CLR);
> writel(value, reg + SET);
>
> . This however results in the mux mode being 0 between the two writes.
>
> On my machine there is an IC's reset pin connected to LCD_D20. The
> bootloader configures this pin as GPIO output-high (i.e. not holding the
> IC in reset). When Linux reconfigures the pin to GPIO the short time
> LCD_D20 is muxed as LCD_D20 instead of GPIO_1_20 is enough to confuse
> the connected IC.
>
> The same problem is present for the pin's drive strength setting which is
> reset to low drive strength before using the right value.
>
> So instead of relying on the hardware to modify the register setting
> using two writes implement the bit toggling using read-modify-write.
>
> Fixes: 17723111e64f ("pinctrl: add pinctrl-mxs support")
> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: Shawn Guo <shawnguo@kernel.org>
next prev parent reply other threads:[~2017-05-21 8:46 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-05-18 9:23 [PATCH] pinctrl: mxs: atomically switch mux and drive strength config Uwe Kleine-König
2017-05-21 8:46 ` Shawn Guo [this message]
2017-05-23 9:28 ` Linus Walleij
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