* [PATCH v1] pinctrl: intel: merrifield: Correct UART pin lists
@ 2017-08-04 16:26 Andy Shevchenko
2017-08-05 18:50 ` Mika Westerberg
2017-08-07 13:23 ` Linus Walleij
0 siblings, 2 replies; 3+ messages in thread
From: Andy Shevchenko @ 2017-08-04 16:26 UTC (permalink / raw)
To: Linus Walleij, linux-gpio, Mika Westerberg; +Cc: Andy Shevchenko
UART pin lists consist GPIO numbers which is simply wrong.
Replace it by pin numbers.
Fixes: 4e80c8f50574 ("pinctrl: intel: Add Intel Merrifield pin controller support")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
drivers/pinctrl/intel/pinctrl-merrifield.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/pinctrl/intel/pinctrl-merrifield.c b/drivers/pinctrl/intel/pinctrl-merrifield.c
index 4d4ef42a39b5..86c4b3fab7b0 100644
--- a/drivers/pinctrl/intel/pinctrl-merrifield.c
+++ b/drivers/pinctrl/intel/pinctrl-merrifield.c
@@ -343,9 +343,9 @@ static const struct pinctrl_pin_desc mrfld_pins[] = {
static const unsigned int mrfld_sdio_pins[] = { 50, 51, 52, 53, 54, 55, 56 };
static const unsigned int mrfld_spi5_pins[] = { 90, 91, 92, 93, 94, 95, 96 };
-static const unsigned int mrfld_uart0_pins[] = { 124, 125, 126, 127 };
-static const unsigned int mrfld_uart1_pins[] = { 128, 129, 130, 131 };
-static const unsigned int mrfld_uart2_pins[] = { 132, 133, 134, 135 };
+static const unsigned int mrfld_uart0_pins[] = { 115, 116, 117, 118 };
+static const unsigned int mrfld_uart1_pins[] = { 119, 120, 121, 122 };
+static const unsigned int mrfld_uart2_pins[] = { 123, 124, 125, 126 };
static const unsigned int mrfld_pwm0_pins[] = { 144 };
static const unsigned int mrfld_pwm1_pins[] = { 145 };
static const unsigned int mrfld_pwm2_pins[] = { 132 };
--
2.13.2
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH v1] pinctrl: intel: merrifield: Correct UART pin lists
2017-08-04 16:26 [PATCH v1] pinctrl: intel: merrifield: Correct UART pin lists Andy Shevchenko
@ 2017-08-05 18:50 ` Mika Westerberg
2017-08-07 13:23 ` Linus Walleij
1 sibling, 0 replies; 3+ messages in thread
From: Mika Westerberg @ 2017-08-05 18:50 UTC (permalink / raw)
To: Andy Shevchenko; +Cc: Linus Walleij, linux-gpio
On Fri, Aug 04, 2017 at 07:26:34PM +0300, Andy Shevchenko wrote:
> UART pin lists consist GPIO numbers which is simply wrong.
> Replace it by pin numbers.
>
> Fixes: 4e80c8f50574 ("pinctrl: intel: Add Intel Merrifield pin controller support")
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v1] pinctrl: intel: merrifield: Correct UART pin lists
2017-08-04 16:26 [PATCH v1] pinctrl: intel: merrifield: Correct UART pin lists Andy Shevchenko
2017-08-05 18:50 ` Mika Westerberg
@ 2017-08-07 13:23 ` Linus Walleij
1 sibling, 0 replies; 3+ messages in thread
From: Linus Walleij @ 2017-08-07 13:23 UTC (permalink / raw)
To: Andy Shevchenko; +Cc: linux-gpio@vger.kernel.org, Mika Westerberg
On Fri, Aug 4, 2017 at 6:26 PM, Andy Shevchenko
<andriy.shevchenko@linux.intel.com> wrote:
> UART pin lists consist GPIO numbers which is simply wrong.
> Replace it by pin numbers.
>
> Fixes: 4e80c8f50574 ("pinctrl: intel: Add Intel Merrifield pin controller support")
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Patch applied for fixes with Mika's ACK.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 3+ messages in thread
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2017-08-04 16:26 [PATCH v1] pinctrl: intel: merrifield: Correct UART pin lists Andy Shevchenko
2017-08-05 18:50 ` Mika Westerberg
2017-08-07 13:23 ` Linus Walleij
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