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* [PATCH] gpio: grgpio: Do not use gc->pin2mask()
@ 2017-10-20 13:03 Linus Walleij
  2017-10-20 13:47 ` Andreas Larsson
  0 siblings, 1 reply; 2+ messages in thread
From: Linus Walleij @ 2017-10-20 13:03 UTC (permalink / raw)
  To: linux-gpio; +Cc: Linus Walleij, Andreas Larsson

The pin2mask() accessor only shuffles BIT ORDER in big endian systems,
i.e. the bitstuffing is swizzled big endian so "bit 0" is bit 7 or
bit 15 or bit 31 or so.

The grgpio only uses big endian BYTE ORDER which will be taken car of
by the ->write_reg() callback.

Just use BIT(offset) to assign the bit.

Cc: Andreas Larsson <andreas@gaisler.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
 drivers/gpio/gpio-grgpio.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpio/gpio-grgpio.c b/drivers/gpio/gpio-grgpio.c
index 6544a16ab02e..e2fc561f4315 100644
--- a/drivers/gpio/gpio-grgpio.c
+++ b/drivers/gpio/gpio-grgpio.c
@@ -35,6 +35,7 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/irqdomain.h>
+#include <linux/bitops.h>
 
 #define GRGPIO_MAX_NGPIO 32
 
@@ -96,12 +97,11 @@ static void grgpio_set_imask(struct grgpio_priv *priv, unsigned int offset,
 			     int val)
 {
 	struct gpio_chip *gc = &priv->gc;
-	unsigned long mask = gc->pin2mask(gc, offset);
 
 	if (val)
-		priv->imask |= mask;
+		priv->imask |= BIT(offset);
 	else
-		priv->imask &= ~mask;
+		priv->imask &= ~BIT(offset);
 	gc->write_reg(priv->regs + GRGPIO_IMASK, priv->imask);
 }
 
-- 
2.13.6


^ permalink raw reply related	[flat|nested] 2+ messages in thread

* Re: [PATCH] gpio: grgpio: Do not use gc->pin2mask()
  2017-10-20 13:03 [PATCH] gpio: grgpio: Do not use gc->pin2mask() Linus Walleij
@ 2017-10-20 13:47 ` Andreas Larsson
  0 siblings, 0 replies; 2+ messages in thread
From: Andreas Larsson @ 2017-10-20 13:47 UTC (permalink / raw)
  To: Linus Walleij, linux-gpio

On 2017-10-20 15:03, Linus Walleij wrote:
> The pin2mask() accessor only shuffles BIT ORDER in big endian systems,
> i.e. the bitstuffing is swizzled big endian so "bit 0" is bit 7 or
> bit 15 or bit 31 or so.
>
> The grgpio only uses big endian BYTE ORDER which will be taken car of
> by the ->write_reg() callback.
>
> Just use BIT(offset) to assign the bit.

Sure, as bgpio_init is not called with BGPIOF_BIG_ENDIAN in the flags 
argument, the pin2mask call just resulted in a BIT(offset) anyway.

Acked-by: Andreas Larsson <andreas@gaisler.com>


> Cc: Andreas Larsson <andreas@gaisler.com>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
>   drivers/gpio/gpio-grgpio.c | 6 +++---
>   1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpio/gpio-grgpio.c b/drivers/gpio/gpio-grgpio.c
> index 6544a16ab02e..e2fc561f4315 100644
> --- a/drivers/gpio/gpio-grgpio.c
> +++ b/drivers/gpio/gpio-grgpio.c
> @@ -35,6 +35,7 @@
>   #include <linux/interrupt.h>
>   #include <linux/irq.h>
>   #include <linux/irqdomain.h>
> +#include <linux/bitops.h>
>
>   #define GRGPIO_MAX_NGPIO 32
>
> @@ -96,12 +97,11 @@ static void grgpio_set_imask(struct grgpio_priv *priv, unsigned int offset,
>   			     int val)
>   {
>   	struct gpio_chip *gc = &priv->gc;
> -	unsigned long mask = gc->pin2mask(gc, offset);
>
>   	if (val)
> -		priv->imask |= mask;
> +		priv->imask |= BIT(offset);
>   	else
> -		priv->imask &= ~mask;
> +		priv->imask &= ~BIT(offset);
>   	gc->write_reg(priv->regs + GRGPIO_IMASK, priv->imask);
>   }
>
>


^ permalink raw reply	[flat|nested] 2+ messages in thread

end of thread, other threads:[~2017-10-20 14:09 UTC | newest]

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