From mboxrd@z Thu Jan 1 00:00:00 1970 From: Maxime Ripard Subject: Re: [RFC PATCH v3 07/17] clocksource: sun4i: add a compatible for suniv Date: Thu, 22 Nov 2018 09:36:15 +0100 Message-ID: <20181122083615.2ksgpvmfllbqnfiu@flea> References: <60bc70fc43743f664de76abf3ab0a01cd7924458.1542824904.git.mesihkilinc@gmail.com> Reply-To: maxime.ripard-LDxbnhwyfcJBDgjK7y7TUQ@public.gmane.org Mime-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="7qqjbx4ddugpjz3t" Return-path: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org Content-Disposition: inline In-Reply-To: <60bc70fc43743f664de76abf3ab0a01cd7924458.1542824904.git.mesihkilinc-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Mesih Kilinc Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org, Chen-Yu Tsai , Russell King , Daniel Lezcano , Marc Zyngier , Linus Walleij , Icenowy Zheng , Rob Herring , Julian Calaby List-Id: linux-gpio@vger.kernel.org --7qqjbx4ddugpjz3t Content-Type: text/plain; charset="UTF-8" Content-Disposition: inline On Wed, Nov 21, 2018 at 09:30:40PM +0300, Mesih Kilinc wrote: > The suniv (new F-series) chip has a timer with less functionality than > the A10 timer, e.g. it has only 3 channels. > > Add a new compatible for it. As we didn't use the extra channels on A10 > either now, the code needn't to be changed. > > The suniv chip is based on ARM926EJ-S CPU, thus it has no architecture timer. > > Register sun4i_timer as sched_clock on it. > > Signed-off-by: Mesih Kilinc Acked-by: Maxime Ripard Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com --7qqjbx4ddugpjz3t--