From mboxrd@z Thu Jan 1 00:00:00 1970 From: Maxime Ripard Subject: Re: [PATCH v6 16/17] ARM: dts: suniv: add initial DTSI file for F1C100s Date: Mon, 3 Dec 2018 10:01:27 +0100 Message-ID: <20181203090127.enxxh5ah7eehbql7@flea> References: Reply-To: maxime.ripard-LDxbnhwyfcJBDgjK7y7TUQ@public.gmane.org Mime-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="cgoydzqpbnyatpx4" Return-path: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org Content-Disposition: inline In-Reply-To: List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Mesih Kilinc Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org, Chen-Yu Tsai , Russell King , Daniel Lezcano , Marc Zyngier , Linus Walleij , Icenowy Zheng , Rob Herring , Julian Calaby List-Id: linux-gpio@vger.kernel.org --cgoydzqpbnyatpx4 Content-Type: text/plain; charset="UTF-8" Content-Disposition: inline On Sun, Dec 02, 2018 at 11:23:50PM +0300, Mesih Kilinc wrote: > F1C100s is one product with the suniv die, which has a 32MiB co-packaged > DDR1 DRAM chip. As we have the support for suniv pin controller and CCU now, add a > initial DTSI for it. > > Signed-off-by: Mesih Kilinc Applied, thanks! Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com --cgoydzqpbnyatpx4--