From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?UTF-8?Q?=27Ond=C5=99ej_Jirman=27_via_linux=2Dsunxi?= Subject: Re: [PATCH 10/12] pinctrl: sunxi: Support I/O bias voltage setting on H6 Date: Mon, 8 Apr 2019 03:31:24 +0200 Message-ID: <20190408013124.y7rvhmmwsqw3i2mz@core.my.home> References: <20190405234514.6183-1-megous@megous.com> <20190405234514.6183-11-megous@megous.com> Reply-To: megous-5qf/QAjKc83QT0dZR+AlfA@public.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Return-path: Content-Disposition: inline In-Reply-To: <20190405234514.6183-11-megous-5qf/QAjKc83QT0dZR+AlfA@public.gmane.org> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org, Maxime Ripard , Chen-Yu Tsai , Rob Herring , Linus Walleij Cc: Mark Rutland , David Airlie , Chi-Hsien Lin , dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, linux-stm32-XDFAJ8BFU24N7RejjzZ/Li2xQDfSxrLKVpNB7YpNyf8@public.gmane.org, brcm80211-dev-list-+wT8y+m8/X5BDgjK7y7TUQ@public.gmane.org, Jose Abreu , Naveen Gupta , devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Arend van Spriel , Alexandre Torgue , Hante Meuleman , linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Wright Feng , Giuseppe Cavallaro , linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, Franky Lin , Maxime Coquelin , brcm80211-dev-list.pdl-dY08KVG/lbpWk0Htik3J/w@public.gmane.org, netdev-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-wireless-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Kalle Valo , Daniel Vetter List-Id: linux-gpio@vger.kernel.org On Sat, Apr 06, 2019 at 01:45:12AM +0200, verejna wrote: > From: Ondrej Jirman > > H6 SoC has a "pio group withstand voltage mode" register (datasheet > description), that needs to be used to select either 1.8V or 3.3V > I/O mode, based on what voltage is powering the respective pin > banks and is thus used for I/O signals. > > Add support for configuring this register according to the voltage > of the pin bank regulator (if enabled). > > This is similar to the support for I/O bias voltage setting patch > for A80 and the same concerns apply. (see commit 402bfb3c135213dc > Support I/O bias voltage setting on A80). > > Signed-off-by: Ondrej Jirman > --- > drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c | 1 + > drivers/pinctrl/sunxi/pinctrl-sunxi.c | 14 ++++++++++++++ > drivers/pinctrl/sunxi/pinctrl-sunxi.h | 3 +++ > 3 files changed, 18 insertions(+) > > diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c > index ef4268cc6227..30b1befa8ed8 100644 > --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c > +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c > @@ -591,6 +591,7 @@ static const struct sunxi_pinctrl_desc h6_pinctrl_data = { > .irq_banks = 4, > .irq_bank_map = h6_irq_bank_map, > .irq_read_needs_mux = true, > + .io_bias_cfg_variant = IO_BIAS_CFG_V2, > }; > > static int h6_pinctrl_probe(struct platform_device *pdev) > diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c > index 9f329fec77cf..59a4ed396d92 100644 > --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c > +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c > @@ -607,6 +607,8 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl, > unsigned pin, > struct regulator *supply) > { > + unsigned short bank = pin / PINS_PER_BANK; > + unsigned long flags; > u32 val, reg; > int uV; > > @@ -639,6 +641,18 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl, > reg = readl(pctl->membase + sunxi_grp_config_reg(pin)); > reg &= ~IO_BIAS_MASK; > writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin)); > + } else if (pctl->desc->io_bias_cfg_variant == IO_BIAS_CFG_V2) { > + val = uV <= 1800000 ? 1 : 0; > + > + dev_info(pctl->dev, > + "Setting voltage bias to %sV on bank P%c\n", > + val ? "1.8" : "3.3", 'A' + bank); I'll drop this logging in v2. I forgot it here, after testing the patch. o. > + raw_spin_lock_irqsave(&pctl->lock, flags); > + reg = readl(pctl->membase + PIO_POW_MOD_SEL_REG); > + reg &= ~(1 << bank); > + writel(reg | val << bank, pctl->membase + PIO_POW_MOD_SEL_REG); > + raw_spin_unlock_irqrestore(&pctl->lock, flags); > } > > return 0; > diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h > index 476772f91dba..3a66376f141b 100644 > --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h > +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h > @@ -95,7 +95,10 @@ > #define PINCTRL_SUN7I_A20 BIT(7) > #define PINCTRL_SUN8I_R40 BIT(8) > > +#define PIO_POW_MOD_SEL_REG 0x340 > + > #define IO_BIAS_CFG_V1 1 > +#define IO_BIAS_CFG_V2 2 > > struct sunxi_desc_function { > unsigned long variant; > -- > 2.21.0 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel