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From: Stephen Boyd <sboyd@kernel.org>
To: Sowjanya Komatineni <skomatineni@nvidia.com>,
	jason@lakedaemon.net, jonathanh@nvidia.com,
	linus.walleij@linaro.org, marc.zyngier@arm.com,
	mark.rutland@arm.com, stefan@agner.ch, tglx@linutronix.de,
	thierry.reding@gmail.com
Cc: pdeschrijver@nvidia.com, pgaikwad@nvidia.com,
	linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org,
	jckuo@nvidia.com, josephl@nvidia.com, talho@nvidia.com,
	linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
	mperttunen@nvidia.com, spatra@nvidia.com, robh+dt@kernel.org,
	devicetree@vger.kernel.org
Subject: Re: [PATCH V2 03/12] clk: tegra: save and restore PLLs state for system
Date: Wed, 05 Jun 2019 16:31:22 -0700	[thread overview]
Message-ID: <20190605233123.AC6DD2083E@mail.kernel.org> (raw)
In-Reply-To: <f5fd9068-134a-3343-9cca-94db67cd748f@nvidia.com>

Quoting Sowjanya Komatineni (2019-05-31 12:52:44)
> 
> On 5/29/19 4:28 PM, Stephen Boyd wrote:
> > Quoting Sowjanya Komatineni (2019-05-28 16:08:47)
> >> +               WARN_ON(1);
> >> +               return;
> >> +       }
> >> +
> >> +       parent_rate = clk_hw_get_rate(parent);
> >> +
> >> +       if (clk_frac_div_set_rate(hw, rate, parent_rate) < 0)
> >> +               WARN_ON(1);
> >> +}
> >> +#endif
> >> diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
> >> index 09bccbb9640c..e4d124cc5657 100644
> >> --- a/drivers/clk/tegra/clk.h
> >> +++ b/drivers/clk/tegra/clk.h
> >> @@ -841,6 +841,15 @@ int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div);
> >>   int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width,
> >>                   u8 frac_width, u8 flags);
> >>   
> >> +#ifdef CONFIG_PM_SLEEP
> > Can you remove this ifdef? It just complicates compilation testing.
> OK, Will fix in next version
> >> +void tegra_clk_pll_resume(struct clk *c, unsigned long rate);
> >> +void tegra_clk_divider_resume(struct clk_hw *hw, unsigned long rate);
> >> +void tegra_clk_pll_out_resume(struct clk *clk, unsigned long rate);
> >> +void tegra_clk_plle_tegra210_resume(struct clk *c);
> >> +void tegra_clk_sync_state_pll(struct clk *c);
> >> +void tegra_clk_sync_state_pll_out(struct clk *clk);
> > Do these APIs need to operate on struct clk? Why can't they operate on
> > clk_hw or why can't we drive the suspend/resume sequence from the clk
> > provider driver itself?
> >
> Yes can change to use clk_hw.
> 
> By clk provider driver, are you referring to clk-tegra210?

I guess so.

> 
> clk-terga210 driver has suspend/resume implementation. These API's are 
> for corresponding clock specific implementations (clk-pll, clk-pll-out, 
> clk-divider) for enabling and restoring to proper rate and are invoked 
> during clk-tegra210 driver resume.

Yes, so when the clk provider suspends it needs to do something? Our
handling of clk rates and other state like enable/disable over
suspend/resume isn't really well thought out or implemented so far. TI
has some code to do some stuff, but otherwise I haven't seen drivers
handling this. Ideally it would be something generic in the framework so
that drivers don't have to work around stuff.

  reply	other threads:[~2019-06-05 23:31 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-05-28 23:08 [PATCH V2 00/12] LP0 entry and exit support for Tegra210 Sowjanya Komatineni
2019-05-28 23:08 ` [PATCH V2 01/12] irqchip: tegra: do not disable COP IRQ during suspend Sowjanya Komatineni
2019-05-29 14:21   ` Thierry Reding
2019-05-28 23:08 ` [PATCH V2 02/12] pinctrl: tegra: add suspend and resume support Sowjanya Komatineni
2019-05-29 15:29   ` Dmitry Osipenko
2019-05-29 18:14     ` Sowjanya Komatineni
2019-05-29 19:32       ` Dmitry Osipenko
2019-05-29 20:11         ` Sowjanya Komatineni
2019-05-29 20:47           ` Dmitry Osipenko
2019-05-29 20:56             ` Sowjanya Komatineni
2019-05-29 21:07               ` Sowjanya Komatineni
2019-05-29 21:25               ` Dmitry Osipenko
2019-05-29 21:27                 ` Sowjanya Komatineni
2019-05-29 21:33                   ` Dmitry Osipenko
2019-05-28 23:08 ` [PATCH V2 03/12] clk: tegra: save and restore PLLs state for system Sowjanya Komatineni
2019-05-29 23:28   ` Stephen Boyd
2019-05-31 19:52     ` Sowjanya Komatineni
2019-06-05 23:31       ` Stephen Boyd [this message]
2019-05-28 23:08 ` [PATCH V2 04/12] clk: tegra: add support for peripheral clock suspend and resume Sowjanya Komatineni
2019-05-29 23:30   ` Stephen Boyd
2019-05-31 19:55     ` Sowjanya Komatineni
2019-05-28 23:08 ` [PATCH V2 05/12] clk: tegra: add support for OSC clock resume Sowjanya Komatineni
2019-05-28 23:08 ` [PATCH V2 06/12] clk: tegra: add suspend resume support for DFLL clock Sowjanya Komatineni
2019-06-04 12:41   ` Peter De Schrijver
2019-05-28 23:08 ` [PATCH V2 07/12] clk: tegra: support for Tegra210 clocks suspend-resume Sowjanya Komatineni
2019-06-06 18:17   ` Stephen Boyd
2019-06-06 19:13     ` Sowjanya Komatineni
2019-05-28 23:08 ` [PATCH V2 08/12] soc/tegra: pmc: allow support for more tegra wake models Sowjanya Komatineni
2019-05-29 14:30   ` Thierry Reding
2019-05-28 23:08 ` [PATCH V2 09/12] soc/tegra: pmc: add pmc wake support for tegra210 Sowjanya Komatineni
2019-05-29  5:42   ` JC Kuo
2019-05-29 13:52   ` Thierry Reding
2019-05-28 23:08 ` [PATCH V2 10/12] gpio: tegra: implement wake event support for Tegra210 and prior GPIO Sowjanya Komatineni
2019-05-29 14:03   ` Thierry Reding
2019-06-01  8:28     ` Sowjanya Komatineni
2019-05-28 23:08 ` [PATCH V2 11/12] arm64: tegra: enable wake from deep sleep on RTC alarm Sowjanya Komatineni
2019-05-28 23:08 ` [PATCH V2 12/12] soc/tegra: pmc: configure tegra deep sleep control settings Sowjanya Komatineni
2019-05-29 14:05   ` Thierry Reding
2019-05-29 14:12 ` [PATCH V2 00/12] LP0 entry and exit support for Tegra210 Thierry Reding
2019-06-04 13:47 ` Peter De Schrijver

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