From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Boyd Subject: Re: [PATCH] pinctrl: qcom: Clear status bit on irq_unmask Date: Mon, 10 Jun 2019 07:51:32 -0700 Message-ID: <20190610145132.DD1132085A@mail.kernel.org> References: <1559285512-27784-1-git-send-email-tengfeif@codeaurora.org> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org To: Bjorn Andersson , Linus Walleij , Niklas Cassel , Tengfei Fan Cc: Andy Gross , David Brown , MSM , "open list:GPIO SUBSYSTEM" , "linux-kernel@vger.kernel.org" List-Id: linux-gpio@vger.kernel.org Quoting Linus Walleij (2019-06-07 14:08:10) > On Fri, May 31, 2019 at 8:52 AM Tengfei Fan wro= te: >=20 > > The gpio interrupt status bit is getting set after the > > irq is disabled and causing an immediate interrupt after > > enablling the irq, so clear status bit on irq_unmask. > > > > Signed-off-by: Tengfei Fan >=20 > This looks pretty serious, can one of the Qcom maintainers ACK > this? >=20 > Should it be sent to fixes and even stable? >=20 > Fixes: tag? >=20 How is the interrupt status bit getting set after the irq is disabled? It looks like this is a level type interrupt? I thought that after commit b55326dc969e ("pinctrl: msm: Really mask level interrupts to prevent latching") this wouldn't be a problem. Am I wrong, or is qcom just clearing out patches on drivers and this is the last one that needs to be upstreamed?