From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B2EECA9EC6 for ; Wed, 30 Oct 2019 15:31:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 151E62173E for ; Wed, 30 Oct 2019 15:31:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726963AbfJ3Pby (ORCPT ); Wed, 30 Oct 2019 11:31:54 -0400 Received: from mga18.intel.com ([134.134.136.126]:51306 "EHLO mga18.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726501AbfJ3Pby (ORCPT ); Wed, 30 Oct 2019 11:31:54 -0400 X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 30 Oct 2019 08:31:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,247,1569308400"; d="scan'208";a="211349110" Received: from lahna.fi.intel.com (HELO lahna) ([10.237.72.157]) by fmsmga001.fm.intel.com with SMTP; 30 Oct 2019 08:31:50 -0700 Received: by lahna (sSMTP sendmail emulation); Wed, 30 Oct 2019 17:31:49 +0200 Date: Wed, 30 Oct 2019 17:31:49 +0200 From: Mika Westerberg To: Linus Walleij Cc: linux-gpio@vger.kernel.org, Bartosz Golaszewski , Andy Shevchenko , Hans de Goede Subject: Re: [PATCH] gpio/pinctrl: Add pin ranges before gpiochip Message-ID: <20191030153149.GH2593@lahna.fi.intel.com> References: <20191030144940.21133-1-linus.walleij@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20191030144940.21133-1-linus.walleij@linaro.org> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo User-Agent: Mutt/1.12.1 (2019-06-15) Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org On Wed, Oct 30, 2019 at 03:49:40PM +0100, Linus Walleij wrote: > This fixes a semantic ordering issue as we need to add > pin ranges before adding gpiochips when gpiochips use > pin control as a backend: as it needs to talk to the > pin control backend during initialization, the backend > needs to be there already. > > Other drivers in the tree using pincontrol as backend do > not necessarily have this problem, as they might not need > to access the pincontrol portions during initialization. > > Cc: Andy Shevchenko > Cc: Mika Westerberg > Reported-by: Hans de Goede > Signed-off-by: Linus Walleij Looks good to me as well. Are you going to take this? In that case Acked-by: Mika Westerberg