From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.3 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3E9CCA9EC6 for ; Wed, 30 Oct 2019 16:10:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BE926217F9 for ; Wed, 30 Oct 2019 16:10:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726800AbfJ3QKq (ORCPT ); Wed, 30 Oct 2019 12:10:46 -0400 Received: from mga03.intel.com ([134.134.136.65]:47204 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726175AbfJ3QKq (ORCPT ); Wed, 30 Oct 2019 12:10:46 -0400 X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 30 Oct 2019 09:10:45 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,247,1569308400"; d="scan'208";a="211356119" Received: from lahna.fi.intel.com (HELO lahna) ([10.237.72.157]) by fmsmga001.fm.intel.com with SMTP; 30 Oct 2019 09:10:42 -0700 Received: by lahna (sSMTP sendmail emulation); Wed, 30 Oct 2019 18:10:41 +0200 Date: Wed, 30 Oct 2019 18:10:41 +0200 From: Mika Westerberg To: Linus Walleij Cc: Hans de Goede , "open list:GPIO SUBSYSTEM" , Bartosz Golaszewski , Andy Shevchenko Subject: Re: [PATCH] gpio/pinctrl: Add pin ranges before gpiochip Message-ID: <20191030161041.GI2593@lahna.fi.intel.com> References: <20191030144940.21133-1-linus.walleij@linaro.org> <0e8c15d9-c805-c1ee-f8f0-528866c7ac1c@redhat.com> <9d21b3fe-852b-a430-4e71-af0742edcd9b@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo User-Agent: Mutt/1.12.1 (2019-06-15) Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org On Wed, Oct 30, 2019 at 05:04:21PM +0100, Linus Walleij wrote: > On Wed, Oct 30, 2019 at 5:01 PM Hans de Goede wrote: > > > For 5.4 we should probably revert > > "gpio: merrifield: Pass irqchip when adding gpiochip" > > and the fixes added on top of it, since AFAICT _AEI handling > > will be broken on merrifield after this change too. > > > > So I suggest that we revert the following commits (in revert order): > > > > 4c87540940cbc7ddbe9674087919c605fd5c2ef1 "gpio: merrifield: Move hardware initialization to callback" > > 6658f87f219427ee776c498e07c878eb5cad1be2 "gpio: merrifield: Restore use of irq_base" > > 8f86a5b4ad679e4836733b47414226074eee4e4d "gpio: merrifield: Pass irqchip when adding gpiochip" > > > > That seems like the safest thing to do at this point in the cycle. > > OK are the Intel people OK with this? I'm fine but I'll leave this to Andy since that's his stuff. > If so I'll go and revert them. > > Mika: will any of the pin control fixes you sent collide with > this? (I guess not...) No they should not, they don't touch the merrifield driver.