From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Bartosz Golaszewski <bgolaszewski@baylibre.com>,
Linus Walleij <linus.walleij@linaro.org>,
linux-gpio@vger.kernel.org,
Mika Westerberg <mika.westerberg@linux.intel.com>,
Hans de Goede <hdegoede@redhat.com>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
Thierry Reding <treding@nvidia.com>
Subject: [PATCH v2 7/7] pinctrl: baytrail: Pass irqchip when adding gpiochip
Date: Tue, 5 Nov 2019 22:35:57 +0200 [thread overview]
Message-ID: <20191105203557.78562-8-andriy.shevchenko@linux.intel.com> (raw)
In-Reply-To: <20191105203557.78562-1-andriy.shevchenko@linux.intel.com>
We need to convert all old gpio irqchips to pass the irqchip
setup along when adding the gpio_chip. For more info see
drivers/gpio/TODO.
For chained irqchips this is a pretty straight-forward conversion.
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Mika Westerberg <mika.westerberg@linux.intel.com>
Cc: Thierry Reding <treding@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
drivers/pinctrl/intel/pinctrl-baytrail.c | 43 ++++++++++++++----------
1 file changed, 25 insertions(+), 18 deletions(-)
diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c
index b4d0e945e8c2..1234fe5f2a27 100644
--- a/drivers/pinctrl/intel/pinctrl-baytrail.c
+++ b/drivers/pinctrl/intel/pinctrl-baytrail.c
@@ -1450,9 +1450,9 @@ static void byt_init_irq_valid_mask(struct gpio_chip *chip,
*/
}
-static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
+static int byt_gpio_irq_init_hw(struct gpio_chip *chip)
{
- struct gpio_chip *gc = &vg->chip;
+ struct byt_gpio *vg = gpiochip_get_data(chip);
struct device *dev = &vg->pdev->dev;
void __iomem *reg;
u32 base, value;
@@ -1476,7 +1476,7 @@ static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
value = readl(reg);
if (value & BYT_DIRECT_IRQ_EN) {
- clear_bit(i, gc->irq.valid_mask);
+ clear_bit(i, chip->irq.valid_mask);
dev_dbg(dev, "excluding GPIO %d from IRQ domain\n", i);
} else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i)) {
byt_gpio_clear_triggering(vg, i);
@@ -1504,6 +1504,8 @@ static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
"GPIO interrupt error, pins misconfigured. INT_STAT%u: 0x%08x\n",
base / 32, value);
}
+
+ return 0;
}
static int byt_gpio_add_pin_ranges(struct gpio_chip *chip)
@@ -1542,26 +1544,31 @@ static int byt_gpio_probe(struct byt_gpio *vg)
if (!vg->saved_context)
return -ENOMEM;
#endif
- ret = devm_gpiochip_add_data(&vg->pdev->dev, gc, vg);
- if (ret) {
- dev_err(&vg->pdev->dev, "failed adding byt-gpio chip\n");
- return ret;
- }
/* set up interrupts */
irq_rc = platform_get_resource(vg->pdev, IORESOURCE_IRQ, 0);
if (irq_rc && irq_rc->start) {
- byt_gpio_irq_init_hw(vg);
- ret = gpiochip_irqchip_add(gc, &byt_irqchip, 0,
- handle_bad_irq, IRQ_TYPE_NONE);
- if (ret) {
- dev_err(&vg->pdev->dev, "failed to add irqchip\n");
- return ret;
- }
+ struct gpio_irq_chip *girq;
+
+ girq = &gc->irq;
+ girq->chip = &byt_irqchip;
+ girq->init_hw = byt_gpio_irq_init_hw;
+ girq->parent_handler = byt_gpio_irq_handler;
+ girq->num_parents = 1;
+ girq->parents = devm_kcalloc(&vg->pdev->dev, 1,
+ sizeof(*girq->parents),
+ GFP_KERNEL);
+ if (!girq->parents)
+ return -ENOMEM;
+ girq->parents[0] = (unsigned int)irq_rc->start;
+ girq->default_type = IRQ_TYPE_NONE;
+ girq->handler = handle_bad_irq;
+ }
- gpiochip_set_chained_irqchip(gc, &byt_irqchip,
- (unsigned)irq_rc->start,
- byt_gpio_irq_handler);
+ ret = devm_gpiochip_add_data(&vg->pdev->dev, gc, vg);
+ if (ret) {
+ dev_err(&vg->pdev->dev, "failed adding byt-gpio chip\n");
+ return ret;
}
return ret;
--
2.24.0.rc1
next prev parent reply other threads:[~2019-11-05 20:36 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-05 20:35 [RESEND][PATCH v2 0/7] gpiolib: fix GPIO <-> pin mapping registration Andy Shevchenko
2019-11-05 20:35 ` [PATCH v2 1/7] gpiolib: Switch order of valid mask and hw init Andy Shevchenko
2019-11-05 20:35 ` [PATCH v2 2/7] gpiolib: No need to call gpiochip_remove_pin_ranges() twice Andy Shevchenko
2019-11-05 20:35 ` [PATCH v2 3/7] gpiolib: Introduce ->add_pin_ranges() callback Andy Shevchenko
2019-11-06 13:51 ` Mika Westerberg
2019-11-13 9:46 ` Linus Walleij
2019-11-13 13:22 ` Andy Shevchenko
2019-11-13 17:25 ` Linus Walleij
2019-11-13 17:47 ` Andy Shevchenko
2019-11-05 20:35 ` [PATCH v2 4/7] gpio: merrifield: Add GPIO <-> pin mapping ranges via callback Andy Shevchenko
2019-11-06 13:54 ` Mika Westerberg
2019-11-06 16:52 ` Andy Shevchenko
2019-11-05 20:35 ` [PATCH v2 5/7] gpio: merrifield: Pass irqchip when adding gpiochip Andy Shevchenko
2019-11-06 13:56 ` Mika Westerberg
2019-11-05 20:35 ` [PATCH v2 6/7] pinctrl: baytrail: Add GPIO <-> pin mapping ranges via callback Andy Shevchenko
2019-11-06 13:56 ` Mika Westerberg
2019-11-05 20:35 ` Andy Shevchenko [this message]
2019-11-06 14:00 ` [PATCH v2 7/7] pinctrl: baytrail: Pass irqchip when adding gpiochip Mika Westerberg
2019-11-06 11:59 ` [RESEND][PATCH v2 0/7] gpiolib: fix GPIO <-> pin mapping registration Hans de Goede
2019-11-06 17:30 ` Andy Shevchenko
2019-11-08 9:40 ` Linus Walleij
2019-11-08 13:39 ` Andy Shevchenko
2019-11-13 9:43 ` Linus Walleij
2019-11-13 13:28 ` Andy Shevchenko
2019-11-13 13:37 ` Andy Shevchenko
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