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Sat, 04 Jan 2020 13:35:05 -0800 (PST) Received: from rob-hp-laptop ([64.188.179.251]) by smtp.gmail.com with ESMTPSA id q1sm22416757ils.60.2020.01.04.13.35.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 04 Jan 2020 13:35:05 -0800 (PST) Received: from rob (uid 1000) (envelope-from rob@rob-hp-laptop) id 2219b7 by rob-hp-laptop (DragonFly Mail Agent v0.11); Sat, 04 Jan 2020 14:33:32 -0700 Date: Sat, 4 Jan 2020 14:33:32 -0700 From: Rob Herring To: Anson Huang Cc: aisheng.dong@nxp.com, festevam@gmail.com, shawnguo@kernel.org, stefan@agner.ch, kernel@pengutronix.de, linus.walleij@linaro.org, mark.rutland@arm.com, s.hauer@pengutronix.de, catalin.marinas@arm.com, will@kernel.org, bjorn.andersson@linaro.org, olof@lixom.net, maxime@cerno.tech, leonard.crestez@nxp.com, dinguyen@kernel.org, marcin.juszkiewicz@linaro.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Linux-imx@nxp.com Subject: Re: [PATCH V2 1/3] dt-bindings: imx: Add pinctrl binding doc for i.MX8MP Message-ID: <20200104213332.GA19211@bogus> References: <1577342743-25885-1-git-send-email-Anson.Huang@nxp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1577342743-25885-1-git-send-email-Anson.Huang@nxp.com> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org On Thu, Dec 26, 2019 at 02:45:41PM +0800, Anson Huang wrote: > Add binding doc for i.MX8MP pinctrl driver. > > Signed-off-by: Anson Huang > --- > No changes. > --- > .../bindings/pinctrl/fsl,imx8mp-pinctrl.txt | 38 + Please make this a DT schema. > arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h | 931 +++++++++++++++++++++ > 2 files changed, 969 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx8mp-pinctrl.txt > create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h > > diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mp-pinctrl.txt > new file mode 100644 > index 0000000..619104b > --- /dev/null > +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mp-pinctrl.txt > @@ -0,0 +1,38 @@ > +* Freescale IMX8MP IOMUX Controller > + > +Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory > +for common binding part and usage. > + > +Required properties: > +- compatible: "fsl,imx8mp-iomuxc" > +- reg: should contain the base physical address and size of the iomuxc > + registers. > + > +Required properties in sub-nodes: > +- fsl,pins: each entry consists of 6 integers and represents the mux and config > + setting for one pin. The first 5 integers + input_val> are specified using a PIN_FUNC_ID macro, which can be found in > + . The last integer CONFIG is > + the pad setting value like pull-up on this pin. Please refer to i.MX8M Plus > + Reference Manual for detailed CONFIG settings. > + > +Examples: > + > +&uart1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart1>; > +}; > + > +iomuxc: pinctrl@30330000 { > + compatible = "fsl,imx8mp-iomuxc"; > + reg = <0x30330000 0x10000>; > + > + pinctrl_uart1: uart1grp { In particular, define some node naming pattern that you can match on. Perhaps "grp$" works. > + fsl,pins = < > + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 > + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 > + MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140 > + MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 > + >; > + }; > +};