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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id 7sm7090318pfc.203.2020.05.18.18.39.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 May 2020 18:39:36 -0700 (PDT) Date: Mon, 18 May 2020 18:38:13 -0700 From: Bjorn Andersson To: Mayank Grover , linus.walleij@linaro.org Cc: agross@kernel.org, linux-gpio@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, neeraju@codeaurora.org Subject: Re: [PATCH] pinctrl: msm: Add check for pinctrl group is valid Message-ID: <20200519013813.GU2165@builder.lan> References: <1589817025-21886-1-git-send-email-groverm@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1589817025-21886-1-git-send-email-groverm@codeaurora.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org On Mon 18 May 08:50 PDT 2020, Mayank Grover wrote: > The list of reserved gpio pins for platform are populated > in gpiochip valid_mask. > > Here on MSM common driver introduce ability to check if > pingroup is valid, by parsing pins in pingroup against > reserved pins for gpios. This does not handle non-gpio > pingroups. > Thanks Mayank, I can confirm that this is a problem, but don't we need this on some of the pinmux_ops as well? @Linus, we started off with something similar for GPIOs and ended up with the logic in the core code. Should we somehow try to do the same for pinctrl? Regards, Bjorn > Signed-off-by: Mayank Grover > --- > drivers/pinctrl/qcom/pinctrl-msm.c | 26 ++++++++++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c > index 85858c1..b6ebe26 100644 > --- a/drivers/pinctrl/qcom/pinctrl-msm.c > +++ b/drivers/pinctrl/qcom/pinctrl-msm.c > @@ -261,6 +261,24 @@ static unsigned msm_regval_to_drive(u32 val) > return (val + 1) * 2; > } > > +static bool msm_pingroup_is_valid(struct msm_pinctrl *pctrl, > + const struct msm_pingroup *g) > +{ > + const unsigned int *pins = g->pins; > + unsigned int num_pins = g->npins; > + struct gpio_chip *chip = &pctrl->chip; > + unsigned int max_gpios = chip->ngpio; > + unsigned int i; > + > + for (i = 0; i < num_pins; i++) { > + /* Doesn't handle non-gpio pingroups */ > + if (pins[i] < max_gpios && > + !gpiochip_line_is_valid(chip, pins[i])) > + return false; > + } > + return true; > +} > + > static int msm_config_group_get(struct pinctrl_dev *pctldev, > unsigned int group, > unsigned long *config) > @@ -276,6 +294,10 @@ static int msm_config_group_get(struct pinctrl_dev *pctldev, > > g = &pctrl->soc->groups[group]; > > + /* Check if group has all valid pins */ > + if (!msm_pingroup_is_valid(pctrl, g)) > + return -EINVAL; > + > ret = msm_config_reg(pctrl, g, param, &mask, &bit); > if (ret < 0) > return ret; > @@ -355,6 +377,10 @@ static int msm_config_group_set(struct pinctrl_dev *pctldev, > > g = &pctrl->soc->groups[group]; > > + /* Check if group has all valid pins */ > + if (!msm_pingroup_is_valid(pctrl, g)) > + return -EINVAL; > + > for (i = 0; i < num_configs; i++) { > param = pinconf_to_config_param(configs[i]); > arg = pinconf_to_config_argument(configs[i]); > -- > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a > member of the Code Aurora Forum, hosted by The Linux Foundation